CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic

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1 CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational network change, the output changes. X = x x 2... x n Z = z z 2... z m x x 2 z z 2 x n z m Page 2 of 77

2 UAH Chapter CPE/EE 422/522. Combinational Logic - Basic Logic Gates Page 3 of 77 UAH Chapter CPE/EE 422/522. Combinational Logic - Full Adder (Minterm Form) Module m-form Sum = Cout = Sum = Cout = Truth table X Y Cin Cout Sum Page 4 of 77 2

3 UAH Chapter CPE/EE 422/522. Combinational Logic - Full Adder (Maxterm Form) Sum = Sum = Cout = Cout = Module Truth table X Y Cin Cout Sum Sum = Cout = m-form Page 5 of 77 UAH Chapter CPE/EE 422/522.2 Boolean Algebra and Algebraic Simplification Some routines are widely used and been pooled into subroutine libraries. Operating systems are programs that manage the resources of a computer for the benefit of the programs that run on that machine Software Categories Systems - OS, compilers, assemblers, etc. Applications - spreadsheets, text editors, etc. Page 6 of 77 3

4 UAH Chapter CPE/EE 422/522.3 More Boolean Algebra and Algebraic Simplification Page 7 of 77 UAH Chapter CPE/EE 422/522.2 Boolean Algebra with Exclusive OR X = X' X = X X X = X X' = X Y = Y X (Commutative law) ( X Y) Z = X (Y Z) X(Y Z) = XY XZ ( X Y)' = X Y' = X' Y = XY + (Distributive law) X' Y' Page 8 of 77 4

5 UAH Chapter CPE/EE 422/522.3 Karnaugh Maps Convenient way to simplify logic functions of 3, 4, 5, (6) variables Four-variable K-map Each square d adjacent cells Page 9 of 77 UAH Chapter CPE/EE 422/522.3 Karnaugh Maps - Examples C C B B A A D D Page of 77 5

6 UAH Chapter CPE/EE 422/522.3 Karnaugh Maps - Sum of Products Function consists of a sum of Prime implicant Prime implicant is if it contains a that is not contained in any other prime implicant Page of 77 UAH Chapter CPE/EE 422/522.3 Karnaugh Maps - Prime Implicant Selection Two minimum forms f = f = C B A D Page 2 of 77 6

7 UAH Chapter CPE/EE 422/522.3 Karnaugh Maps - Selection Procedure. Choose a ( ) that has not been covered yet 2. Find all _s and s adjacent to that minterm. (Check the n adjacent squares on an n-variable map.) 3. If a single term covers the minterm and all the adjacent s and ds, then that term is an prime implicant, so select that term. 4. Repeat steps, 2, 3 until all essential prime implicants have been chosen 5. Find a set of prime implicants that cover the remaining s on the map. If there is more than one such set, choose a set with a Page 3 of 77 UAH Chapter CPE/EE 422/522.4 Designing with NAND and NOR Gates Implementation of NAND and NOR gates is easier than that of AND and OR gates (e.g., CMOS) Page 4 of 77 7

8 UAH Chapter CPE/EE 422/522.4 Designing with NAND and NOR Gates (continued) Any logic function can be realized using only NAND or NOR gates - : : a : ab: a+b: Page 5 of 77 UAH Chapter CPE/EE 422/522.4 Designing with NAND and NOR Gates - Conversion to NOR Gates Start with POS ( ) circle s in K-maps Find network of OR and AND gates Page 6 of 77 8

9 UAH Chapter CPE/EE 422/522.4 Designing with NANDand NOR Gates - Conversion to NAND Gates Start with SOP (Sum of Products) circle s in K-maps Find network of OR and AND gates Page 7 of 77 UAH Chapter CPE/EE 422/522.3 Tristate Logic and Busses Four kinds of tristate buffers B is a control input used to enable and disable the output Page 8 of 77 9

10 UAH Chapter CPE/EE 422/522.3 Tristate Logic and Busses - Data Transfer Page 9 of 77 UAH Chapter CPE/EE 422/522.6 Flip-Flops and Latches Sequential Networks Have memory (state) Present state depends not only on the, but also on all previous inputs (history) Future state depends on the and x x 2 Q z z 2 x n Z ( t ) = Q ( t ) = + F ( X ( t ), Q ( t )) G ( X ( t ), Q ( t )) z m Flip-flops are commonly used as storage devices: D-FF, JK-FF, T-FF Page 2 of 77

11 UAH Chapter CPE/EE 422/522.6 Flip-Flops and Latches - Clocked D Flip- Flop with Rising-edge Trigger Next state The next state in response to the of the clock is equal to the input before the rising edge Page 2 of 77 UAH Chapter CPE/EE 422/522.6 Flip-Flops and Latches Clocked JK Flip-Flop JK = => JK = => JK = => JK = => Next state Page 22 of 77

12 UAH Chapter CPE/EE 422/522.6 Flip-Flops and Latches Clocked T Flip-Flop T = => T = => Next state Page 23 of 77 UAH CPE/EE 422/522 Chapter.6 Flip-Flops and Latches S-R Latch Page 24 of 77 2

13 UAH Chapter CPE/EE 422/522.6 Flip-Flops and Latches Transparent D Latch Page 25 of 77 UAH CPE/EE 422/522 Chapter.6 Flip-Flops and Latches Transparent D Latch Page 26 of 77 3

14 UAH Chapter CPE/EE 422/522.7 Mealy Sequential Network Design General Model of Mealy Sequential Machine () X inputs are changed to a new value (2) After a delay, the Z outputs and next state appear at the output of CN (3) The next state is clocked into the state register and the state changes Page 27 of 77 UAH Chapter CPE/EE 422/522.7 Mealy Sequential Network Design BCD to Excess3 BCD Code Converter Example x Q z t3 X (inputs) t2 t t t3 Z (outputs) t2 t t Page 28 of 77 4

15 UAH Chapter CPE/EE 422/522.7 Mealy Sequential Network Design State Graph and Table for Code Converter Page 29 of 77 UAH Chapter CPE/EE 422/522.9 Equivalent States and Reduction of State Tables Code Converter Example Page 3 of 77 5

16 UAH Chapter CPE/EE 422/522.9 Equivalent States and Reduction of State Tables Code Converter Transition Table NS Z PS X = X = X= X = S S S2 S3 S4 S5 S6 Q+Q2+Q3+ Z QQ2Q3 X = X = X= X = Page 3 of 77 UAH Chapter CPE/EE 422/522.9 Equivalent States and Reduction of State Tables Code Converter K-maps Q2 Q2 X Q X Q Q3 Q2 Q3 Q2 X Q X Q Q3 Q3 Page 32 of 77 6

17 UAH Chapter CPE/EE 422/522.9 Equivalent States and Reduction of State Tables Code Converter Realization Page 33 of 77 UAH Chapter CPE/EE 422/522. Sequential Network Timing Code Converter Code converter X = _ => Z = _ Page 34 of 77 7

18 UAH Chapter CPE/EE 422/522. Sequential Network Timing Timing Diagram for Code Converter Timing diagram assuming a propagation delay of ns for each flip-flop and gate (State has been replaced with the state of three flip-flops) Page 35 of 77 UAH Chapter CPE/EE 422/522. Setup and Hold Times D Flip-Flop For a real D-FF D input must be stable for a certain amount of time before the active edge of clock cycle => D input must be stable for a certain amount of time after the active edge of the clock => Propagation time: from the time the clock changes to the time the output changes Manufacturers provide minimum t su, t h, and maximum t plh, t phl Page 36 of 77 8

19 t t UAH Chapter CPE/EE 422/522. Setup and Hold Times Maximum Clock Frequency Calculation c max p max t ck t c max ck - Max propagation delay through the combinational network - Max propagation delay from the time the clock changes to the flip-flop output changes { = max(t plh, t phl )} - Clock period + t c max p max t ck t t + t + p max t t su su Example: t p max t gate = 5 = 5 ns ns, t su = 5 ns, t ck f max = 2 * 5 = 5 ns = = 2 MHz 5 ns Page 37 of 77 UAH Chapter CPE/EE 422/522. Setup and Hold Times Hold Time Violations (from Q) Occurs if the change in Q that is fed back through the combinational network causes input D to change too soon after the clock edge Hold time is satisfied if: t p min + t c min t h t c min t p min -Min propagation delay through - the combinational network - Min propagation delay from - the time the clock changes to - the flip-flop output changes - { = min(t plh, t phl )} Page 38 of 77 9

20 UAH Chapter CPE/EE 422/522. Setup and Hold Times Setup Time Violations (from X) Occurs if the change in X that is fed back through the combinational network causes input D to change too soon after the clock edge t t + x cx max t su -Max propagation delay through t cx max -the combinational network from - input X (or any other input) to -the flip-flop input D Page 39 of 77 UAH Chapter CPE/EE 422/522. Setup and Hold Times Hold Time Violations (from X) Occurs if the change in X that is fed back through the combinational network causes input D to change too soon after the clock edge Make sure that X does not change too soon after the clock. If X changes at time t y after the active edge, hold time is satisfied if t y t h t cx min t cx min -Min propagation delay -through the combinational -network from input X (or any -other input) to the flip-flop input D Page 4 of 77 2

21 UAH Chapter CPE/EE 422/522 Synchronous Design Use a clock to synchronize the operation of all flipflops, registers, and counters in the system all changes occur immediately following the active clock edge clock period must be long enough so that all changes flip-flops, registers, counters will have time to stabilize before the next active clock edge Typical design: Control section + Data Section Page 4 of 77 UAH Chapter CPE/EE 422/522 Synchronous Design Example Data section // s= n*(n+a) // R=n, R2=a // R=s Design flowchart for SMUL operation Design Control section S S F B B C B + C A + B BR LD(BR) DEC(BR) + LD(R) RD(R) 6 6 ld dec BR rd ld rd LD(L) CL(L) RD(BR) C6 LD(A) R ld cl 6 ld L A 6 6 ALU F F A B R2 6 rd cl 6 ld rd RD(A) CL(A) S S C LD(R2) RD(R2) 6 Page 42 of 77 2

22 UAH Chapter CPE/EE 422/522 Moore Sequential Networks Outputs depend only on present state! X = x x 2... x n Q = Q Q 2... Q k Z = z z 2... z m x x 2 Q z z 2 x n Z ( t ) = + Q ( t ) = F ( Q ( t )) G ( X ( t ), Q ( t )) z m Page 43 of 77 UAH Chapter General Model of CPE/EE 422/522 Moore Sequential Machine Outputs depend only on present state! Combinational Network Outputs(Z) Inputs(X) Combinational Network Next State State Register State(Q) Clock X = x x 2... x n + Q ( t ) = G ( X ( t ), Q ( t )) Q = Q Q 2... Q k Z = z Z ( t ) = F ( Q ( t )) z 2... z m Page 44 of 77 22

23 UAH Chapter CPE/EE 422/522 Code Converter: Moore Machine Page 45 of 77 UAH Chapter CPE/EE 422/522 Moore Machine: State Table PS NS X= X= S S S2 S S3 S4 S2 S4 S5 S3 S6 S7 S4 S7 S8 S5 S7 S8 S6 S9 S S7 S9 S S8 S - S9 S S2 S S S2 Z N C N C S N S C C 3 S 6 S 9 N C N C N C St art S S 4 S C 7 S C S 2 C S 8 S 5 Page 46 of 77 23

24 UAH Chapter CPE/EE 422/522 Moore Machine Timing X = _ => Z = _ Moore Mealy Page 47 of 77 UAH Chapter CPE/EE 422/522 State Assignments Rule I: (S, S9, S), (S4, S5), (S6, S7) Rule II: (S, S2), (S3, S4), (S4, S5), (S6, S7), (S7, S8), (S9, S) Rule III: (S, S2, S4, S6, S8, S9) (S, S3, S5, S7, S) S S -. S - PS S S S2 S3 S4 S5 S6 S7 S8 S9 S NS Z X= X= S S2 S3 S4 S4 S5 S6 S7 S7 S8 S7 S8 S9 S S9 S S - S S2 S S2 Page 48 of 77 24

25 UAH Chapter CPE/EE 422/522 State Assignments PS X= NS X= Z Q A Q B Q C Q D Q A Q B Q C Q D Q A Q B Q C Q D Page 49 of 77 UAH Chapter CPE/EE 422/522 Logic Reduction Q A Q B X \ Q C Q D Q A Q B X \ Q C Q D Q A+ = Q D + Q A Q B Q C Q B+ = Q C + Q B Q D +X Q A Q D +Q A Q B + XQ A Page 5 of 77 25

26 UAH Chapter CPE/EE 422/522 Logic Reduction Q A Q X \ B Q C Q D Q A Q X \ B Q C Q D Q D+ = X Q A + Q A Q B Q C Q C+ = X Q D + X Q A +Q A Q C + Q A Q B +Q B Q D Page 5 of 77 UAH Chapter CPE/EE 422/522 Logic Reduction Q A Q B Q C Q D Z = Q A Q B Q C + Q A Q B Q C +Q C Q D +Q B Q D Page 52 of 77 26

27 UAH Chapter CPE/EE 422/522 Altera Logic Implementation Page 53 of 77 UAH Chapter CPE/EE 422/522 Altera Simulation Reset Portion X = _ => Z = _ Page 54 of 77 27

28 UAH Chapter CPE/EE 422/522 Moore Machine: Another Example NRZ to Manchester Converter Coding schemes for serial data transmission NRZ: NRZI: in input sequence in input sequence RZ: return-to-zero ; Manchester Page 55 of 77 UAH Chapter CPE/EE 422/522 NRZ-to-Manchester Converter: Timing Page 56 of 77 28

29 UAH Chapter CPE/EE 422/522 NRZ-to-Manchester: State Diagram and Table Page 57 of 77 UAH Chapter CPE/EE 422/522.2 Synchronous Design: Control Signal Timing Issues Change in state of the flip-flops in control section determined by the propagation delay Time control signals change depend upon this FF propagation delay and combinational network delay Glitches and spikes may occur in the control signals due to hazards in the network Noise may be introduced on the control signals by changing signals in another part of the circuit THIS MEANS THAT THERE IS A TIME INTERVAL AFTER THE ACTIVE EDGE OF THE CLOCK WHERE THE STATE OF THE CONTROL SIGNAL IS NOT KNOWN AND MAY NOT BE STABLE Page 58 of 77 29

30 UAH Chapter CPE/EE 422/522.2 Synchronous Design: Timing Chart for System with Falling-edge Devices Page 59 of 77 UAH CPE/EE 422/522 Chapter.2 Synchronous Design: Timing Chart for System with Rising-edge Devices Page 6 of 77 3

31 UAH Chapter CPE/EE 422/522 Principles of Synchronous Design Method All clock inputs to flip-flops, registers, counters, etc., are driven directly from the system clock or from the clock ANDed with a control signal Result All state changes occur immediately following the active edge of the clock signal Advantage All switching transients, switching noise, etc., occur between the clock pulses and have no effect on system performance Page 6 of 77 UAH Chapter CPE/EE 422/522 Asynchronous Design Disadvantage - More difficult Problems Race conditions: Hazards Special design techniques are needed to cope with races and hazards Advantages = Disadvantages of Synchronous Design In high-speed synchronous design propagation delay in wiring is significant => clock signal must be carefully routed so that it reaches all devices at essentially same time Inputs are not synchronous with the clock need for synchronizers Clock cycle is determined by the worst-case delay Page 62 of 77 3

32 UAH Chapter CPE/EE 422/522 Equivalent States Two state are equivalent if we cannot tell them apart by observing input and output sequences Definition: Two states are equivalent s i ==s j if and only if, for every input sequence X, the output sequences Z and Z2 are the same. Page 63 of 77 UAH Chapter CPE/EE 422/522 Equivalent States State Equivalence Theorem Two state are equivalent S i == S j if and only if for every single input X, the outputs are the same and the next states are equivalent Page 64 of 77 32

33 UAH Chapter CPE/EE 422/522 Implication Table Method. Construct a chart that contains a square for each pair of states. 2. Compare each pair in the state table. If the outputs associated with states i and j are different, place an X in square i-j to indicate that i!=j. If outputs are the same, place the implied pairs in square i-j. If outputs and next states are the same (or i-j implies only itself), i==j. 3. Go through the implication table square by square. If square i-j contains the implied pair m-n, and square m- n contains X, then i!=j, and place X in square i-j. 4. If any Xs were added in step 3, repeat step 3 until no more Xs are added. 5. For each square i-j that does not contain an X, i==j. Page 65 of 77 UAH Chapter CPE/EE 422/522 State Table Reduction ) States a and h have the same next states and outputs (when X= and X=) 2) Eliminate h from the table and replace with a 3) States a and b have the same output => they are same iff c==d and f==e. We say c-d and e-f are implied pairs for a-b. To keep track of the implied pairs we make an implication chart. Page 66 of 77 33

34 UAH Chapter CPE/EE 422/522 State Table Reduction 4) Make another pass through the chart. E-g cell contains c-e and b-g; since c-e cell contains x, c!=e => e!=g (put X). 5) Repeat the step 4 until no additional squares are X- ed. {Put X in f-g, a-c, a-d, b-c, b-d squares}. 6) The remaining squares indicate equivalent state pairs => a==b, c==d, e==f. Page 67 of 77 UAH Chapter CPE/EE 422/522 Hazards in Combinational Networks What are hazards in Combinational Networks? Unwanted switching transients at the output (glitches) Example ABC =, B changes to Assume each gate has propagation delay of ns Page 68 of 77 34

35 UAH Chapter CPE/EE 422/522 Hazards in Combinational Networks Occur when different paths from input to output have different propagation delays Static -hazard a network output momentarily go to when it should remain a constant Static -hazard a network output momentarily go to when it should remain a constant Dynamic hazard if an output change three or more times, when the output is supposed to change from to ( to ) Page 69 of 77 UAH Chapter CPE/EE 422/522 Hazards in Combinational Circuits Why do we care about hazards? Combinational networks don t care the network will function correctly Synchronous sequential networks don t care - the input signals must be stable within setup and hold time of flip-flops Asynchronous sequential networks hazards can cause the network to enter an incorrect state circuitry that generates the next-state variables must be hazard-free Power consumption is proportional to the number of transitions Page 7 of 77 35

36 UAH Chapter CPE/EE 422/522 Detection of Static and Hazards Page 7 of 77 UAH Chapter CPE/EE 422/522 Hazards in Combinational Circuits AB C AB C f = AB' + BC f = AB' + BC + AC To avoid hazards: every pair of adjacent s should be covered by a -term Page 72 of 77 36

37 UAH Chapter CPE/EE 422/522 Detection of Static Hazards Each product term of F t is called a -term. The -terms of F t are plotted on a Karnaugh map If two s in adjacent squares on the map of F t are covered by the same -term, changing the input to the network between the corresponding two input states cannot cause a hazard. If two s in adjacent squares on the map are not covered by a single -term, a hazard is present. Page 73 of 77 UAH Chapter CPE/EE 422/522 Detection of Static Hazards Page 74 of 77 37

38 UAH Chapter CPE/EE 422/522 Detection of Static Hazards Page 75 of 77 UAH Chapter CPE/EE 422/522 Detection of Static Hazards Page 76 of 77 38

39 UAH Chapter CPE/EE 422/522 Design of Hazard Free Networks Page 77 of 77 39

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