Chapter 6. Synchronous Sequential Circuits
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1 Chapter 6 Synchronous Sequential Circuits
2 In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs. In a sequential circuit, the values of the outputs depend on the past behavior of the circuit, as well as the present values of its inputs. A sequential circuit has states, which in conjunction with the present values of inputs determine its behavior.
3 Sequential circuits can be:! Synchronous where flip-flops are used to implement the states, and a clock signal is used to control the operation! Asynchronous where no clock is used
4 W Combinational circuit Flip-flops Q Combinational circuit Z Clock Figure 6.1. The general form of a synchronous sequential circuit.
5 If the outputs depend only on the present state, the circuit is said to be of Moore type. If the outputs depend on both the present state and the present values of the inputs, the circuit is said to be of Mealy type.
6 Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : z : Figure 6.2. Sequences of input and output signals.
7 Reset w = 0 A z = 0 w = 1 w = 0 B z = 0 w = 0 w = 1 C z = 1 w = 1 Figure 6.3. State diagram of a simple sequential circuit.
8 Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1 Figure 6.4. State table for the sequential circuit in Figure 6.3.
9 w Combinational circuit Y 1 y 1 Combinational circuit z Y 2 y 2 Clock Figure 6.5. A general sequential circuit with input w, output z, state flip-flops. and two
10 The present state variables, y 1 and y 2, determine the present state of the circuit. The next state variables, Y 1 and Y 2, determine the state into which the circuit will go after the next active edge of the clock signal.
11 Present Next state state w = 0 w = 1 Output z y y Y Y Y Y A B C dd dd d Figure 6.6. State-assigned table for the sequential circuit in Figure 6.4.
12 y 2 y 1 w Ignoring don't cares Using don't cares d 0 Y = wy y Y = wy y d 0 w y 2 y d 0 Y = wy y + wy y Y = wy + wy d 1 = w ( y + y ) 1 2 y 1 y z = y y 1 2 z = y d Figure 6.7. Derivation of logic expressions for the sequential circuit in Figure 6.6.
13 Figure 6.8. Final implementation of the sequential circuit derived in Figure 6.7.
14 Clock w y 1 y 2 z t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 Figure 6.9. Timing diagram for the circuit in Figure 6.8.
15 Design steps: 1. Obtain the specification of the desired circuit. 2. Derive a state diagram. 3. Derive the corresponding state table. 4. Reduce the number of states if possible. 5. Decide on the number of state variables. 6. Choose the type of flip-flops to be used. 7. Derive the logic expressions needed to implement the circuit.
16 Figure System for Example 6.1.
17 w = 0 A No transfer Reset w = 1 B R 2 out = 1, R 3 in = 1 w = 0 w = 1 w = 0 w = 1 C R 1 out = 1, R 2 in = 1 w = 0 w = 1 D R 3 out = 1, R 1 in = 1, Done = 1 Figure State diagram for Example 6.1.
18 Present Next state Outputs state w = 0 w = 1 A A B B C C C D D D A A Figure State table for Example 6.1.
19 Present state Next state Outputs A B C D Figure State-assigned table for the sequential circuit in Figure 6.12.
20 w y 2 y Y 1 = wy 1 + y 1 y 2 w y 2 y Y 2 = y 1 y 2 + y 1 y 2 Figure Derivation of next-state expressions for the sequential circuit in Figure 6.13.
21 Figure Final implementation of sequential circuit in Figure 6.13.
22 Next state Present state w = 0 w = 1 Output z y 2 y 1 Y 2 Y 1 Y 2 Y 1 A B C dd dd d Figure Improved state assignment for the sequential circuit 6.4. in Figure
23 Y 2 D Q y 2 z Q w Y 1 D Q y 1 Clock Q Resetn Figure Final circuit for the improved state assignment in Figure 6.16.
24 Present state Nextstate Outputs A B C D Figure Improved state assignment for the sequential circuit in Figure 6.12.
25 w y 2 y Y 1 = wy 2 + y 1 y 2 w y 2 y Y 2 = y 1 Figure Derivation of next-state expressions for the sequential circuit in Figure 6.18.
26 Present Nextstate state w = 0 w = 1 Output y 3 y 2 y z 1 Y 3 Y 2 Y 1 Y 3 Y 2 Y 1 A B C Figure One-hot state assignment for the sequential circuit 6.4. in Figure
27 Present state Nextstate Outputs A B C D Figure One-hot state assignment for the sequential Figure circuit in
28 Clock cycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w : z : Figure Sequences of input and output signals.
29 Reset w = 1 z = 0 w = 0 z = 0 A B w = 1 z = 1 w = 0 z = 0 Figure State diagram of an FSM that realizes the task in Figure
30 Present Next state Output z state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 Figure State table for the FSM in Figure 6.23.
31 Present Next state Output state w = 0 w = 1 w = 0 w = 1 y Y Y z z A B Figure State-assigned table for the FSM in Figure 6.24.
32 z w D Q y Clock Q Resetn (a) Circuit Clock w y z t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 (b) Timing diagram Figure Implementation of FSM in Figure 6.25.
33 Figure Circuit that implements the specification in Figure 6.2.
34 w = 0 A Reset w = 1 R2 out = 1, R3 in = 1 B w = 0 w = 1 R1 out = 1, R2 in = 1 C w = 0 w = 1 R3 out = 1, R1 in = 1, Done = 1 Figure State diagram for Example 6.4.
35 module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit y) case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx; endcase // Define the sequential block Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; // Define output assign z = (y = = C); endmodule Figure Verilog code for the FSM in Figure 6.3.
36 Please see portrait orientation PowerPoint file for Chapter 6 Figure Implementation of the FSM of Figure 6.3 in a CPLD.
37 Resetn w Gnd Clock EPM7032 z V DD Figure The circuit from Figure 6.30 in a small CPLD.
38 Figure Simulation results for the circuit in Figure 6.30.
39 module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output reg z; reg [2:1] y, Y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the next state combinational circuit y) begin case (y) A: if (w) Y = B; else Y = A; B: if (w) Y = C; else Y = A; C: if (w) Y = C; else Y = A; default: Y = 2'bxx; endcase z = (y = = C); //Define output end // Define the sequential block Resetn, posedge Clock) if (Resetn = = 0) y <= A; else y <= Y; endmodule Figure Second version of code for the FSM in Figure 6.3.
40 module simple (Clock, Resetn, w, z); input Clock, Resetn, w; output z; reg [2:1] y; parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define the sequential block Resetn, posedge Clock) if (Resetn = = 0) y <= A; else case (y) A: if (w) y <= B; else y <= A; B: if (w) y <= C; else y <= A; C: if (w) y <= C; else y <= A; default: y <= 2'bxx; endcase // Define output assign z = (y = = C); endmodule Figure Third version of code for the FSM in Figure 6.3.
41 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the FSM in Figure 6.11.
42 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the Mealy machine of Figure 6.23.
43 Figure Simulation results for the Mealy machine.
44 Figure Potential problem with asynchronous inputs to a Mealy FSM.
45 A Shift register a Adder FSM s Shift register Shift register b Sum = A + B B Clock Figure Block diagram for the serial adder.
46 Reset ( ab s ) G H G: H: carry-in = 0 carry-in = 1 Figure State diagram for the serial adder FSM.
47 Present Next state Output s state ab = G G G G H H G H H H Figure State table for the serial adder FSM.
48 Next state Output Present state ab = y Y s Figure State-assigned table for Figure 6.41.
49 a b Full adder Y carry-out D Q y s Clock Q Reset Figure Circuit for the adder FSM in Figure 6.39.
50 Reset 00 G 0 s = 0 11 H 0 s = G 1 s = 1 00 H 1 s = 1 11 Figure State diagram for the Moore-type serial adder FSM.
51 Present Nextstate Output state ab = s G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1 Figure State table for the Moore-type serial adder FSM.
52 Nextstate Present state ab = Output y 2 y 1 s Y 2 Y Figure State-assigned table for Figure 6.45.
53 a b Full adder Sum bit Carry-out Y 1 D Q Q y 1 s Y 2 D Q y 2 Clock Q Reset Figure Circuit for the Moore-type serial adder FSM.
54 module shiftrne (R, L, E, w, Clock, Q); parameter n = 8; input [n-1:0] R; input L, E, w, Clock; output reg [n-1:0] Q; integer k; Clock) if (L) Q <= R; else if (E) begin for (k = n-1; k > 0; k = k-1) Q[k-1] <= Q[k]; Q[n-1] <= w; end endmodule Figure Code for a left-to-right shift register with an enable input.
55 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the serial adder.
56 Please see portrait orientation PowerPoint file for Chapter 6 Figure Synthesized serial adder.
57 Equivalence of states Two states S i and S j are said to be equivalent if and only if for every possible input sequence, the same output sequence will be produced regardless of whether S i or S j is the initial state.
58 Present Next state Output state w = 0 w = 1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Figure State table for Example 6.6.
59 Present Nextstate Output state w = 0 w = 1 z A B C 1 B A F 1 C F C 0 F C A 0 Figure Minimized state table for Example 6.6.
60 Clock sense N sense D N D (a) Timing diagram N sense N D Q D Q Clock Q Q (b) Circuit that generates N Figure Signals for the vending machine.
61 DN DN DN S1 0 Reset DN DN D N DN S4 1 N S2 0 S3 0 D S7 1 D DN N S5 1 S6 0 DN DN N D S8 1 S9 1 Figure State diagram for Example 6.7.
62 Present Next state Output state DN = z S1 S1 S3 S2 0 S2 S2 S4 S5 0 S3 S3 S6 S7 0 S4 S1 1 S5 S3 1 S6 S6 S8 S9 0 S7 S1 1 S8 S1 1 S9 S3 1 Figure State table for Example 6.7.
63 Present Next state Output state DN = z S1 S1 S3 S2 0 S2 S2 S4 S5 0 S3 S3 S2 S4 0 S4 S1 1 S5 S3 1 Figure Minimized state table for Example 6.7.
64 DN S1 0 DN N D S3 0 DN N DN DN S2 0 D S5 1 N S4 1 D Figure Minimized state diagram for Example 6.7.
65 DN 0 S1 N 0 D 1 DN 0 N 1 S3 D 0 N 0 D 1 S2 DN 0 Figure Mealy-type FSM for Example 6.7.
66 Present Next state Output z state w = 0 w = 1 w = 0 w = 1 A B C 0 0 B D 0 C F E 0 1 D B G 0 0 E F C 0 1 F E D 0 1 G F 0 Figure Incompletely specified state table for Example 6.8.
67 w = 0 w = 0 w = 0 w = 0 w = 1 w = 1 w = 1 A/0 B/1 C/2 D/3 w = 1 w = 1 H/7 w = 1 G/6 w = 1 F/5 w = 1 E/4 w = 0 w = 0 w = 0 w = 0 Figure State diagram for the counter.
68 Present Next state state w = 0 w = 1 Output A A B 0 B B C 1 C C D 2 D D E 3 E E F 4 F F G 5 G G H 6 H H A 7 Figure State table for the counter.
69 Next state Present Count state w = 0 w = 1 y 2 y 1 y 0 z 2 z 1 z 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 A B C D E F G H Figure State-assigned table for the counter.
70 y 1 y 0 y 1 y 0 wy 2 wy Y 0 = wy 0 + wy 0 Y 1 = wy 1 + y 1 y 0 + wy 0 y 1 y 1 y 0 wy Y 2 = wy 2 + y 0 y 2 + y 1 y 2 + w y 0 y 1 y 2 Figure Karnaugh maps for D flip-flops for the counter.
71 Please see portrait orientation PowerPoint file for Chapter 6 Figure Circuit diagram for the counter implemented with D flip-flops.
72 Flip-flop inputs Present Count state w = 0 w = 1 y 2 y 1 y 0 z 2 z 1 z 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 A d 0d 0d 001 0d 0d 1d 000 B d 0d d d 1d d1 001 C d d0 0d 011 0d d0 1d 010 D d d0 d d d1 d1 011 E d0 0d 0d 101 d0 0d 1d 100 F d0 0d d0 110 d0 1d d1 101 G d0 d0 0d 111 d0 d0 1d 110 H d0 d0 d0 000 d1 d1 d1 111 Figure Excitation table for the counter with JK flip-flops.
73 Please see portrait orientation PowerPoint file for Chapter 6 Figure Karnaugh maps for JK flip-flops in the counter.
74 w J Q y 0 K Q J Q y 1 K Q J Q y 2 K Q Clock Resetn Figure Circuit diagram using JK flip-flops.
75 w J Q y 0 K Q J Q y 1 K Q J Q y 2 K Q Clock Resetn Figure Factored-form implementation of the counter.
76 Present Next Output state state z 2 z 1 z 0 A B 000 B C 100 C D 010 D E 110 E F 001 F G 101 G H 011 H A 111 Figure State table for the counterlike example.
77 Present Next Output state state y 2 y 1 y 0 Y 2 Y 1 Y 0 z 2 z 1 z Figure State-assigned table for Figure 6.69.
78 D Q z 2 Q D Q z 1 Q D Q z 0 w Q Figure Circuit for Figure 6.70.
79 Reset 000 Idle 0xx 1xx gnt1 g 1 = 1 x0x 1xx 01x gnt2 g 2 = 1 xx0 x1x 001 gnt3 g 3 = 1 xx1 Figure State diagram for the arbiter.
80 Reset r 1 r 2 r 3 Idle r 1 r 1 gnt1 g 1 = 1 r 2 r 1 r 1 r 2 gnt2 g 2 = 1 r 3 r 2 r 1 r 2 r 3 gnt3 g 3 = 1 r 3 Figure Alternative style of state diagram for the arbiter.
81 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the arbiter.
82 Y 1 D Q y 1 z w Q Y 2 D Q y 2 Clock Q Resetn Figure Circuit for Example 6.9.
83 Next State Present Output state w = 0 w = 1 y 2 y 1 z Y 2 Y 1 Y 2 Y Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A D 0 D A D 1 (a) State-assigned table (b) State table Figure Tables for the circuit in Example 6.75.
84 w J 1 J Q y 1 z K 1 K Q Clock J 2 K 2 J K Q Q y 2 Resetn Figure Circuit for Example 6.10.
85 Present Flip-flop inputs state w = 0 w = 1 Output y 2 y 1 z J 2 K 2 J 1 K 1 J 2 K 2 J 1 K Figure The excitation table for the circuit in Figure 6.77.
86 w D 1 D Q y 1 z Q T 2 T Q y 2 Clock Q Resetn Figure Circuit for Example 6.11.
87 Present Flip-flop inputs Output state w = 0 w = 1 y 2 y 1 z T 2 D 1 T 2 D Figure Excitation table for the circuit in Figure 6.79.
88 State name Output signals or actions (Moore type) 0 (False) Condition 1 (True) expression (a) State box (b) Decision box Conditional outputs or actions (Mealy type) (c) Conditional output box Figure Elements used in ASM charts.
89 Please see portrait orientation PowerPoint file for Chapter 6 Figure ASM chart for the FSM in Figure 6.3.
90 Reset A 0 w 1 B z 0 1 w Figure ASM chart for the FSM in Figure 6.23.
91 Reset Idle r gnt1 g 1 1 r 1 0 r gnt2 g 2 1 r r 3 gnt3 g 3 1 r 3 0 Figure ASM chart for the arbiter FSM in Figure 6.73.
92 w 1 z 1 Inputs w n Combinational circuit z m Outputs y k Y k Present-state variables Next-state variables y 1 Y 1 Figure The general model for a sequential circuit.
93 Figure State diagram for Example 6.12.
94 Figure State table for the FSM in Figure 6.86.
95 Figure State-assigned table for the FSM in Figure 6.87.
96 Figure An improved state assignment for the FSM in Figure 6.87.
97 Figure FSM that detects a sequence of two zeros.
98 Figure State diagram for Example 6.14.
99 Figure State table for the FSM in Figure 6.91.
100 Figure State-assigned table for the FSM in Figure 6.92.
101 Figure Excitation table for the FSM in Figure 6.89 with JK flip-flops.
102 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the FSM in Figure 6.86.
103 Please see portrait orientation PowerPoint file for Chapter 6 Figure Verilog code for the FSM in Figure 6.91.
104 Figure Parallel-to-serial converter.
105 Please see portrait orientation PowerPoint file for Chapter 6 Figure FSM for parity generation.
106 Present Next state state w = 0 w = 1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z Figure P6.1. State-assigned table for Problems 6.1 and 6.2.
107 w D Q z Clock Q D Q Q Figure P6.2. Circuit for Problem 6.29.
Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1
W Combinational circuit Flip-flops Combinational circuit Z cycle: t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t : : Figure 8.. The general form of a sequential circuit. Figure 8.2. Sequences of input and output
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