FSM Optimization. Counter Logic Diagram Q1 Q2 Q3. Counter Implementation using RS FF 10/13/2015

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Virginia Donna Wilkinson
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1 /3/5 CS: Digital Design FSM Optimization A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Outline Last Class: Comb. Cirt. Complexity (CCC) Optimization JK FF gives the best: For next State logic FSM : Type of Machine Moore: depends on State Mealy: depends on State FSM : State minimization ow Implication Method, Implication chart method, FSM Partitioning FSM Encoding: andom, Sequential, Gray, One Hot, Oriented, Heuristics FF Counter Logic Diagram 3 FF Logic Network 3 J= 3 K= J= 3 K= J3= K3= Counter Implementation using D FF D = FF D C D C D C D = + 3 D 3 = + 3 Same as FSM Controller equire more Logic as JK FF Based Counter Implementation using T FF 3 FF T C T C T C T = + 3 T = + 3 T 3 = + 3 Still equire more Logic as JK FF Based Counter Implementation using S FF 3 FF S C S C S C S = 3 = S = 3 = S 3 = 3 3 = 3 equire more Logic as JK FF Based

2 /3/5 FSM Types Two main types of FSMs 7 Moore FSM : output is only function of state Mealy FSM: output is function of state and inputs Set Theoretic Description Moore Machineis an ordered quintuple M o o r e = S, I, O, δ, λ where ( ) S = Finiteit set of states tt Φ I= Finite set of inputs Φ O = Finite set of outputs Φ, { s,s, L,s n,{ i,i, L,i m,{ o,o, L,o δ = Next state function w hich maps S I S λ= function w hich maps S O l Set Theoretic Description Mealy Machineis an ordered quintuple Mealy = where ( S, I, O, δ, β ) S = Finiteit set of states tt Φ, I = Finite set of inputs Φ, O = Finite set of outputs Φ β = function which maps { s,s, L,sn { i, i, L, im,{ o, o, L, o δ = Next state function which maps l S I S S I O Clocked synchronous FSM Clocked All storage elements employ a clock input (i.e. all storage elements are flipflops) Synchronous All of the flip flops use the same clock signal Clocked synchronous FSM FSM State machine is simply another name for sequential circuits. Finite refers to the fact that the number of states the circuit can assume if finite AsyncFSM: A synchronous clocked FSM changes state only when a triggering edge (or tick) occurs on the clock signal Clocked synchronous FSM structure States: determined by possible values in sequential storage elements Transitions: change of state Clock: controls when state can change by controlling storage elements I nputs Current State or State Combinational Logic Storage Elements s t Next State Clock

/3/5 Moore machine Mealy machine A Much better name of State Memory is State Storage Inputs Next State Logic F Excitation State Memory Current State OutPutLogic F s Inputs Next State Logic F

3 /3/5 Moore machine Mealy machine A Much better name of State Memory is State Storage Inputs Next State Logic F Excitation State Memory Current State OutPutLogic F s Inputs Next State Logic F Excitation State Memory Current State OutPutLogic F s Clock Signal s Next state = F (current state, inputs) = G (current state) Out put logic may cause glitches Clock Signal s State Storage= Set of n FFs n State can be stored Out put logic may cause glitches Next state = F (current state, inputs) = F (current state, inputs) 3 Example of Moore & Melay Machine Parity Checker Solution :(Moore) Even [] Odd [] Input is dependent only on current state Moore Machine: is associated with the state and hence appears afterthe state transition take place. 5 Example of Moore & Mealy Machine Parity Checker Transition Arc / Even Odd Solution :(Mealy) / / Input O/Pisdependent on current state and input in Mealy / Mealy Machine: is associated with the state transition, and appears beforethe state transition is completed (by the next clock pulse). D FF x= Parity Checker: Moore M/C Implementation D A y T FF x Moore O/P is synchronized with clock. T A y x= D FF Parity Checker: Mealy M/C Implementation D A y x T FF T Mealy O/P is not synchronized with clock. y 8 3

4 /3/5 Comparison : Mealy FSM Vs Moore FSM Mealymachines have less states s are on transitions (n ) rather than states (n) Mooremachines are saferto use s changeat at clock edge(always onecycle later) Mealy machines: input change can cause output change as soon as logic is done A big problemwhen two machines are interconnected Asynchronous feedback mayoccur if one isn t careful 9 Comparison : Mealy FSM Vs Moore FSM Mealymachines react fasterto inputs react in same cycle don't need to wait for clock outputs maybe considerably shorter than the clock cycle in Moore machines, more logic maybe necessary to decode state into outputs there maybe more gate delays after clock edge FSM Example : Mealy vsmoore Design a system that outputs a whenever it receives a multiple of 3 # of s (i.e.,, 3, 6, 9, etc. # of s) on a serial input line x. FSM Example: Moore Machine Design a system that outputs a whenever it receives a multiple of 3 # of s (i.e.,, 3, 6, 9, etc. # of s) on a serial input line x. i= [] i= [] i= [] Moore Machine FSM Example: Moore Machine Design a system that outputs a whenever it receives a multiple of 3 # of s (i.e.,, 3, 6, 9, etc. # of s) on a serial input line x. / i= Input / / i= / Mealy Vs Moore : Problem Σo = {t, f ΣI ={, s t at least last input digits are same i= / / Mealy Machine 3 4

5 /3/5 Solutions to Problem Mealy implementation Needs only 3 states Moore implementation Needs more almost duplicated states justinordertotheoutputvaluetthere. /t FSM: Mealy Machine /f S /f /f /t /f FSM: Moore Machine FSM: Moore Machine s true if at least last input digits are same Is it possible to design Moore FSM of the same problem with 3 state? /f /t /f S/f You can try now.. /t FSM State Minimization Minimizing number of state reduce equirement of bigger size state register Possibly reduce the CCC Some Definitions State Equivalence: S and S are equivalent if for every input sequence applied to machine goes to same NS and If S(t+)=S(t+) and Z=Z then S=S Distinguishable States: Two states S and S are Distinguishableiffthere exist at least one finite input sequence which produce different outputs from S and S 9 3 5

6 /3/5 Methods ow Matching Method or Partitioning Method Completely specified machine (n edges) Partially specified machine Implication Chart tmthd Method 3 Form an initial partition (P ) that includes all states. Form a nd partition (P ) by separating the states into two blocks based upon their output values. Form a third partition (P 3 ) by separating the states into blocks corresponding to the next state values. Continue partitioning until two successive partitions are the same (i.e. P N = P N ). All states in any one block are equivalent Equivalent states can be combined into a single state. 3 Example of State Minimization: Partitioning A/ B/ C/ State Diagram D/ E/ G/ F/ Present Next state state w = w = z A B C B D F C F E D B G E F C F E D G F G Separate states based on output value. P = (ABD)(CEFG) Initial Partition: Present Next state state w = w = z P = (ABCDEFG) The initial partition contains all states in the state diagram / table. 35 A B C B D F C F E D B G E F C F E D G F G 36 6

7 /3/5 P = (ABD) (CEFG) Separate states based on next state values. ABD CEFG D is not from set CEFG, otherare from CEFG P 3 = (ABD) (CEG) (F) Separate states based on next state values. F is not from ABD CEG set CEG, but CG are from CEG BDB CFG FFEF ECDG P 3 = (ABD) (CEG) (F) unique state 37 BDB CFG FFF ECG P 4 = (AD) (CEG) (F) (B) unique states 38 P 4 = (AD)(CEG) (F)(B) Separate states based on next state values. AD CEG BB CG FFF ECG P 5 = (AD)(CEG)(F)(B) Since P 4 = P 5, state minimization is complete. The equivalent states are: A = D C = E = G P 4 = (AD) (CEG) (F) (B) B F Thus, the FSM can be realized with just 4 states. Same as previous partition (P 4 ) 39 4 FSM: State Minimization Present Next state state w = w = z A B C B A F C F C F C A Minimized State Table 4 FSM: State Minimization B/ A/ C/ F/ Minimized State Diagram 4 7

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes