15.1 Elimination of Redundant States

Transcription

1 15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter 15: Reduction of State Tables State Assignments CENG 4534 Advantage of reducing the number of states? Number of flip-flops Amount of logic required At the flip-flop inputs More don t care s, larger groups in K-map [Lecture slides are adapted from Fundamentals of Logic Design, 6 th Edition, Roth & Kinney, 2010, Cengage Learning] 3 This chapter in the book includes: Objectives Study Guide 15.1 Elimination of Redundant States 15.2 Equivalent States 15.3 Determination of State Equivalence Using an Implication Table 15.4 Equivalent Sequential Circuits 15.5 Incompletely Specified State Tables 15.6 Derivation of Flip-Flop Input Equations 15.7 Equivalent State Assignments 15.8 Guidelines for State Assignment 15.9 Using a One-Hot State Assignment Problems Rework Example 1 in Section 14.3 Circuit has one input (X) and one output (Z). It examines groups of four consecutive inputs Z = 1 if the input sequence 0101 or 1001 occurs The circuit resets after every four inputs

2 Our Solution in Ch. 14 with minimum number of states: State table for sequence detector: state sequence received S0 reset S 1 0 S2 1 S3 01 or 10 S or 100 S5 2 inputs received, no 1 output is possible S6 3 inputs received, no 1 output is possible 5 7 Now, lets set up enough states to remember first three bits of every possible input sequence. After fourth input, machine goes to reset state States: State 6 Input Sequence A Reset B 0 C 1 D 00 G 11 H 000 P 111 States H, I, K, M, N, P? Next states and the outputs are the same These states are equivalent H I K M N P Replace I, K, N, M, P with H and delete corresponding rows Similarly, states J and L are equivalent (J L) Replace L with J and delete row L Resulting table is shown 8 2

3 State table after replacing and deleting states Reduced State Table: 9 11 After making these changes, in the new table States D and G are identical (D G) States E and F are identical (E F) So, eliminate F and G Reduced State Graph

4 The technique used in the example is called row matching Row matching is not sufficient to find all equivalent states Except in the special case where the circuit resets to the starting state after receiving a fixed number of inputs Two sequential circuits N1& N2 Feed an input sequence X into both circuits and observe the output sequences Z1 & Z2 Then, reset the circuits to states p & q and feed another input sequence X; and observe Z1 & Z2 again Do this for every possible input sequence X (i.e., 1-bit input sequences (0, 1), 2-bit sequences (00, 01, 10, 11), and so on) Equivalence of two states? If Z1 & Z2 are equal for every X, two states are equivalent If any of Z1 & Z2 are different, two states are not equivalent This is not practical! Equivalent States Two states are equivalent if there is no way of telling them apart through observation of the circuit inputs and outputs In a sequential circuit, the output sequence is a function of initial state and input sequence Consider two sequential circuits (not necessarily different) N1 starting in state p and N2 starting in state q Definition 15.1: Let N 1 and N 2 be sequential circuits (not necessarily different). Let X represent a sequence of inputs of arbitrary length. Then, state p in N 1 is equivalent to state q in N 2 iff λ 1 (p, X) = λ 2 (q, X) for every possible input sequence X. λ(p, X) is the output given the present state p and input X

5 Theorem 15.1: Two states p and q of a sequential circuit are equivalent iff for every single input X, the outputs are the same and the next states are equivalent, that is, 3. Go through the table square-by-square. If square i-j contains the implied pair m-n, and square m-n contains an X, then i j, and an X should be placed in square i-j. 4. If any X s were added in step 3, repeat step 3 until no more X s are added. 5. For each square i-j which does not contain an X, i j. λ(p, X) is the output given the present state p and input X δ(p, X) is the next state given the present state p and input X Note that the next states do not have to be equal, just equivalent. This is practical! Determination of State Equivalence The implication table method of determining state equivalence can be summarized as follows: 1. Construct a chart which contains a square for each pair of states. 2. Compare each pair of rows in the state table. 18 If the outputs associated with states i and j are different, place an X in square i-j to indicate that i j. If the outputs are the same, place the implied pairs in square i-j. If the next states of i and j are m and n for some input x, then m-n is an implied pair. If the outputs and next states are the same (or if i-j only implies itself), place a check ( ) in square i-j to indicate that i j. Example Eliminate the redundant states in the following state table Can State a and State b equivalent? a b iff d f and c h d-f and c-h are called implied pairs How about State a and State c? 20 Not equivalent (Outputs are different!) 5

6 Implication chart Implication chart after second pass Implication chart after first pass After replacing d with a and e with c, eliminate rows d & e. Reduced Table with six rows:

7 15.4 Equivalent Sequential Circuits Two sequential circuits are equivalent if they are capable of doing the same work. Definition 15.2: Sequential circuit N 1 is equivalent to sequential circuit N 2 if for each state p in N 1, there is a state q in N 2 such that p q, and conversely, for each state s in N 2, there is a state t in N 1 such that s t. Thus, if N 1 N 2, for every starting state p in N 1, we can find a corresponding starting state q in N 2 such that λ 1 (p, X) λ 2 (p, X) i.e., the output sequences are the same for the same input sequences If N 1 and N 2 have minimum number of states, N 1 and N 2 must have the same number of states 25 Example Machine 1 Machine 2 Are these two machines equivalent? A S 2, B S 0, C S 3, D S 1 27 Machine equivalence can be checked by two methods Equivalence by inspection Equivalence using implication chart Machine equivalence by inspection If machines have a few states, match up pairs of equivalent states by inspection to show that N 1 N 2. Machine Equivalence using Implication Chart Same idea in the state equivalence X-axis is for states of N 1 Y-axis is for states of N 2 If outputs are different, put an X into the corresponding square If outputs are the same, write down the implied pairs For each pass, check each square in the chart Do this until no X is put in one pass Squares with no X indicate the equivalent states

8 Example Equivalent States A S2 B S0 C S3 D S1 Then, N1 N Incompletely Specified State Tables Some entries of state table could be - (don t care) when Sequential circuit is part of a larger digital system Certain input sequences never occur Output is only observed at certain times (not every clock cycle) Similar to - in truth tables, - in state table can be used to simplify the sequential circuits How to use: If - in next-state columns, - can be replaced by any state If - in output columns, - can be replaced by any output value

9 Example: Design the sequential circuit for subsystem B Assume that Circuit A can generate only two output sequences: X=100 and X=110. i.e., Circuit B has only two input sequences When the third input is received, Z=0 if 100 is received and Z=1 if 110 is received Circuit C reads Z at every third input State Table: S 0 1/- 0/0 S 1 0/- 1/- 0/1 S 2 S State Graph: S 0 0/0 1/- 0/1 S 1 0/- 1/- S 2 S 3 State Meaning S 0 S 1 1 S 2 10 S 3 11 Initial, Reset Reduced Table

10 15.6 Derivation of Flip-Flop Input Equations After reducing number of states, derive FF input equations: 1. Assign flip-flop state values to the states (Make state assignments) 2. Construct a transition table 3. Derive the next-state maps from the transition table 4. Find flip-flop input maps from the next-state maps (Ch. 12) and find the flip-flop input equations from the maps Step 3: Derive next state maps from transition table We could make arbitrary state assignments. However, smart state assignments simplify the circuit Example Step 4: Find FF input maps from next state maps and find FF input equations using the input maps Finding FF inputs using present state (Q) and next state (Q + ) values is discussed in Chapter 12 (12.6 gives summary) Note that, for D-FFs, FF input maps are the same as next state maps. So, in the previous step, FF input equations are derived using next state maps. After finding the FF input maps, use K-maps to find input equations. 7 states 3 FFs needed Step1: Make state assignments (smart ones here) S 0 =000, S 1 =110, S 2 =001, S 3 =111, S 4 =011, S 5 =101, S 6 =010 What about 100? (next state and output values are don t care ) Step 2: Construct Transition Table

11 Finding FF inputs (Sect.12.6 Summary) Given Q (present state) and Q + (next state), find the required inputs for FFs. D FF: Input is the same as next state T FF: Input is 1 whenever state change is required S-R FF: S=1 whenever FF must be set to 1; R=1 whenever FF must be reset to 0; S= - if state is 1 and must remain 1; R= - if state is 0 and must remain 0. J-K FF: Same as SR except when one input is one and other input is - Because S=R=1 is not allowed, but J=K=1 causes a state change Before applying these rules, copy any - from next state maps into FF input maps J-K FF input maps for the previous example Input equations derived J C and K C are not shown Example 2 You can use following table to find FF input values A sequential circuit with two inputs and two outputs How to read this table: For D FF: if Q=0 and desired Q + =0, input must be 0 (D=0) For J-K FF: if Q=0 and desired Q + =1, J=1 and K=X 42 State Assignments S0=00, S1=01, S2=11, S3=

12 When D FF are used: Two D FFs: A & B Next state maps are the same as FF input maps FF input equations are derived Output equations are also derived 15.8 Guidelines for State Assignments The cost of logic strongly depends on the way state assignments are made. Making state assignments is a challenge in design Trail-and-error method is useful for a machine with small number of states 3 states 2 FF 4 possibilities for S1, 3 for S2, and 2 for S =24 possibilities (some assignments are equivalent) This is not practical for machines with large number of states Guideline method produces good solutions for some problems, but sometimes it is not satisfactory When S-R FF are used Two S-R FFs: A & B Input maps are shown S A and R A S B and R B Input equations are derived The following guidelines are useful in making assignments: This will place 1 s together (or 0 s) on the next-state maps: 1. States which have the same next state for a given input should be given adjacent assignments 2. States which are the next states of the same state should be given adjacent assignments 3. States which have the same output for a given input should be given adjacent assignments Place 1 s together on the output maps Assignments for two states are said to be adjacent if they differ in only one variable Ex: 010 and 011 are adjacent; 010 and 001 are not adjacent

13 How to use these guidelines, First, write down the sets of states which should be adjacent Then, using K-maps try to satisfy as many adjacencies as possible A fair amount of trial-and-error may be required 57 Example Guideline 2: S 1, S 2 (next states of S 0 ) S 2, S 3 (next states of S 1 ) S 1, S 4 S 2, S 5 (two times: S 3 & S 5 ) S 1, S 6 (two times: S 4 & S 6 ) 59 Guideline 1: S 0, S 2, S 4, S 6 be adjacent S 1 is next state when X=0 S 3 and S 5 S 5 is next state when X=0 S 0, S 1, S 3, S 5 S 2 is next state when X=1 S 4 and S 6 S 6 is next state when X=1 *Guideline 3 is not considered in this example When filling the map, Assign the starting state to 0 square on the map Simplifies the initialization of the circuit Adjacency conditions from Guide 1 and 2 that are required 2 or 3 times should be satisfied first When 3 or 4 states are required to be adjacent, these states should be placed within a group of four adjacent squares If output table is considered, then Guide 3 should be considered Guide 3 has less priority than Guide 1 and 2 if there is single output If there are 2 or more outputs, Guide 3 may have higher priority Guide 1: (S 0, S 2, S 4, S 6 ), (S 3, S 5 ), (S 0, S 1, S 3, S 5 ), (S 4, S 6 ) Guide 2: (S 1, S 2 ), (S 2, S 3 ), (S 1, S 4 ), 2 (S 2, S 5 ), 2 (S 1, S 6 ) Cost of realizing D FF input equations: 6 gates, 13 inputs If straight binary assignment were used, cost: 10 gates, 39 inputs

14 Example 2 Next State and Output Maps: Guide 1: (b, d) (c, f) (b, e) Guide 2: 2x(a, c) (d, f) (b, d) (b, f) (c, e) Guide 3: (a, c) (b, d) (e, f) Assume assignment (c) is in use All adjacencies except (b,f), (c,e), (e,f) are satisfied Transition Table: Assignment (c) satisfies all adjacencies except (b,f), (c,e), (e,f) Cost:10 gates, 26 gate inputs Assignment (b) satisfies all adjacencies except (d,f), (e,f) Cost: 13 gates, 35 gate inputs So, the states assignment which satisfies the most guidelines is not necessarily the best one Good idea to try several assignments which satisfies most of the guidelines and choose the one with lowest cost

15 15.9 Using One-Hot State Assignment When designing with CLPDs or FPGAs, each logic cell contains one or more FFs These FFs are there whether we use them or not Instead of number of FF, try to reduce number of logic cells used and the interconnections between them Because the propagation delay typically depends on number of cell used One-hot state assignment may help to accomplish this The one-hot assignment uses one flip-flop for each state So, a state machine with N states requires N flip-flops Exactly one of the flip-flops is set to 1 in each state How to write next-state equations? There are 4 arcs leading into S3 So, 4 conditions under which next state is S3 PS=S 0 and X 1 =1 PS=S 1 and X 2 =1 PS=S 2 and X 3 =1 PS=S 3 and X 4 =1 Next state of Q3 =1 under these conditions; otherwise, Q3=0 Q 3+ = X 1 (Q 0 Q 1 Q 2 Q 3 ) + X 2 (Q 0 Q 1 Q 2 Q 3 ) + X 3 (Q 0 Q 1 Q 2 Q 3 ) + X 4 (Q 0 Q 1 Q 2 Q 3 ) Q 0 = 1 implies that Q 1 =Q 2 =Q 3 = 0 Q 3+ = X 1 Q 0 + X 2 Q 1 + X 3 Q 2 + X 4 Q Example Partial graph is given 4 states (S0, S1, S2, S3) 4 FFs (Q0, Q1, Q2, Q3) State Assignment S 0 = 1000 (Q 0 Q 1 Q 2 Q 3 ) S 1 = 0100 S 2 = 0010 S 3 = 0001 Next-state and output equations can be written by inspecting the state graph 69 How to write output equations? Z 1 =1 when PS=S 0 and X 1 =1 & when PS=S 2 and X 3 =1 Z 1 = X 1 Q 0 + X 3 Q 2 Similarly, Z 2 = X 2 Q 1 + X 4 Q 3 In general, each term in next-state equation contains exactly one state variable Similarly, each term in output equation contains exactly one state variable 71 15

16 What if the FFs used do not have a preset input? That is, Q 0 can not be set to 1 for initial state Replace Q 0 with Q 0 throughout State assignments for the previous example: S 0 =0000, S 1 =0100, S 2 =0010, S 3 =0001 Modified Equations: Q 3+ = X 1 Q 0 + X 2 Q 1 + X 3 Q 2 + X 4 Q 3 Z 1 = X 1 Q 0 + X 3 Q 2 Z 2 = X 2 Q 1 + X 4 Q 3 Next state equation for Q 0+ : 2 arcs leading to S 0 2 terms in the equation Q + 0 = Q 0 St + Q 3 Next state equation for Q 1+ : 3 arcs leading to S 0 3 terms Q 1+ = Q 0 St + Q 1 K M + Q 2 K Output equation for Sh: Sh appears in 4 places Sh=1 in S1 if K M =1 or KM =1; also in S2 if K =1 or K=1 Sh = Q 1 (K M + KM ) + Q 2 (K + K) = Q 1 M + Q Example 2 A sequential circuit that controls a binary multiplier 3 inputs: St, M, K 4 outputs: Load, Ad, Sh, Done Starting in S 0 When designing with CPLDs or FPGAs, try both an assignment with minimum number of state variables and a one-hot state assignment If area is the concern, choose one with minimum number of logic cells If speed is the concern, choose the fastest one How many FFs? 4 states 4 FFs S 0 =1000 S 1 =0100 S 2 =0010 S 3 =