Mealy & Moore Machines
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- Heather Meredith Turner
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4 Mealy & Moore Machines Moore Machine is a finite-state machine whose output values are determined solely by its current state and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the following: a finite set of states ( S ) a start state (also called initial state) S 0 which is an element of (S) a finite set called the input alphabet ( Σ ) a finite set called the output alphabet ( Λ ) a transition function (T : S Σ S) mapping a state and the input alphabet to the next state an output function (G : S Λ) mapping each state to the output alphabet. Mealy Machine output values are determined both by its current state and by the values of its inputs and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the following: a finite set of states ( S ) a start state (also called initial state) S 0 which is an element of (S) a finite set called the input alphabet ( Σ ) a finite set called the output alphabet ( Λ ) a transition function (T : S Σ S) mapping a state and the input alphabet to the next state an output function (G : S Σ Λ) mapping pairs of a state and an input symbol to the corresponding output symbol.
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13 RS Flip Flop Truth Tables In order to eliminate ambiguity and to achieve some sense of continuity, we will follow the convention: Set implies Q = 1. Reset implies Q = 0. Set Reset Set Reset Set Reset NOR Gates NAND Gates NAND Gates with Inverted S & R inputs S R Q S R Q S R S R Q 0 0 Q Hold 0 0 X Q Hold Reset Set Reset Set Reset Set 1 1 X 1 1 Q Hold X X = Not Allowed X = Not Allowed X = Not Allowed S=1 => Set (Q=1) S=0 => Set (Q=1) S=1 => S=0 => Set (Q=1) R=1 => Reset (Q=0) R=0 => Reset (Q=0) R=1 => R=0 => Reset (Q=0) As you can see, there is consistency for Set means Q=1 and Reset means Q=0; but there can be confusion trying to decide whether-or-not S & R are 0 or 1 depending on the type of gates (NOR or NAND). If inverted S & R inputs are used with the NAND gates, then S=1 is the Set input and R=1 is the Reset input; which is the same as the NOR gates implementation.
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18 NAND Gate Equivalent Circuits Two-input (X & Y) with one-output (F) logic gate circuits can be defined by a total of 16 functions. X Y F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F Six of the functions can be represented merely as hard-wired configurations (inverters as required): F1, F16, F11, F10, F6, F7. X Y F1 F16 F11 F10 F6 F X Y X Y Eight other functions can be implemented using only one NAND gate (inverters as required): F2, F3, F4, F5, F15, F14, F13, F12 X Y F2 F3 F4 F5 F15 F14 F13 F X Y X Y X Y X Y NOT (X Y) NOT (X Y) NOT (X Y) NOT (X Y) The remaining two functions can be implemented using three NAND gates (inverters as required): F8, F9. X Y F8 F X Y + X Y X Y + X Y Notes: A OR B = NAND (A B) F6 = NOT F11 = X F7 = NOT F10 = Y F15 = NOT F2 = NAND (X Y) F14 = NOT F3 = NAND (X Y) F13 = NOT F4 = NAND (X Y) F12 = NOT F5 = NAND (X Y) F8 = X Y + X Y = NAND [ NAND (X Y) with NAND (X Y) ] F9 = X Y + X Y = NAND [ NAND (X Y) with NAND (X Y) ] F8 = NOT F9
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20 NAND Gate Equivalent Circuits Sketch an equivalent circuit using only NAND gates to represent each of 16 different possible output functions from a combination of 2 inputs (X & Y). Note: Indicate inversion with either input bubbles or output bubbles; do not use additional inverter gates. X Y F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F Example: See Function F8 above, use positive logic when the Output Function = 1 X = 0, Y = 0 X AND Y or X = 1, Y = 1 X AND Y F8 = (X AND Y) OR (X AND Y) F8 = (X AND Y) OR (X AND Y) F8 = (X AND Y) AND (X AND Y) = NAND( X with Y ) AND NAND (X with Y) F8 = NAND (NAND( X with Y ) with NAND( X with Y ) Sketch: X Y #1 #3 #2 Logic Table Proof: X Y X Y Gate #1 Gate #2 Gate #3 X NAND Y X NAND Y Gate#1 NAND Gate # See page 2 for a similar case using negative logic when the Output Function F8 = 0. Page 1.
21 Negative logic when the Output Function F8 = 0 X = 0, Y = 1 X AND Y or X = 1, Y = 1 X AND Y Note F8 = 0, is the same as F8 so F8 = (X AND Y) OR (X AND Y) F8 = (X AND Y) OR (X AND Y) F8 = (X AND Y) AND (X AND Y) F8 = NAND( X with Y) AND NAND( X with Y) F8 = NOT NAND [(NAND( X with Y) with NAND( X with Y)] Sketch: X Y #1 #3 #2 Logic Table Proof: X Y X Y Gate #1 Gate #2 Gate #3 X NAND Y X NAND Y Gate#1 NAND Gate #2 NOT (Gate#3) Page 2.
22 NAND Gate Equivalent Circuits Sketch an equivalent circuit using only NAND gates to represent each of 16 different possible output functions from a combination of 2 inputs (X & Y). Note: Indicate inversion with either input bubbles or output bubbles; do not use additional inverter gates. X Y F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F Example: See Function F9 above, use positive logic when the Output Function = 1 X = 0, Y = 1 X AND Y or X = 1, Y = 0 X AND Y F9 = (X AND Y) OR (X AND Y) F9 = (X AND Y) OR (X AND Y) F9 = (X AND Y) AND (X AND Y) = NAND( X with Y) AND NAND (X with Y) F9 = NAND (NAND( X with Y) with NAND( X with Y ) Sketch: X Y #1 #3 #2 Logic Table Proof: X Y X Y Gate #1 Gate #2 Gate #3 X NAND Y X NAND Y Gate#1 NAND Gate # See page 4 for a similar case using negative logic when the Output Function F9 = 0. Page 3.
23 Negative logic when the Output Function F9 = 0 X = 0, Y = 0 X AND Y or X = 1, Y = 1 X AND Y Note F9 = 0, is the same as F9 so F9 = (X AND Y) OR (X AND Y) F9 = (X AND Y) OR (X AND Y) F9 = (X AND Y) AND (X AND Y) F9 = NAND( X with Y) AND NAND( X with Y) F9 = NOT NAND [(NAND( X withy) with NAND( X with Y)] Sketch: X Y #1 #3 #2 Logic Table Proof: X Y X Y Gate #1 Gate #2 Gate #3 X NAND Y X NAND Y Gate#1 NAND Gate #2 NOT (Gate#3) Page 4.
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