Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc.

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Roland Ross
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1 Finite State Machines Introduction Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc. Such devices form basis for control Most modern computing and control systems Implementation may be in hardware or software Hardware implementation of such machines LSI Arrayed logic PLD ROM Discrete logic Up to this point in our studies We ve looked at the basic storage element Some simple counting and dividing circuits Next we ll examine several different kinds of machine More sophisticated counting Timing Basic storage Control Recognition Pattern Sequence Simple state machines Like counter, divider, timer Have No inputs other than clock Only primitive outputs Such machines referred to as autonomous clock As we move to more complex designs Introduce Inputs Outputs offering rich functionality

2 Such functionality based upon State of the machine Inputs to the machine Our high level block diagram begins with the following Inputs Finite State Machine Outputs Now we have Set of inputs Set of outputs Important to recognize Outputs may be State variables Combinations of state variables Combinations of State variables Inputs Let s increase the level of detail of out state machine We ll reflect the Inputs State variables Outputs Inputs Finite State Machine State Variables Outputs We see that our state variables Fed back as inputs to our system We re now looking at the essence of the strength of the machine It has the ability to Recognize the state that it is in Based upon the values of the state variables React based upon that information

3 Decision as to which state to go to next now based upon The current input The state that the machine is currently in Let s continue increasing the level of detail We ll increase our view to now include Storage elements comprising the machine Combinational logic Implements output functionality Input equations to storage elements Our block diagram now becomes X Z X n- Combinational Logic Z m- Y (t+) Y (t) Memory Device Y p- (t+) Memory Device Y p- (t) We now see that we have n inputs m outputs p state variables Associated with each state variable We have a memory device At this point we do not specify the particular type Working from this model We can begin to formalize out model of the finite state machine

4 Our model must reflect Inputs Outputs Which may be a function of Inputs and State variables State variables alone State variables Movement between states Finite State Model Finite State Machine Also known as finite automaton Abstract model describing Sequential machine Forms basis for understanding and developing Various computational structures We now formally define such a finite state machine We specify the variables X i Represent system n inputs Z j Represent system m outputs Y k Represent internal p state variables We define our finite state machine as a quintuple M = { I, O, S,, } I - Finite nonempty set or vector of inputs O - Finite nonempty set or vector of outputs S - Finite nonempty set or vector of states - Mapping I x S S - Mapping I x S O - Mealy Machine 2 - Mapping S O - Moore Machine x is the Cartesian or cross product The Cartesian product of two vectors Gives matrix of all possible pairs Among elements of two vectors

5 To reflect the different ways of expressing our output We define Mealy machine - Output function of Present state and inputs Moore machine - 2 Output function of Present state only Putting State Machines to Work Let s take a detailed look at how we can begin to use our model We ll begin with a simple pattern or sequence detector One possible use for such a system Communications systems Synchronize or lock onto incoming data stream Based upon initial or synchronizing pattern We will accept data coming into our system Data will come in in serial One bit at a time Our specifications require We detect the pattern in the data If we recognize the pattern We are to output a found signal The immediate implication of specification Time is an important component of our design Let s start to analyze the problem High level system requirements Input One input Serial stream of data Output One output Logical every time sequence detected

6 As a first step We try to capture the requirements in a block diagram For this problem the diagram will be pretty simple Serial Input Pattern Detect Found Note: pattern must be Assume: LSB arrives at t Next we formally express the behaviour of the system Capture such behaviour in state diagram Such a diagram Expresses the behaviour of the system in time Identifies each legal state of the system Depicts means by which system got to each state State Diagram Vertices Each state in machine Corresponds vertex in state diagram If the system has states We ill have vertices Arcs For each vertex We have 2 p directed arcs One for each combination of inputs Arcs correspond to state transitions Caused by input variables These arcs express the mapping we saw earlier I x S S If we have 3 inputs to system Each state will have 2 3 arcs leaving One arc for each possible input combination Each directed arc Labeled with Input combination

7 Caused transition Resulting output symbol that is generated Associated with each arc we write input / output Behaviour State diagram describes our system It shows Succession of states Through which sequential machine passes Output sequence which it produces In many systems we can define two distinguished states Initial State State of machine prior to application of input sequence Final State State of machine after application of input sequence Let s see what the state diagram for our system will look like Before we can begin Need to clarify the specification Consider that we receive the sequence.. We have two possible interpretations. We examine the pattern in groups of 4 If we detect the pattern We must start over looking for the pattern again For the above sequence We will detect the pattern twice 2. We can reuse part of the pattern For the above pattern We will detect the pattern 3 times We will build the second interpretation This is also called a sliding window We begin in the idle state Most of our designs use an initial or idle state We will label that state as state A Since we only have a single input

8 We will only have two arcs emanating from each state From the idle state we re at t Our input can be either a or a If we get a We will go to state B Says that we now have bit correct If we get a We remain in state A Says that we have no bits correct Our state diagram becomes / A / B Observe that se label each arc Showing input and output combination From state B - we re at t Once again our input can be either a or a If we get a We remain in state B Says that we still only have bit correct If we get a We go to state C Says that we have two bits correct Our state diagram becomes / / A / B / C Observe that our output remains a It must since we have not detected the full sequence yet From state C we re at t 2 Once again our input can be either a or a If we get a We re winning we go to state C Says that we now have 3 bits correct

9 If we get a We fail and must return to A Says that we have no bits correct Our state diagram becomes / / / A / B / / C D Observe that our output remains a It must since we have not detected the full sequence yet Now we re looking for the 4 th bit From state D we re at t 3 Yet again our input can be either a or a If we get a We re only partially win we go to state B Says that we now have just 2 bits correct If we get a We return to C and output a Says that We have matched the patters Also we still have three bits correct Our final state diagram becomes / / / A / B / / C D / /

10 We have now captured in graphical presentation Complete behaviour of our system We can use such a diagram for discussion and analysis Need somewhat different format To begin next stage of design The State Table The state table contains same information as state diagram Expresses in tabular form Easier to develop logic equations from Let s take a look A state table has Two major subdivisions One column Showing the state of the system at time t n A set of columns Showing the state of the system at time t n+ Each column reflects the next state for each specific input combination Thus in general we have p columns One for each combination of input symbols in set I n rows One or each state in S This is now the matrix we referred to earlier The columns give us the input combinations The rows give us the set of present and next states To implement machine will require k memory elements k is smallest integer value such that k log 2 n For our design We will have two columns One for the input data taking a value of logical One for the input data taking a value of logical We will have 4 rows One for each state

11 Taking the information directly from the state diagram we have Present State t = t n Next State t= t n+ x = x = A B, A, B B, C, C D, A, D B, C, The Output Table The next step in our process is to specify the outputs from our system These appear in an output table Once again this information Captured directly from the state diagram Often we will combine the state and output tables into single table The output table has p columns One for each combination of input symbols in set I n rows One or each state in S The output table gives us our output matrix Here we have I x S O S O For each combination of input symbol and present state Specifies output of system Remember If building a Moore machine Each output column will have same value Once again reading directly from the state diagram The output table for our design is given as Present State t = t n Output t= t n+ x = x = A B C D

12 State Assignment Our next step is to Choose state variables Assign appropriate combinations to each state Let s us uniquely identify each state in our system Selecting state assignment Important step in design of finite state machine There are wide variety of techniques of varying degrees of complexity Let s look at a couple. Binary Assignment Easiest is to simply use binary sequence Initial state gets pattern of binary Each subsequent state gets next binary number Often works with no problem One major limitation Building outputs as combinational patterns As we ve learned Combinational logic subject to race conditions and hazards With such an approach Run risk of having decoding spikes on our outputs 2. Gray Assignment To address problem of race conditions Want to ensure that we have only single variable change between states Reduces chances of decoding spikes As first step We develop table listing all states For each state Identify Preceding states Next states For our system we have Previous Present Next C A B A,D B C B,D C A,D C D B,C

13 Then we assign states such that Single variable change Previous to present Present to next Not always able to do Using a Karnaugh map helps For our system We have 4 states Requires we use 2 state variables Thus we now have P Q A B D C Generally we select our initial state to have the value of binary Simplifies ensuring system starts in known state The Transition Table Once we have the state assignment We use it to construct a transition table The transition table combines our state table With the state assignment we just developed We simply substitute the state variable combination for each state Back into the state table For our design we have PQ Next State x = x = A B A B B C C D A D B C

14 The Input Equations We re now ready to implement the design For the state equations Simply follow same procedure we did earlier For our design We first develop the following K Maps PQ X P PQ X Q If we choose to use JK flip flops We write the following equations from the maps Jp = QX Kp = QX +!Q!X Jq = P +!X Kq = P The Output Equations The output equations follow in a similar manner We simply use a K Map For our design we have PQ X Out Out = P!QX Design Guidelines From our work we propose the following guidelines. From word description of problem, form a state diagram 2. From the state diagram develop the state table 3. Check for redundant states 4. Select a state assignment

15 5. Develop transition and output tables 6. Develop Karnaugh map for each state variable 7. Select memory device and develop input equations from Karnaugh map 8. Develop Karnaugh map for each output variable 9. Develop output equations from Karnaugh map Let s look at another pattern recognition problem Our specification now requires a system that Accepts serial bit stream on input Searches for either of the patterns in the input data stream If patterns recognized Output is asserted true False otherwise Our high level block diagram is given as Serial Input Pattern Detect Found Note: pattern must be or Assume: LSB arrives at t We begin by developing the state diagram Step Always draw state diagram / / 2 / / / / / / / / / / No Match 7 8 Match

16 Step 2 Write the state table from the state diagram Step 3 Present Next State Output X = X = X = x = Observe that we are building a Moore machine here The output in states 7 and 8 Function of only the state We ll assume some form of reset to get back to state Assign state variables and values For this example 9 states 4 state variables This will give us 7 don t care conditions Prev. Present Next -,2 3,4 2 5, , ,8 3,4, ,6 8 8 A B C D Which gives us our state assignment Observe that this is not unique State ABCD

17 Step 5 Specify the transition table Present ABCD Next State Output X = X = ABCD ABCD X = x = Step 6 Develop Karnaugh maps for each state variable Illustrate the A variable A B C D x x x x x x x x x x x x x x x x x J A =!BD!x + AD + B!D!x K A = Let s now look at an example In which we have more than one input Our specification is for a combination lock The combination requires the sequence 3 2 to open We ask What are the inputs What are the outputs

18 Once again We begin with state diagram /, /, / / /, /, / /, /, / / /, /, / 3 / 2 / From here we write the state table Next State Present x2 x The develop the output table Output Present 2 3 x2 x For this problem We stay with a binary sequence for the state assignment Based upon such an assignment We write the transition table Next State Present AB AB AB AB AB 2 3 x2 x

19 Then follow with the K Maps Present Next State x2 x ABC 2 3 A Present Next State x2 x ABC 2 3 B J A = B!X X 2 K A =!B + X +!X 2 J B =!A X X 2 K B = A + X +!X 2 Multiple Machines When designing complex systems Good practice to decompose into smaller pieces Powerful architecture Top level controller Enable slave machines as needed Consider system with 4 major tasks Each task comprised of multiple simpler tasks State State Slave Slave System now consists of 5 sequential machines Master controller 4 Slave controllers Master State 2 Slave 2 Architecture appears as State 3 Slave 3 State Machine Reduction So far in our designs Have not paid much attention to optimizing design Although one could argue With LSI lots of memory etc Why waste time trying to reduce or simplify design First not all designs have such luxury Many consumer products stress simplification

20 Major reason is to save power Fewer transistors Less power Second even with LSI If design can be simpler Can add more functionality or features For same real estate Simpler design easier to manufacture Yep even for LSI Third reliability Less complexity means fewer things can go wrong Let s take a look at several approaches We ll illustrate techniques manually However they can be easily written as software design tools All of that said let s begin Goal Identify and combine states that have equivalent behavior Equivalent States For all input combinations States transition to the same or equivalent states We ll examine two alternative algorithms Row matching Implication charts We ll begin with row matching Row Matching Algorithm General plan or algorithm Rather straight forward. Start with state transition table 2. Identify states with same output behavior 3. If such states transition to the same next state, they are equivalent 4. Combine into a single new renamed state 5. Repeat until no new states are combined Once again will work with simple pattern matching system

21 For our system we will have Single input X, output Z Taking inputs grouped four at a time Output if last four inputs Were the string or Example I/O Behavior: X =... Z =... Taking what we call the exhaustive approach That is elaborating each possible transition With no those given to reduction We arrive at following state diagram / / Reset / / / / / / / / / / / / / / / / / / / / / / / / / / / / For this problem Let s take a look at worst complexity That is how complex can system be We simplify from there We have Fifteen states ( ) Thirty transitions ( ) Sufficient to recognize any binary string of length four

22 From our state diagram our first cut at the state table becomes Input Sequence Reset Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 S S S S S S S S S S S S S S S S Output X = X = In the state table We ve segregated rows into transitions at t, t, t 2, and t 3 We now apply steps 2..4 of our algorithm We begin at time t 3 and work backwards For our system We see that states S and S 2 Have the same next state and same output We can combine them into a single state This gives us Input Sequence Reset Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S S S 2 S 3 S 4 S S S S S S S S S S S S S S S S Output X = X =

23 We combine the two into state S Input Sequence Reset or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S ' S 3 S 4 S S S S S S S S S S S S S S Output X = X = We now see that we can combine S 7..S 9 and S, S 3, and S 4 into a single state For the same reason Input Sequence Reset or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S 3 S 4 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S ' S S ' S 3 S 4 S S S S S S S S S S S S S S Output X = X =

24 This gives us Input Sequence Reset not ( or ) or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 ' S ' Next State X = X = S S 2 S 3 S 4 S 5 S 7 ' S 7 ' S 7 ' S 7 ' S S S 6 S 7 ' S ' S ' S 7 ' S S Output X = X = Next we move back to time t 2 and repeat the process Here states S 3 and S 6 and S 4 and S 5 can be combined Thus Input Sequence Reset not ( or ) or Present State S S S 2 S 3 S 4 S 5 S 6 S 7 ' S ' Next State X = X = S S 2 S 3 S 4 S 5 S 7 ' S 7 ' S 7 ' S 7 ' S S S 6 S 7 ' S ' S ' S 7 ' S S Output X = X = There are no reductions at the t level So we have our final reduced state table Input Sequence Reset or or not ( or ) or Present State S S S2 S3' S4' S7' S' Next State X= X= S S2 S3' S4' S4' S3' S7' S7' S7' S' S S S S Output X= X=

25 Our system has been Reduced from original 5 states To 7 states Number of flip flops Reduced from 4 to 3 Implication Chart Second approach want to look at Called implication chart algorithm For our state machine we have the following specification Single input X Single output Z Output a whenever the serial sequence or Has been observed at the inputs Our state table is given as Input Sequence Reset Present State S S S 2 S 3 S 4 S 5 S 6 Next State X = X = S S 2 S 3 S 4 S 5 S 6 S S S S S S S S Output X = X = Our initial design has 7 states To implement we ll need 3 flip flops The implication chart algorithm says. Construct implication chart. We have one square For each pair of states 2. For each square labeled Si, Sj If outputs differ then that square gets "X" Otherwise write down implied state pairs for all input combinations 3. Advance through chart top-to-bottom and left-to-right If square Si, Sj contains next state pair Sm, Sn and that pair labels a square already labeled "X"

26 Then Si, Sj is labeled "X" 4. Continue executing Step 3 until no new squares are marked with "X". 5. For each remaining unmarked square Si, Sj Then Si and Sj are equivalent. For our system We begin with the following chart elaborating all the present state pairs S S2 S3 S4 S5 S6 S S S2 S3 S4 S5 We begin by examining S and S and ask If these two states are combined what are the implications Looking at the state table If we combine these two states into a single state The next state entries demand We must also combine S and S 3 and S 2 and S 4 We make note of this by entering the implication Into the square S -S We repeat with all remaining combinations to give Following complete implication chart

27 S S2 S3 S4 S-S3 S2-S4 S-S5 S3-S5 S2-S6 S4-S6 S-S S3-S S5-S S2-S S4-S S6-S S5 S6 S-S S3-S S5-S S-S S2-S S4-S S6-S S-S S-S S-S S S S2 S3 S4 S5 Observe that we cannot combine states S4 or S6 With any of other states The outputs are incompatible Thus We mark an X in each of the pairs involving these two states Observe also States S4 and S6 are compatible with each other Our next step is to examine each of the implications With their associated constraints Mark out those that are incompatible For any reason Let s begin with the potential merger of S and S Such a merger requires that S 2 and S 4 be merged However chart says these two states cannot be merged Outputs are not compatible Mark that square with an X Consequence any states requiring merger of S and S Not permitted We repeat with all squares and associated implications

28 To get the final chart S S2 S3-S5 S4-S6 S3 S4 S5 S6 S-S S-S S-S S-S S S S2 S3 S4 S5 We see that only possible mergers are S S2 S3 S5 S4 S6 Which gives us the final reduced state table Input Sequence Reset or or or Present State S S ' S 3 ' S 4 ' Next State X = X = S ' S ' S 3 ' S 4 ' S S S S Output X = X =

The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure. Output Equation Determination - Derive output equations from the state table The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types