14.1. Unit 14. State Machine Design

Transcription

1 4. Unit 4 State Machine Design

2 4.2 Outcomes I can create a state diagram to solve a sequential problem I can implement a working state machine given a state diagram

3 STATE MACHINES OVERVIEW 4.3

4 4.4 Review of State Machines We've implemented state machines in software, now let's see how we can build them in hardware State machines are described with state diagrams that show various states, transition arrows between them, and outputs to be generated based on the current state We use the state to help us know which step of an algorithm we are currently at

5 4.5 Hardware State Machines Hardware (finite) state machines of (FSMs) provide the brains or control for electronic and electro-mechanical systems Many custom hardware designs use a hardware-based FSM to control their operation Goal is to generate output values at specific times When you need time dependent HW outputs, you can use an FSM FSMs require sequential and combinational logic elements Sequential Logic to remember what step (state) we re in Encodes everything that has happened in the past Combinational Logic to produce outputs and find what state to go to next Generates outputs based on what state we re in and the input values

6 4.6 Hardware vs. Software FSM Comparison Hardware FSMs Changes state (makes a transition) every clock cycle Uses a register (i.e. flip-flops) to store the current state Designer can choose state 'codes' arbitrarily but the choice can greatly affect the size of the circuit Uses logic gates (found from a truth table and K-Map or other means) to implement the state transition arrows Must implement the initial state value using the RESET signal Software FSMs Changes state (makes a transition) when software polls the inputs (which could be very low frequency) Uses a variable to store the current state Programmer can choose state 'codes' arbitrarily with little implication Uses 'if' statements to implement the state transition arrows Must implement the initial value of the state variable

7 4.7 Comparison: FSM in SW and HW int main() { unsigned char state=; // init state unsigned char input, output; while() { _delay_ms(); // choose appropriate delay input = PIND & ( << PD); State Diagram } if(state == ){ PORTD &= ~( << PD7); // output off if( input ){ state = ; /* transition */ } else { state = 2; /* transition */ } } else if(state == ){ PORTD &= ~( << PD7); // output on if( input ){ state = 2; } else { state = ; } } else if(state == 2) { PORTD = ( << PD7); // output on if(!input ) { state = ; } } } return ; Software Implementation (Input) X CLK (Next State) D D D D PRE CLR Q Q RESET PRE CLR Q RESET Q (Current State) Q Q (Output) F Hardware Implementation

8 4.8 State Machine Example Design a sequence detector to check for the combination "" Input, X, provides -bit per clock Check the sequence of X for "" in successive clocks If "" detected, output F= (F= all other times) X CLK RESET "" Sequence Detector F

9 4.9 Another State Diagram Example Sequence Detector should output F= when the sequence is found in consecutive order Sinit F= S F= S F= S F= State Diagram for Sequence Detector See the end of this slide set for more detailed solutions and explanations.

10 4. Correct Specification of State Diagrams For HW especially, it is critical that exactly one transition from a state may be true at a time We can't go 2 places at once and if we don't tell it explicitly where to go next, it may go to any random state If you want to stay in a state, include an explicit loopback arrow On the 2 nd example if you want to stay in Q, include a loopback labeled X= Q X= Q X= Q X= Q NO LABEL = Unconditional transition X= X= Incorrect (2 conditions true) Incorrect (No condition for X = ) Correct Correct

11 4. Correct Specification of State Diagrams 2 Exactly one transition from a state may be true at a time Make sure the conditions you associate with the arrows coming out of a state are mutually exclusive (< 2 true) but all inclusive (> true) X= X= and Y= X= and Y= Q Q Q Y = X= and Y = (X= and Y=) Incorrect (More than one condition can be true) Incorrect (Not all conditions covered) Correct ( and only condition will be true at all times) ALWAYS double check your transitions to ensure they are mutually exclusive.

12 4.2 State Machines The HW for a state machines can be broken into 3 sections of logic State Memory (SM) Just FF s to remember the current state Next State Logic (NSL) Combo logic to determine the next state Essentially implements the transition conditions Output Function Logic (OFL) Combo logic to produce the outputs

13 4.3 State Machine NEXT STATE The FF inputs will be the value of the next state logic output. On the next clock edge the FF outputs will change based on these inputs. CURRENT STATE The FF outputs represent the current state (the state we re in right now) inputs Next State Logic next state D i State Memory (Flip- Flops) current state Q i Output Function Logic outputs clock Important: State is always represented and stored by the flip-flop outputs in the system

14 4.4 State Machines Below is a circuit implementing a state machine, notice how it breaks into the 3 sections (Input) (Next State) (Current State) X D Q D Q OFL NSL Q SM (Output) F D D Q Q Q CLK

15 STATE MACHINE DESIGN 4.5

16 4.6 State Diagram vs. State Machine State Diagrams. States 2. Transition Conditions 3. Outputs State Machines require sequential logic to remember the current state (w/ just combo logic we could only look at the current value of X, but now we can take 4 separate actions when X=) On Reset (power on) X= Sinit F= X= S S F= F= X= X= X= X= X= X= State Diagram for Sequence Detector S F= State Machine. State Memory => Flip-Flops (FFs) n-ff s => 2 n states 2. Next State Logic (NSL) combinational logic logic for FF inputs 3. Output Function Logic (OFL) MOORE: f(state) MEALY: f(state + inputs) (Input) (Next State) (Current State) X D Q D Q OFL (Output) NSL Q F SM D D Q Q Q CLK

17 4.7 State Machine Design State machine design involves taking a problem description and coming up with a state diagram and then designing a circuit to implement that operation Problem Description State Diagram Circuit Implementation

18 4.8 State Machine Design Coming up with a state diagram is non-trivial Requires creative solutions Designing the circuit from the state diagram is done according to a simple set of steps To come up w/ a state diagram to solve a problem Write out an algorithm or series of steps to solve the problem Each step in your algorithm will usually be one state in your state diagram Ask yourself what past inputs need to be remembered and that will usually lead to a state representation

19 EXAMPLE 4.9

20 4.2 Consecutive Detector Given a single-bit input, X, set the output to if the last 2 values of X have been X CLK RESET Consecutive 's Detector X F

21 4.2 6 Steps of State Machine Design. State Diagram 2. Transition/Output Table (Q -> Q*) 3. State Assignment Determine the # of FF s required Assign binary codes to replace symbolic names 4. Rename Qi* to Di 5. K-Maps for NSL (Di values) and OFL One K-Map for every FF input One K-Map for every output of OFL 6. Draw out the circuit

22 4.22 Transition Output Table Convert state diagram to transition/output table Show Next State & Output as a function of Current State and Input Current State Input (X) Next State Output (F) On Reset (power on) X= X= S F= X= S F= S2 F= X= X= X= S S S S S S S S2 S2 S S2 S2

23 State Assignment Mapping 4.23 Transition Output Table Now assign binary codes to represent states The order doesn't matter. Use don't cares for unused state codes On Reset (power on) X= X= S F= X= S F= S2 F= X= X= State Q Q S -- S S2 X= Current State Input Next State Output Q Q X Q* Q* F d d d d d d

24 Notice we used Gray Code order. This will help in a future step 4.24 Transition Output Table Convert state diagram to transition/output table Current State Next State Output X = X = State Q Q State Q* Q* State Q* Q* F S S S d d -- d d d S S S2 S2 S S2 On Reset (power on) X= X= S F= X= S F= S2 F= X= X= X= Here we have redrawn the 8 row table from the previous slide into 4 rows & 2 columns. We've also separated the output F since it doesn't depend on X but only Q and Q

25 4.25 Rename Q* to D The goal is to produce logic for the inputs to the FF s D,D : (aka "excitation equations") For D-FF s Q* will be whatever D is at the edge NSL Next State SM OFL X D D SET Q Q CLR Q F Q D D SET Q Q CLR CLK Current State Feedback

26 4.26 Updated Table Find a truth table for the flip-flop inputs (Di) and output (F) Current State State Q Q State Next State X = X = Q* D Q* D State S S S d d -- d d d S S S2 S2 S S2 Q* D Q* D Output F On Reset X= (power on) X= X= S S S2 F= X= F= F= X= X=

27 4.27 Karnaugh Maps Now need to perform K-Maps for D, D, and F Current State Next State X = X = Output State Q Q State D D State D D F S S S d d -- d d d S S S2 S2 S S2 X QQ d d D = X

28 4.28 Karnaugh Maps Now need to perform K-Maps for D, D, and F Current State Next State X = X = Output State Q Q State D D State D D F S S S d d -- d d d S S S2 S2 S S2 X QQ X QQ d d D = X d d D = X Q'

29 4.29 Karnaugh Maps Now need to perform K-Maps for D, D, and F Current State Next State X = X = Output State Q Q State D D State D D F S S S d d -- d d d S S S2 S2 S S2 QQ X QQ X Q Q d d D = X d d D = X Q' d F = Q Q' = Q XOR Q

30 4.3 Implementing the Circuit Implements the consecutive s detector (Input) X (Next State) D D PRE Q (Current State) Q CLR RESET Q (Output) F D D PRE Q Q CLR Q RESET CLK

31 4.3 Implementing an Initial State How can we make the machine start in S on reset (or power on?) Flip-flops by themselves will initialize to a random state ( or ) when power is turned on On Reset X= (power on) X= X= S S S2 F= X= F= F= X= X=

32 4.32 Implementing an Initial State Use the CLEAR and PRESET inputs on our flip-flops in the state memory When CLEAR is active the FF initializes Q= When PRESET is active the FF initializes Q= D PRESET Q CLK CLR

33 State Assignment Mapping 4.33 Implementing an Initial State We assigned S the binary code Q Q = so we must initialize our flip-flops to QQ= State Q Q On Reset (power on) X= X= S F= X= S F= S2 F= X= X= X= S -- S S2

34 4.34 Implementing an Initial State Use the CLR inputs of your FF s along with the RESET signal to initialize them to s We don't need the PRESET inputs so GND them (Input) X (Next State) D D PRE Q (Current State) Q CLR RESET Q (Output) F D D PRE Q Q CLR Q RESET CLK

35 4.35 Implementing an Initial State When RESET is activated Q s initialize to and then when it goes back to the Q s look at the D inputs Forces Q s to because it s connected to the CLR inputs RESET Q Q Once RESET goes to, the FF s look at the D inputs

36 4.36 Alternate State Assignment Important Fact: The codes we assign to our states can have a big impact on the size of the NSL and OFL Let us work again with a different set of assignments Current State Next State X = X = Out put State Q Q S -- S S2 Old Assignments State Q Q State State F S S S S2 S S2 S S S New Assignments

37 4.37 Alternate State Assignment Current State State Q Q State Next State X = X = Q* =D Q* =D State Q* =D Q*= D S S S d d -- d d S2 S S2 S S S Outp ut F QQ X QQ X Q Q d d D = X Q Q' d d D = X Q'+X Q d F = Q Q = Q

38 4.38 Updated Circuit & Reset Condition Consider the initial state implementation S = QQ = (Input) X (Next State) D D PRE CLR Q Q RESET RESET (Current State) Q (Output) F D D PRE Q Q CLR Q CLK Notice the different state assignment led to larger circuits (NSL is considerably larger). We will generally provide you the state assignment!

39 EXAMPLE

40 4.4 Traffic Light Controller Design the controller for a traffic light at an intersection Main street has a protected turn while small street does not Sensors embedded in the street to detect cars waiting to turn Let S = S OR S2 to check if any car is waiting Simplify and only have Green and Red lights (no yellow) Turn Sensor S On Reset (power on) MS Q Q = Small Street SS Q Q = S = Turn Sensor S2 Overall sensor output S = S + S2 S = MT Q Q =

41 4.4 State Assignment Design of the traffic light controller with main turn arrow Represent states with some binary code Codes: 3 States => 2 bit code: =SSG, =MSG, =MTG Turn Sensor S On Reset (power on) MS Q Q = SS Q Q = S = State Diagram Turn Sensor S2 Overall sensor output S = S + S2 S = MT Q Q = Main Street

42 4.42 K-Maps Find logic for each FF input by using K-Maps Current State Next State S = S = Output State Q Q State Q * Q * State Q * Q * SSG MTG MSG SS MS MT N/A X d d X d d d d d MT MS MS MS SS SS On Reset (power on) SS Q Q = S = S = Q Q d MSG = Q Q MS Q Q = MT Q Q = S QQ d d S QQ d d Q Q d SSG = Q Q Q d MTG = Q D = Q +Q D = S Q

43 EXAMPLE

44 4.44 Water Pump Implement the water pump controller using the High and Low sensors as inputs Recall the H and L sensor produce when water is covering them and otherwise L= Pump OFF P= ON P= High Sensor L= H= H= Low Sensor Water Tank

45 4.45 L Transition Table OFF P= ON P= L H H Current State Next State H L = H L = H L = H L = Symbol Q Sym. Q* Sym. Q* Sym. Q* Sym. Q* OFF ON OFF OFF X d ON ON ON OFF X d Note: The State Value, Q forms the Pump output (i.e. when we want the pump to be on and othewise) Q H L d d D = L' + H'Q

46 4.46 Alternating Priority Arbiter EXAMPLE 4

47 4.47 Problem Description Two digital devices (Device and Device ) can request to use a shared resource via individual request signals: R (from Dev) and R (from Dev) An arbiter will examine the requests and issue a grant signal to the appropriate device (G to Dev and G to Dev). Requests are examined during cycle and a grant will be generated on the next, and active for one cycle If only one device makes a request during a cycle, it should receive the grant on the next. If both devices request on the same cycle, the grant should be given to the device who hasn't received a grant in the longest time. R R CLK RESET Alternating Prioritizing Arbiter G G Cycle R R G G

48 4.48 State Diagram Complete the state diagram On Reset (power on) R R Cycle R R St. G G PW PG 3 PG 4 PG 5 PW 6 PG PG R R' R' R' PW PG G= PW R' R' PG G=

49 4.49 Transition Table Complete the transition table On Reset (power on) R R' R' R R R R R' PW PG G= R' R PW PG G= R' R' R' R R' R' R' R' R' R Current State Next State Output R R = R R = R R = R R = St. Q Q St* Q* Q* St* Q* Q* St* Q* Q* St* Q* Q* G G PW PW PG PG PG PW PW PG PG PG PG PW PG PG PG PG PW PG PG PG

50 4.5 Find the NSL and OFL Current State Next State Output R R = R R = R R = R R = St. Q Q St* Q* Q* St* Q* Q* St* Q* Q* St* Q* Q* G G PW PW PG PG PG PW PW PG PG PG PG PW PG PG PG PG PW PG PG PG RR QQ RR QQ Q Q Q Q G = Q Q G = Q Q D = R + R D = R' Q + R Q

51 4.5 Final Circuit NSL Next State SM OFL R R D D GND SET Q Q G Q CLR RESET Q D D SET GND Q Q G CLR CLK RESET Current State Feedback

52 EXAMPLE

53 4.53 State Machine Example Design a sequence detector to check for the combination "" Input, X, provides -bit per clock Check the sequence of X for "" in successive clocks If "" detected, output Z= (Z= all other times) X CLK RESET "" Sequence Detector Z

54 4.54 State Diagram Be sure to handle overlapping sequences X= On Reset (power on) X= X= X= X= Sinit Z= S S Z= Z= X= X= S Z= S Z= X= X= X=

55 4.55 Transition Output Table Translate the state diagram into the transition output table Current State Next State X = X = State Q2 Q Q State* Q2* Q* Q* State* Q2* Q* Q* Z Sinit Sinit S S Sinit S S S S S S S S S S Outp ut

56 4.56 Transition Output Table Translate the state diagram into the transition output table Current State Next State X = X = State Q2 Q Q State* D2 D D State* D2 D D Z Sinit Sinit S S Sinit S S S S S S S S S S Outp ut

57 4.57 NSL & OFL Current State Next State X = X = State Q2 Q Q State* D2 D D State* D2 D D Z Sinit Sinit S S Sinit S S S S S S S S S S Out put Q2 QQ d d d Z = Q2 XQ2 QQ d d XQ2 QQ d d XQ2 QQ d d d d d d d d d d d d d d D 2 = X Q2 Q Q D = X D = Q2 + QQ + X Q + XQ Q

58 4.58 Drawing the Circuit X NSL SM OFL D Q Q Q D Q Z Q 2 D 2 Q 2

59 4.59 Waveform for Detector CLOCK RESET X Q Q Q 2 STATE INITIAL STATE I Z

60 SELECTED SOLUTIONS 4.6

61 4.6 Another State Diagram Example Sequence Detector should output F= when the sequence is found in consecutive order On Reset (power on) X= Sinit F= X= S X= X= X= S F= F= X= X= X= State Diagram for Sequence Detector S F=

62 4.62 Another State Diagram Example Sequence Detector should output F= when the sequence is found in consecutive order We have to remember the,, along the way On Reset (power on) X= Sinit F= X= X= X= X= S S F= F= X= X= X= S F= A initially is not part of the sequence so stay in Sinit Another in S means you have, but that second can be the start of the sequence A in S means you have which can t be part of the sequence

63 4.63 ALTERNATING SEQUENCE DETECTOR

64 4.64 Alternating Detector Design a state machine to check if sensor produces two s in a row (i.e. 2 consecutive s) or two s in a row (i.e. 2 consecutive s) On Reset (power on) G A= S = S = S = G A= G = Last cycle we got, two cycles ago we got G = Last cycle we got, two cycles ago we got G = Got 2 consecutive s S = S = S = G = Got 2 consecutive 's G A= G A= S = S =

65 4.65 Transition Output Table Convert state diagram to transition/output table Show Next State & Output as a function of Current State and Input On Reset (power on) G A= S = S = S = G A= Current State Input (S) Next State Output (A) G G G G S = S = S = G G G A= G A= S = S = G G G G G G G G G G

66 State Assignment Mapping 4.66 Transition Output Table Now assign binary codes to represent states On Reset (power on) G A= S = G A= S = S = S = G A= S = G A= S = S = S = State Q Q G G G G Current State Input Next State Output Q Q S Q* Q* A

67 4.67 Transition Output Table Convert state diagram to transition/output table Current State Next State Output S = S = State Q Q State State A G G G G G G G G G G G G On Reset (power on) G A= S = G A= S = S = S = G A= S = G A= S = S = S = Here we have redrawn the 8 row table from the previous slide into 4 rows & 2 columns. We've also separated the output A since it doesn't depend on S but only Q and Q

68 4.68 Excitation Table The goal is to produce logic for the inputs to the FF s (D,D ) these are the excitation equations NSL (Next State Logic) SM (State Memory) OFL (Output Function Logic) S D D Q Q (t) CLK A D D Q Q (t) CLK Q (t) Q (t) Current State Feedback CLK

69 4.69 Excitation Table Using your transition table you know what you want Q* to be, but how can you make that happen? For D-FF s Q* will be whatever D is at the edge NSL (Next State Logic) SM (State Memory) OFL (Output Function Logic) S D D Q Q (t) CLK A D D Q Q (t) CLK Q (t) Q (t) Current State Feedback CLK

70 4.7 Excitation Table In a D-FF Q* will be whatever D is, so if we know what we want Q* to be just make sure that s what the D input is Current State Next State S = S = Output State Q Q State D D State D D A G G G G G G G G G G G G

71 4.7 Karnaugh Maps Now need to perform K-Maps for D, D, and A Current State Next State S = S = Output State Q Q State D D State D D A G G G G G G G G G G G G S QQ D = Q

72 4.72 Karnaugh Maps Now need to perform K-Maps for D, D, and A Current State Next State S = S = Output State Q Q State D D State D D A G G G G G G G G G G G G S QQ S QQ D = Q D = S

73 4.73 Karnaugh Maps Now need to perform K-Maps for D, D, and A Current State Next State S = S = Output State Q Q State D D State D D A G G G G G G G G G G G G QQ S QQ S Q Q D = Q D = S A = Q Q + QQ = Q XNOR Q

74 4.74 Implementing the Circuit Implements the alternating detector NSL (Next State Logic) SM (State Memory) OFL (Output Function Logic) S D D Q Q (t) CLK A unused D D Q Q (t) CLK Q (t) Q (t) Current State Feedback CLK

75 4.75 Implementing an Initial State How can we make the machine start in G on reset (or power on?) Flip-flops by themselves will initalize to a random state ( or ) when power is turned on On Reset (power on) S = G A= S = S = G A= S = S = S = G A= G A= S = S =

76 4.76 Implementing an Initial State Use the CLR inputs of your FF s along with the RESET signal to initialize them to s S NSL (Next State Logic) Q (t) Q (t) D D SM (State Memory) D PRE Q Q (t) OFL (Output Function Logic) CLK CLR RESET PRE D Q Q (t) A CLK CLK CLR RESET Current State Feedback

77 4.77 Implementing an Initial State We don't want to initialize our flip-flops to 's (only QQ=) so we just don't use PRE (tie to 'off'='') S NSL (Next State Logic) Q (t) Q (t) D D SM (State Memory) D PRE Q Q (t) OFL (Output Function Logic) CLK CLR RESET PRE D Q Q (t) A CLK CLK CLR RESET Current State Feedback

78 4.78 Alternate State Assignment Important Fact: The codes we assign to our states can have a big impact on the size of the NSL and OFL Let us work again with a different set of assignments Current State Next State S = S = Out put State Q Q G G G G Old Assignments State Q Q State State A G G G G G G G G G G G G New Assignments

79 4.79 Alternate State Assignment Current State State Q Q State Next State S = S = Q*= D Q*= D State Q* =D Q* =D G G G G G G G G G G G G Output A S QQ S QQ Q Q D = S xor Q xor Q D = Q Q + QQ A = Q