ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

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ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of

cost dependence (1) Setup Time = t2-t1 (2) Propagation delay = t3-t2 (3)

Sequential Circuit? Sequential factor - TIME CLK 1 https://www.semiconvn.

1 ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation delay = t3-t2 (3) Hold time = t4-t2 What is the difference between Combinational and Sequential Circuit? Sequential factor - TIME CLK Lab 3 Steps in designing a State Machine Draw a state transition diagram An initial state Other states to keep track of various activities Transitions Generate a state transition table and a output table Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions K map, Logisim.. Lab 3 - State diagram - Next state and output logic - K-map, Logisim, simplification - Design logic circuit Draw the circuit Register, State Transition Logic and Output Logic Circuit 3 FPGA or etc.. 4

2 Sequential Logic Type of Flip Flop : RS, JK, D, T D flip-flop D Flip flop - Sequential logic - TIME Example : Divide-by-2 counter D Q(t) Q(t+1) T Flip Flop T Flip flop ` 7 While T : 0, Q NOT Change T : 1, Q Change 8

3 Example 1 Solution 1 Draw timing diagram of the following circuit 9 10 Solution 1 Note the trigger edge - CLK DFF1 DFF2 DFF3 Example 2 Draw timing diagram of the following circuit a Which triggered by CLK?? 11 12

4 Solution 2 Consider Delay? a, Q1, b, Q2, c,.. -> d Example 3 Which of the following diagrams correctly describes the behavior of the following circuit, with a DFF? Ans : A Useful webb Type of FSM 15 16

Moore and Mealy Machine (Input /Output) FSM design flow Start with counting states Complete the State diagram represent in form of state transition table similar to a truth-table

17 Implementation flip-flop for state register combinational logic for next state and output logic 18 Example 4 From state transition diagram to truth table for the flow diagram Four

5 Moore and Mealy Machine (Input /Output) FSM design flow Start with counting states Complete the State diagram represent in form of state transition table similar to a truth-table State encoding decide coding for states work out the Boolean equation Moore Machine Less integrated Safer for use.. Mealy Machine Less gates. faster or slower? 17 Implementation flip-flop for state register combinational logic for next state and output logic 18 Example 4 From state transition diagram to truth table for the flow diagram Four states Two-bit registers q / q* : Present / Next state Z : Output Mealy Machine : current state and input Moore Machine : current state From truth table to K-map A B D A D B D A D B Input (x) Output (z) 19 20

From K-map to circuit Logic for state transition

with input x that can be A down counter when x = 0 (

01 11 10 00 ) State register D A D B D A D B 21 22

Design a state machine with input A and output B

Logic diagram with logic, output logic and memory 23

6 From K-map to circuit Logic for state transition Logic for output Example 5 Design a 2-bit counter with input x that can be A down counter when x = 0 ( ) A Johnson counter when x = 1 ( ) State register D A D B D A D B K-map to Circuit Example 6 : <110> pattern detector Design a state machine with input A and output B Minimize number of state Transition/output table Logic diagram with logic, output logic and memory 23 Ack : 24

7 Solution 6 : State table and diagram Moore State Machine Solution 6 : K map Mealy State Machine : current state with input Code the next state NEXT First 1 B can be obtained from table input output Wait for the <110> 25 A : Input D1, D2 : next state Q1, Q2 : current state B : Output Solution 6 : circuit Example 7 When interfacing an external signal into the FPGA, it is possible that the internal digital signal may bounce between 1 and 0 when the external voltage is very close to the threshold voltage. To solve this problem, a digital debounce circuit can be used. Next state Logic state register (Logic for transition) (memory) D1 = Q1Q2 + Q2A D2 = A B = Q1Q2 output logic A simple debounce circuit operates as follows: If the output is 0, it is changed to 1 only after two consecutive 1 s have been present in the input. If the output is 1, it is changed to 0 only after two consecutive 0 s have been present in the input. Similarly, FSM for any pattern could be generated, TRY some 27 28

The debounce (two times) logic is implemented as a state machine with the following

Current output is 1 SEEN0 10 encountered a 0 but is not changing output yet SEEN1 11

output from switch Draw a state transition diagram. Input is din; Output is dout.

Moore machine. Express the output dout in terms of s1 and s0.

encountered a 1 but is not changing output yet Ex: OUT 0 OUT 1 Next state of OUT 0

dout = ns0 ns1 K-map Current state din Next state dout OUT0 0 OUT0 0 OUT0 1 SEEN1 0

s0) SEEN1 0 OUT0 0 SEEN1 1 OUT1 1 Current state S1 S0 din Next state ns1 ns0 dout

OUT1 0 1 1 SEEN0 1 0 0 OUT0 0 0 0 SEEN0 1 0 1 OUT1 0 1 1 dout SEEN1 1 1 0 OUT0 0 0 0

8 The debounce (two times) logic is implemented as a state machine with the following states: State Encoding (s1 s0) Description OUT0 00 Current output is 0 OUT1 01 Current output is 1 SEEN0 10 encountered a 0 but is not changing output yet SEEN1 11 encountered a 1 but is not changing output yet Expected output from switch Actual output from switch Draw a state transition diagram. Input is din; Output is dout. Output of the state machine (dout) should be specified within the state as it is a Moore machine. Express the output dout in terms of s1 and s0. 29 Solution 7 State Encoding (s1 s0) Description OUT0 00 Current output is 0 OUT1 01 Current output is 1 SEEN0 10 encountered a 0 but is not changing output yet SEEN1 11 encountered a 1 but is not changing output yet Ex: OUT 0 OUT 1 Next state of OUT 0 din=0 OUT0 din=1 SEEN1 Next state of SEEN1 din=0 OUT0 din=1 OUT1 30 Next state logic. dout = ns0 ns1 K-map Current state din Next state dout OUT0 0 OUT0 0 OUT0 1 SEEN1 0 OUT1 0 SEEN0 1 ns1 OUT1 1 OUT1 1 SEEN0 0 OUT0 0 SEEN0 1 OUT = 1 (din s0) SEEN1 0 OUT0 0 SEEN1 1 OUT1 1 Current state S1 S0 din Next state ns1 ns0 dout ns0 OUT OUT OUT SEEN OUT SEEN OUT OUT SEEN OUT SEEN OUT dout SEEN OUT SEEN OUT dout

Circuit dout = ns0 ns1 Example 8 Combination LOCK

** dout related to din? Could it be NOT related?

into seen1a and seen1b 33 OR TWO turns during 1 CW

; RESET to START Moving the knob, arrow is the

(1) Start(3) -> A (1) -> C (2)->OPEN 1 (START) CW 3

(3) -> A (1) -> C (2) -> OPEN 1 (START) CW 3 CW 2 CW

The states and input positions are encoded with 3

9 Circuit dout = ns0 ns1 Example 8 Combination LOCK Moving the knob START from 1, CW to 3, CCW to 2 OPEN ** dout related to din? Could it be NOT related? TRY : If we have debounce for 3 times, what should be added? Split the state seen0 into seen0a and seen0b seen1 into seen1a and seen1b 33 OR TWO turns during 1 CW to 3 34 Solution 8 : State Diagram Assume START at 1 ; RESET to START Moving the knob, arrow is the adjacent next number Start, A, B states. (1) Start(3) -> A (1) -> C (2)->OPEN 1 (START) CW 3 CCW1 CCW2 (OPEN) (1) Start(3) -> A(2) -> B (1) -> D (3) -> A (1) -> C (2) -> OPEN 1 (START) CW 3 CW 2 CW 1 CW 3 CCW 1 CCW 2 (OPEN) Solution 8 : State Coding The states and input positions are encoded with 3 bits (s2 s1 s0) and 2 bits (p1 p0) respectively as shown below : Total 7 states list for 8, one is dummy (not care) Input :

Solution 8 : Input/Output ports Truth table

<1> <3> 1 <2> <1> 3 2 1 <3> 1 <2> <1> 3 2 1 3

OR (ii) CCW followed by CW <1> 2 <3> <2> <1>

With two turns from 1 to 3 39 Basic Light

To keep track of the light being displayed,

10 Solution 8 : Input/Output ports Truth table Implement the above lock control state machine in Logisim. Apart from the I/O described above, the FSM should also include CLK, and CLR The following table summarizes the input/output ports of the state machine Example 8 a - Extended Rotational Lock ( 1, 3, 2 ) could be OPEN by Example 9 Traffic Light EITHER (i) CW followed by CCW, <1> <3> 1 <2> <1> <3> 1 <2> <1> <3> 1 <2>. OR (ii) CCW followed by CW <1> 2 <3> <2> <1> <3> <2> <1> <3> <2>. With two turns from 1 to 3 39 Basic Light Control State Transition Diagram Begin by implementing the basic pedestrian light control as a finite state machine. To keep track of the light being displayed, it have determined the FSM can be in one of the four (4) states: 2 states for red (Red1, Red2), 1 state for green (Green), and 1 state for flashing green (Green Flash). 40

Example 9 : State Transition Diagram A timer signal t (CLK) serves as input to your FSM. The signal t is set to `1' for 1 clock cycle every 30 seconds.

If r is set to `1', the red light is on. When f is set to `1', the light flashes, otherwise, the light stay solid.

output r 1 to turn on red light, 0 otherwise. g 1 to turn on green light, 0 otherwise. f 1 to flash light, 0 otherwise.

41 42 Next State and Output Logic The state encoding for the four states is as followed : State s1 s0 RED1 0 0 RED2 0 1 GREEN FLASH 1 0 GREEN 1 1 Following

11 Example 9 : State Transition Diagram A timer signal t (CLK) serves as input to your FSM. The signal t is set to `1' for 1 clock cycle every 30 seconds. It is `0' otherwise. This signal controls the switching of light. The FSM produces 3 output : r, g, f. If g is set to `1', the green light is on. If r is set to `1', the red light is on. When f is set to `1', the light flashes, otherwise, the light stay solid. The following table summarizes the I/O signals for the pedestrian light control : Type Name Description input t 1 every 30 seconds have passed, 0 otherwise. output r 1 to turn on red light, 0 otherwise. g 1 to turn on green light, 0 otherwise. f 1 to flash light, 0 otherwise. For sake of hardware implementation, assume the clock is running at 1 Hz. The FSM resets to Red Next State and Output Logic The state encoding for the four states is as followed : State s1 s0 RED1 0 0 RED2 0 1 GREEN FLASH 1 0 GREEN 1 1 Following is the truth table of the next state and output logic of the traffic light control state machine. K-map and circuit Complete with K-map for Boolean expressions : Next state : s0, s1, t ns1, ns0 Output : s0, s1, t r, g, f Logisim to have the circuit 43 Logic Circuits : Memory : 2 DFF Logic circuits : gates 44

12 RECALL : Steps in designing a State Machine Draw a state transition diagram An initial state Other states to keep track of various activities Transitions Generate a state transition table and a output table Write state transition table and output table in binary State assignment, i.e., the code used for each state Derive canonical sum-of-product expressions K map, Logisim.. Draw the circuit Register, State Transition Logic and Output Logic Circuit 45 Examples A Design Example - Traffic Lights Finite state machine that recognizes the particular pattern FSM with outputs How To Design A Finite State Machine rial.pdf Finite State Machines & MORE -END- 46

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic ENGG 1203 Tutorial_9 - Review Boolean Algebra 1. Combinational & Sequential Logic 2. Computer Systems 3. Electronic Circuits 4. Signals, Systems, and Control Remark : Multiple Choice Questions : ** Check