6. Finite State Machines

Transcription

1 6. Finite State Machines 6.4x Computation Structures Part Digital Circuits Copyright 25 MIT EECS 6.4 Computation Structures L6: Finite State Machines, Slide #

2 Our New Machine Clock State Registers k Current State Combinational Logic k Next State Input m n Output Engineered cycles Works only if dynamic discipline obeyed Remembers k bits for a total of 2 k unique combinations Acyclic graph Obeys static discipline Can be exhaustively enumerated by a truth table of 2 k+m rows and k+n output columns 6.4 Computation Structures L6: Finite State Machines, Slide #2

3 A Simple Sequential Circuit Lets make a digital binary Combination Lock: IN CLK How many state bits do I need? Lock U Specification: One input ( or ) One output ( Unlock signal) UNLOCK is if and only if: Last 4 inputs were the combination : 6.4 Computation Structures L6: Finite State Machines, Slide #3

4 Abstraction du jour: Finite State Machines inputs m Clocked FSM n outputs A FINITE STATE MACHINE has k STATES: S S k (one is initial state) m INPUTS: I I m n OUTPUTS: O O n Transition Rules: s (s, I) for each state s and input I Output Rules: Out(s) or Out(s, I) for each state s and input I 6.4 Computation Structures L6: Finite State Machines, Slide #4

5 State Transition Diagram Why do these go to S and S? SX U= S U= S U= S U= S U= Designing our lock Need an initial state; call it SX. Must have a separate state for each step of the proper entry sequence Must handle other (erroneous) entries NAME of state OUTPUT when in this state Heavy circle Means INITIAL state XXX U= INPUT causing transition 6.4 Computation Structures L6: Finite State Machines, Slide #5

6 S S3 S2 MOORE Machine: Outputs on States Valid State Diagrams Inputs/outputs S S3 / / / / / S2 / MEALY Machine: Outputs on Transitions Arcs leaving a state must be: () mutually exclusive can t have two choices for a given input value (2) collectively exhaustive every state must specify what happens for each possible input combination. Nothing happens means arc back to itself. 6.4 Computation Structures L6: Finite State Machines, Slide #6

7 State Transition Diagram as a Truth Table SX U= S U= IN Current State S U= S U= S U= Next State Unlock SX S SX SX S S S S S S S S S S S SX S S S S The assignment of codes to states can be arbitrary, however, if you choose them carefully you can greatly reduce your logic requirements. All state transition diagrams can be described by truth tables Binary encodings are assigned to each state (a bit of an art) The truth table can then be simplified using the reduction techniques we learned for combinational logic 6.4 Computation Structures L6: Finite State Machines, Slide #7

8 We assume inputs are synchronized with clock Now Put It In Hardware! IN ROM 6x4 4 inputs 2 4 locations, each location supplies 4 bits unlock Current state Next state states 3-bit encoding Trigger update periodically ( clock ) 6.4 Computation Structures L6: Finite State Machines, Slide #8

9 Discrete State, Discrete Time inputs STATE s ROM outputs NEXT s Two design choices: () outputs only depend on state (Moore) (2) outputs depend on inputs + state (Mealy) s state bits 2 s possible states Clock STATE NEXT Clock Period Clock Period 2 Clock Period 3 Clock Period 4 Clock Period Computation Structures L6: Finite State Machines, Slide #9

10 Housekeeping Issues inputs STATE s ROM or gates outputs NEXT s. Initialization? Clear the memory? 2. Unused state encodings? - waste ROM (use gates) - what does it mean? - can the FSM recover? initial 3. Choosing encoding for state? reset U 4. Synchronizing input changes with state update? IN CLK Now, that s a funny looking state machine 6.4 Computation Structures L6: Finite State Machines, Slide #

11 FSM States. What can you say about the number of states? k ROM k 2. Same question: m States x y z n States 3. Here s an FSM. Can you discover its rules? 6.4 Computation Structures L6: Finite State Machines, Slide #

12 What s My Transition Diagram? =OFF, =ON? vs. "" = Surprise! If you know NOTHING about the FSM, you re never sure! If you have a BOUND on the number of states, you can discover its behavior: K-state FSM: Every (reachable) state can be reached in < k steps. BUT... FSMs may be equivalent! 6.4 Computation Structures L6: Finite State Machines, Slide #2

13 FSM Equivalence vs. ARE THEY DIFFERENT? NOT in any practical sense! They are EXTERNALLY INDISTINGUISHABLE, hence interchangeable. FSMs are EQUIVALENT iff every input sequence yields identical output sequences. ENGINEERING GOAL: HAVE an FSM which works... WANT simplest (ergo cheapest) equivalent FSM. 6.4 Computation Structures L6: Finite State Machines, Slide #3

14 Let s Build a RoboAnt 8 legs? SENSORS: antennae L and R, each if in contact with something. ACTUATORS: Forward Step F, ten-degree turns TL and TR (left, right). GOAL: Make our ant smart enough to get out of a maze like: STRATEGY: "Right antenna to the wall" 6.4 Computation Structures L6: Finite State Machines, Slide #4

15 Lost In Space? Action: Go forward until we hit something. LOST F L+R lost is the initial state 6.4 Computation Structures L6: Finite State Machines, Slide #5

16 Bonk! Action: Turn left (CCW) until we don t touch anymore L+R LOST F L+R RCCW TL 6.4 Computation Structures L6: Finite State Machines, Slide #6

17 A Little to the Right Action: Step and turn right a little, look for wall L+R LOST F L+R RCCW TL R Wall TR,F _ R 6.4 Computation Structures L6: Finite State Machines, Slide #7

18 Then a Little to the Left Action: Step and turn left a little, till not touching (again) LOST L+R RCCW L+R Wall2 _ F TL L TL,F R Wall TR,F _ R 6.4 Computation Structures L6: Finite State Machines, Slide #8

19 Dealing With Outside Corners Action: Step and turn right until we hit perpendicular wall LOST L+R RCCW L+R Wall2 _ F TL Wall TR,F _ R R L TL,F R Corner TR,F _ R Hey, this might even work! 6.4 Computation Structures L6: Finite State Machines, Slide #9

20 Equivalent State Reduction Observation: two states are equivalent if. Both states have identical outputs; AND 2. Every input equivalent states. Reduction Strategy: Find pairs of equivalent states, MERGE them. LOST L+R RCCW L+R Wall2 _ F TL L TL,F Wall TR,F _ R R R Corner TR,F _ R 6.4 Computation Structures L6: Finite State Machines, Slide #2

21 An Evolutionary Step Merge equivalent states Wall and Corner into a single new, combined state. LOST L+R RCCW L+R Wall2 _ F TL L TL,F R Wall TR,F _ R Behaves exactly as previous (5-state) FSM, but requires half the ROM in its implementation! 6.4 Computation Structures L6: Finite State Machines, Slide #2

22 Building The Transition Table LOST F L+R RCCW TL L+R S S TR TL F Computation Structures L6: Finite State Machines, Slide #22

23 Implementation Details LOST RCCW WALL WALL2 S S TR TL F Complete Transition table S S S LR S! + = SS + LS LRS S S S LR S! + = R + LS LS 6.4 Computation Structures L6: Finite State Machines, Slide #23

24 Ant Schematic 6.4 Computation Structures L6: Finite State Machines, Slide #24

25 FSMs All the Way Down? More than ants: Swarming, flocking, and schooling can result from collections of very simple FSMs Perhaps most physics: Cellular automata, arrays of simple FSMs, can more accurately model fluids than numerical solutions to PDEs Did we all descend from FSMs??? I prefer to think we ascended What if: We replaced the ROM with a RAM and have outputs that modify the RAM?... You'll see FSMs for the rest of your life! 6.4 Computation Structures L6: Finite State Machines, Slide #25

26 The World Doesn t Run on Our Clock! What if each button input is an asynchronous / level? B B Lock U But what about the dynamic discipline? To build a system with asynchronous inputs, we have to break the rules: we cannot guarantee that setup and hold time requirements are met at the inputs! So, we need a synchronizer at each input: U(t) (Unsynchronized) Synchronizer (Synchronized) 6.4 Computation Structures L6: Finite State Machines, Slide #26 S(t) Clock Valid except for brief periods following active clock edges

27 IN: CLK: The Bounded-time Synchronizer a t t IN a t t C A classic problem IN CLK UNSOLVABLE Sync S For NO finite values of t E and t D is this spec realizable, even with reliable components! Synchronizer specifications: finite t D (decision time) IN: finite t E (allowable error) CLK: value of S at time t C +t D : if t IN < t C t E S: if t IN > t C + t E, otherwise > t E CASE t D > t E t D CASE 2 CASE 3 t D 6.4 Computation Structures L6: Finite State Machines, Slide #27

28 Unsolvable? That can t be true Let s just use a D Register: IN: CLK: a t t IN a t t C D Q DECISION TIME is T PD of register. ALLOWABLE ERROR is max(t SETUP, t HOLD ) Our logic: T PD after T C, we ll have We re lured by the digital abstraction into assuming that Q must be either or. But let s look at the input latch in the flip flop when IN and CLK change at about the same time... IN CLK Q= iff t IN + t SETUP < t C Q= iff t C + t HOLD < t IN Q= or otherwise. D Q master G G D Q slave 6.4 Computation Structures L6: Finite State Machines, Slide #28

29 The Mysterious Metastable State V in V out Q Y V out VTC of closed latch Latched in a state Recall that the latch output is the solution to two simultaneous constraints:. The VTC of path thru MUX; and 2. V in = V out Latched in a state Latched in an undefined state VTC of feedback path (V in =V out ) V in In addition to our expected stable solutions, we find an unstable equilibrium in the forbidden zone called the Metastable State 6.4 Computation Structures L6: Finite State Machines, Slide #29

30 Metastable State: Properties. It corresponds to an invalid logic level. 2. It s an unstable equilibrium; a small perturbation will cause it to move toward a stable or. 3. It will settle to a valid or... eventually. 4. BUT depending on how close it is to the V in =V out fixed point of the device it may take arbitrarily long to settle out. 5. EVERY bistable system exhibits at least one metastable state! If metastable at t : metastable state p(metastable at t +T) > for finite T p(metastable at t +T) decreases exponentially with increasing T 6.4 Computation Structures L6: Finite State Machines, Slide #3

31 Solution: Delay Increases Reliability Extra registers between the asynchronous input and your logic are the best insurance against metastable states. For higher clock rates, consider adding additional registers. In Clk D Q A metastable state here will probably resolve itself to a valid level before it gets into my circuit. D Q Combinational logic D Q Out And one here will almost certainly get resolved. Quarantine time reduces p(metastable) In D Q D Q D Q Combinational logic D Q Out Clk 6.4 Computation Structures L6: Finite State Machines, Slide #3