EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

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1 EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2 q q 0 reset D Q D Q D Q D Q S R S R S R S R d 3 d 2 d d 0 Load-enable is a popular option: q 3 q 2 q q 0 reset load D Q D Q D Q D Q S R S R S R S R Xilinx flip-flops employ a clock enable (CE) for same purpose. d 3 d 2 d d 0 Spring 2005 EECS50 - Lec-counters Page 2

Plain shift register: Shift Registers Shifter with shift-enable input Verilog: assign OUT = Q[0]; always @ (posedge clk) if (shiftenable) Q <= {IN; Q[3:]}; else Q <= Q; FPGA FFs have clock-enable

2 Plain shift register: Shift Registers Shifter with shift-enable input Verilog: assign OUT = Q[0]; (posedge clk) if (shiftenable) Q <= {IN; Q[3:]}; else Q <= Q; FPGA FFs have clock-enable (CE), therefore muxes are not needed. Spring 2005 EECS50 - Lec-counters Page 3 Parallel load shift register: Shift-registers Parallel-to-serial converter Also, works as Serial-to-parallel converter, if q values are connected out. Spring 2005 EECS50 - Lec-counters Page 4 2

3 Universal Shift-register Spring 2005 EECS50 - Lec-counters Page 5 Counters Special sequential circuits (FSMs) that repeatedly sequence through a set of outputs. Examples: binary counter: 000, 00, 00, 0, 00, 0, 0,, 000, 00, gray code counter: 000, 00, 0, 00, 0,, 0, 00, 000, 00, 0, one-hot counter: 000, 000, 000, 000, 000, 000, BCD counter: 0000, 000, 000,, 00, 0000, 000 pseudo-random sequence generators: 0, 0, 00,, 0, 0, 00,... Moore machines with ring structure in State Transition Diagram: S3 S0 S2 S Spring 2005 EECS50 - Lec-counters Page 6 3

4 What are they used? Counters are commonly used in hardware designs because most (if not all) computations that we put into hardware include iteration (looping). Examples: Shift-and-add multiplication scheme. Bit serial communication circuits (must count one words worth of serial bits. Other uses for counter: Clock divider circuits 6MHz 64 Systematic inspection of data-structures Example: Network packet parser/filter control. Counters simplify controller design by: providing a specific number of cycles of action, sometimes used in with a decoder to generate a sequence of control signals. Think about using a counter when many FSM states with few branches. Spring 2005 EECS50 - Lec-counters Page 7 A Standard High-level Organization Controller accepts external and control input, generates control and external output and sequences the movement of data in the datapath. Datapath is responsible for data manipulation. Usually includes a limited amount of storage. Memory optional block used for long term storage of data structures. Standard model for CPUs, micro-controllers, many other digital sub-systems. (Remember MIPS processor from 6C) Controllers are the most common use of FSMs. Spring 2005 EECS50 - Lec-counters Page 8 4

Multiplication a 3 a 2 a a 0 Multiplicand b 3 b 2 b b 0 Multiplier X a 3 b 0 a 2 b 0 a b 0 a 0 b 0 a 3 b a 2 b a b a 0 b Partial a 3 b 2 a 2 b 2 a b 2 a 0 b 2 products a 3 b 3 a 2 b 3 a b 3 a 0 b 3.

5 Multiplication a 3 a 2 a a 0 Multiplicand b 3 b 2 b b 0 Multiplier X a 3 b 0 a 2 b 0 a b 0 a 0 b 0 a 3 b a 2 b a b a 0 b Partial a 3 b 2 a 2 b 2 a b 2 a 0 b 2 products a 3 b 3 a 2 b 3 a b 3 a 0 b 3... a b 0 +a 0 b a 0 b 0 Product Many different circuits exist for multiplication. Each one has a different balance between speed (performance) and amount of logic (cost). Spring 2005 EECS50 - Lec-counters Page 9 Controller using Counters Example, Bit-serial multiplier (n 2 cycles, one bit of result per n cycles): Control Algorithm: repeat n cycles { // outer (i) loop repeat n cycles{ // inner (j) loop shifta, selectsum, shifthi } Note: The occurrence of a control shiftb, shifthi, shiftlow, reset signal x means x=. The absence } of x means x=0. Spring 2005 EECS50 - Lec-counters Page 0 5

6 Controller using Counters State Transition Diagram: Assume presence of two binary counters. An i counter for the outer loop and j counter for inner loop. START IDLE CE i,ce j RST i START CE CLK RST counter TC TC is asserted when the counter reaches it maximum count value. CE is count enable. The counter increments its value on the rising edge of the clock if CE is asserted. TC i OUTER <outer contol> CE i,ce j RST j TC i INNER <inner contol> CE i,ce j TC j TC j Spring 2005 EECS50 - Lec-counters Page Controller using Counters Controller circuit implementation: Outputs: CE i = q 2 START IDLE S R q 0 CE j = q RST i = q 0 RST j = q 2 TCi TCj INNER S R OUTER S R q q 2 Global reset shifta = q shiftb = q 2 shiftlow = q 2 shifthi = q + q 2 reset = q 2 selectsum = q Spring 2005 EECS50 - Lec-counters Page 2 6

7 How do we design counters? For binary counters (most common case) incrementer circuit would work: + register In Verilog, a counter is specified as: x = x+; This does not imply an adder An incrementer is simpler than an adder And a counter is simpler yet. In general, the best way to understand counter design is to think of them as FSMs, and follow general procedure, however some special cases can be optimized. Spring 2005 EECS50 - Lec-counters Page 3 Binary Counter Design: Start with 3-bit version and generalize: Synchronous Counters All outputs change with clock edge. c b a c + b + a a + b + c + a + = a b + = a b cb a c + = a c + abc + b c = c(a +b ) + c (ab) = c(ab) + c (ab) = c ab a b c Spring 2005 EECS50 - Lec-counters Page 4 7

8 Synchronous Counters How do we extend to n-bits? Extrapolate c + : d + = d abc, e + = e abcd a + b + c + d + a b c Has difficulty scaling (AND gate inputs grow with n) d CE a + b + c + d + TC a b c d CE is count enable, allows external control of counting, TC is terminal count, is asserted on highest value, allows cascading, external sensing of occurrence of max value. Spring 2005 EECS50 - Lec-counters Page 5 Synchronous Counters CE a + b + c + d + TC How does this one scale? Delay grows α n a b c Generation of TC signals very similar to generation of carry signals in adder. Parallel Prefix circuit reduces delay: d log 2 n log 2 n Spring 2005 EECS50 - Lec-counters Page 6 8

Up-Down Counter c b a c + b + a + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

logic can be added to terminate count before max value is reached: Example: count to

9 Up-Down Counter c b a c + b + a Down-count Spring 2005 EECS50 - Lec-counters Page 7 Odd Counts Extra combinational logic can be added to terminate count before max value is reached: Example: count to 2 Alternative: load 4 4-bit binary counter TC Spring 2005 EECS50 - Lec-counters Page 8 9

10 Ring Counters one-hot counters 000, 000, 000, 000, 000, q 3 q 2 q What are these good for? q 0 reset D Q D Q D Q D Q S R S R S R S R Self-starting version: q 3 q 2 q q 0 D Q D Q D Q D Q Spring 2005 EECS50 - Lec-counters Page 9 Johnson Counter Spring 2005 EECS50 - Lec-counters Page 20 0

11 Ripple counters A 3 A 2 A A time Each stage is 2 of previous. Look at output waveforms: CLK A 0 A A 2 A 3 Often called asynchronous counters. A T flip-flop is a toggle flip-flop. Flips it state on cycles when T=. Spring 2005 EECS50 - Lec-counters Page 2

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters October 24, 2002 John Wawrzynek Fall 2002 EECS150 - Lec18-counters Page 1 Counters Special sequential circuits (FSMs) that sequence though a set outputs.