Sequential vs. Combinational

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Wendy Campbell
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1 Sequential Circuits

2 Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current input but also on current state of the system (which depends on past input values) TV channel selector (up-down) Need some type of memory to remember the current state 2

3 Sequential Logic Sequential Logic circuits Remember past inputs and past circuit state. Outputs from the system are fed back as new inputs. The storage elements are circuits that are capable of storing binary information: memory. 3

4 Feedback Loop Feedback: A signal s depends on another signal whose value depends on s (perhaps with several intermediate signals). s 4

5 Base of Memory Consider the following circuit: It can differentiate between two different states as it has only one feedback line that can keep one of two values, or. A circuit with n feedback lines has 2 n potential states, and that the memory of our circuit depends on the number of its feedback lines: 5

6 Synchronous vs. Asynch. Synchronous sequential circuit: the behavior can be defined from knowledge of its signal at discrete instants of time. achieves synchronization by using a timing signal called the clock. Asynchronous sequential circuit: the behavior is dependent on the order of input signal changes over continuous time, and output can change at any time (clockless). 6

7 Clock Signal Rising Clock Edge Clock generator: Periodic train of clock pulses Different duty cycles Falling Clock Edge 7

8 Clock Signal Clock is distributed throughout the whole design All components synchronizes itself with it. 8

9 Synchronous Circuits Combinational Logic clk time 9

10 SR latch (NOR version) R Q R S S Q Truth Table: Next State = F(S, R, Current State) S(t) R(t) Q(t) Q(t+) (hold) (Hold) (reset) (reset) (set) (set) Not allowed Not allowed

11 SR Latch Truth Table: Next State = F(S, R, Current State) Derived K-Map: S(t) R(t) Q(t) Q(t+) (hold) (Hold) (reset) (reset) (set) (set) Not allowed Not allowed Characteristic Equation: S R R-S Latch Q+ Q+ = S + R Q t Q

12 R=S=?? Illegal output, because When S=R=, both outputs go to zero. If both inputs now go to, the state of the SR flip flop is depends on which input remains a longer before making transition to. Hence, undefined state. MUST be avoided. 2

13 Timing Diagram Reset Hold Set Reset Set Race R S Q Q Forbidden State Forbidden State 3

14 Timing Diagram of SR Latch 4

15 SR Latch State Diagram Observed State Diagram Q Q Q Q Q Q Very difficult to observe R-S Latch in the - state Ambiguously returns to state - or - 5

16 S R Latch (NAND version) S R Q Q S R Q Q Set S R R-S Latch Q Q X Y NAND 6

17 S R Latch (NAND version) S R Q Q S R Q Q Set Hold X Y NAND 7

18 S R Latch (NAND version) S R Q Q S R Q Q Set Reset Hold X Y NAND 8

19 S R Latch (NAND version) S R Q Q X Y NAND S R Q Q Set Reset Hold Hold 9

20 S R Latch (NAND version) S R Q Q X Y NAND S R Q Q Disallowed Set Reset Hold Hold 2

21 SR Latch with Control (Enable) S S Q C R R Q S R C S R Q Q Q Q Store Reset Set Disallowed X X Q Q Store 2

22 D Latch S-R latches are useful in control applications, where we often think in terms of setting a flag in response to some condition, and resetting it when conditions change We often need latches simply to store bits presented on a signal line D latch Can eliminate the undesirable indeterminate state in the RS flip flop: ensure that inputs S and R are never simultaneously. This is done in the D latch: D C D Latch Q Q 22

23 D Latch (cont.) D S S Q C R R Q D C Q Q X Q Q S R C Q Q Q Q Store Reset Set Disallowed X X Q Q Store 23

24 D Latch Timing Diagram D C D Latch Q Q C 24

25 D-Latch Circuit D C D Latch Q Q C D Q Q+ C D Q Q C D Q+ = C.Q + C.D 25

26 D Latch with Transmission Gates 2 C= TG closes and TG2 opens Q =D and Q=D C= TG opens and TG2 closes Hold Q and Q 26

27 JK Latch J Q J, K both one yields toggle K Q J(t) K(t) Q(t) Q(t+) (hold) (Hold) (reset) (reset) (set) (set) (toggle) (toggle) J K Q Q Derived K-Map: JK Q ( t ) J-K Latch K Characteristic Equation: Q+ = Q K + Q J J 27

28 JK Latch Using SR Latch How to eliminate the forbidden state in SR? Idea: use output feedback to guarantee that R and S are never both one J, K both one yields toggle J K S R R-S latch Q Q Q Q J(t) K(t) Q(t) Q(t+ ) HOLD RESET SET Characteristic Equation: Q+ = Q K + Q J TOGGLE 28

29 JK Latch Race Condition Set Reset Toggle Toggle Correctness: Single State change per clocking event Solution: Master/Slave Flipflop 29

30 Flip-Flops Latches are transparent (= any change on the inputs is seen at the outputs immediately). This causes synchronization problems! Solution: use latches to create flipflops that can respond (update) ONLY on SPECIFIC times (instead of ANY time). 3

31 Alternatives in FF choice Type of FF RS D JK T 3

32 D-FF Timing for D Flip-Flop (Falling-Edge Trigger) Truth table 32

33 Symbols 33

34 Compare 3 Types 34

35 Rising Edge D-FF What About Falling-Edge Circuit? 35

36 Setup & Hold Time and Propagation Delay Setup time: D input must be stable for a certain amount of time before the active edge of clock cycle Hold time: D input must be stable for a certain amount of time after the active edge of the clock Propagation Delay (Clock-to-Output): from the time the clock changes to the time the output changes Propagation Delay (Data-to-Output): from the time the data changes to the time the output changes 36

37 Setup & Hold Time and Propagation Delay Setup and Hold Times for an Edge-Triggered D Flip-Flop t plh may be different from t phl t p clock-to-output vs. t p D-to-output 37

38 Timing Parameters of a D-Latch t su not met in D-latch there may be SR-like metastability. 38

39 Edge-Triggered D Flip-Flop Determination of Minimum Clock Period 39

40 Master-Slave FF configuration using SR latches Enables level-triggered behavior 4

41 S R CLK Q Q Master-Slave FF configuration using SR latches (cont.) Q Q Store Reset Set Disallowed X X Q Q Store When C=, master is enabled and stores new data, slave stores old data. When C=, master s state passes to enabled slave (Q=Y), master not sensitive to new data (disabled). Master Slave 4

42 Master-Slave J-K Flip-Flop 42

43 Master-Slave J-K Flip-Flop P P Sample inputs while clock high J Sample inputs while clock low Uses time to break feedback path from outputs to inputs! 's Set Reset Catch T oggle K C P P Q Q Master outputs Slave outputs Correct Toggle Operation 43

44 Edge-Triggered FF 's Catching: a -- glitch on the J or K inputs leads to a state change! forces designer to use hazard-free logic Solution: edge-triggered logic Negative Edge-Triggered D flipflop 4-5 gate delays setup, hold times necessary to successfully latch the input Negative edge-triggered FF when clock is high Characteristic Equation: Q+ = D 44

45 T Flip-Flop T Flip-Flop Timing Diagram for T Flip-Flop (Falling-Edge Trigger) 45

46 Implementation of T-FF Implementation of T Flip-Flop 46

47 FFs with Additional Inputs D Flip-Flop with Clock Enable The characteristic equation : The MUX output : 47

48 Asynchronous Preset/Clear Many times it is desirable to asynchronously (i.e., independent of the clock) set or reset FFs. D S Q Example: At power-up to that we can start from a known state. C R Q Asynchronous set == direct set == Preset Asynchronous reset == direct reset == Clear There may be synchronous preset and clear. 48

49 Asynchronous Set/Reset S J K R C IEEE standard graphics symbol for JK- FF with direct set & reset Cn indicates that Cn controls all other inputs whose label starts with n. In this case, C controls J and K. Function Table S R C J K Q(t+) X X X Preset X X X Clear X X X Undefined Q(t) Hold Reset Set Q(t) -- Complement 49

50 Asynchronous Inputs 5

51 Synchronous Reset 5

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate