9.1. Unit 9. Implementing Combinational Functions with Karnaugh Maps or Memories
|
|
- Silas Cameron
- 6 years ago
- Views:
Transcription
1 . Unit Implementing Combinational Functions with Karnaugh Maps or Memories
2 . Outcomes I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth table)
3 . A new way to synthesize your logic functions KARNAUGH MAPS
4 . Logic Function Synthesis Given a function description as a T.T. or canonical form, how can we arrive at a circuit implementation or equation (i.e. perform logic synthesis)? First method Minterms / maxterms Can simplify to find minimal -level implementation Use "off-the-shelf" decoder + gate per output New, second method Karnaugh Maps Minimal -level implementation (though not necessarily minimal -, -, level implementation)
5 . Gray Code Different than normal binary ordering Reflective code When you add the (n+) th bit, reflect all the previous n-bit combinations Consecutive code words differ by only -bit differ by only -bit when you move to the next bit, reflect the previous combinations differ by only -bit -bit Gray code differ by only -bit -bit Gray code
6 . Karnaugh Maps If used correctly, will always yield a minimal, - level implementation There may be a more minimal -level, -level, - level implementation but K-maps produce the minimal two-level (SOP or POS) implementation Represent the truth table graphically as a series of adjacent squares that allows a human to see where variables will cancel
7 . Karnaugh Map Construction Every square represents input combination Must label axes in Gray code order Fill in squares with given function values F=Σ XYZ (,,,) G=Σ YZ (,,,,,,,,,,) XY Z YZ Variable Karnaugh Map Variable Karnaugh Map
8 . Karnaugh Maps W X Y Z F YZ
9 . Karnaugh Maps Squares with a '' represent minterms Squares with a '' represent maxterms YZ Maxterm: w + x + y + z Maxterm: w + x + y + z Minterm: w x y z Minterm: w x y z
10 . Karnaugh Maps Groups of adjacent s will always simplify to smaller product term than just individual minterms XY Z F=Σ XYZ (,,,,) Variable Karnaugh Map
11 . Karnaugh Maps Groups of adjacent s will always simplify to smaller product term than just individual minterms F=Σ XYZ (,,,,) XY Z Variable Karnaugh Map = m + m + m + m = x y z + x yz + xyz + xy z = z (x y + x y + xy + xy ) = z (x (y +y) + x(y+y )) = z (x +x) = z = m + m = xy z + xy z = xy (z +z) = xy
12 . Karnaugh Maps Adjacent squares differ by -variable This will allow us to use T = AB + AB = A or T = (A+B )(A+B) = A Variable Karnaugh Map Variable Karnaugh Map Difference in X: & XY x yz + xyz Z = yz Difference in Y: & x yz + x y z = x z = = = = Difference in Z: & x yz + x yz = x y Adjacent squares differ by -bit YZ = = = = = Adjacent squares differ by -bit
13 . Karnaugh Maps adjacent s (or s) differ by only one variable adjacent s (or s) differ by two variables,, adjacent s (or s) differ by,, variables By grouping adjacent squares with s (or s) in them, we can come up with a simplified expression using T (or T for s) w x y z + w x y z + w x y z + w x y z = w z w z are constant while all combos of x and y are present (x y, x y, xy, xy) YZ (w +x +y+z) (w +x +y+z ) = (w +x +y) w x y z + w x y z = w y z
14 . K-Map Grouping Rules Cover the 's [=on-set] or 's [=off-set] with as few groups as possible, but make those groups as large as possible Make them as large as possible even if it means "covering" a (or ) that's already a member of another group Make groups of,,,,... and they must be rectangular or square in shape. Wrapping is legal
15 . Group These K-Maps XY Z YZ XY Z
16 . Karnaugh Maps YZ Cover the remaining with the largest group possible even if it reuses already covered s
17 . Karnaugh Maps Groups can wrap around from: Right to left Top to bottom Corners YZ YZ F = X Z + Z F = X Z
18 . Group This YZ
19 . K-Map Translation Rules When translating a group of s, find the variable values that are constant for each square in the group and translate only those variables values to a product term Grouping s yields SOP When translating a group of s, again find the variable values that are constant for each square in the group and translate only those variable values to a sum term Grouping s yields POS
20 . Karnaugh Maps (SOP) W X Y Z F YZ F =
21 . Karnaugh Maps (SOP) W X Y Z F Y YZ F = Y
22 . Karnaugh Maps (SOP) W X Y Z F YZ Z W F = Y + W Z +
23 . Karnaugh Maps (SOP) W X Y Z F YZ Z X F = Y + W Z + X Z X
24 . Karnaugh Maps (POS) W X Y Z F YZ F =
25 . Karnaugh Maps (POS) W X Y Z F Y,Z YZ F = (Y+Z)
26 . Karnaugh Maps (POS) W X Y Z F Y YZ F = (Y+Z)(W +X +Y)
27 . Karnaugh Maps Groups can wrap around from: Right to left Top to bottom Corners Z YZ X X Z YZ X X Z Z Z F = X Z + Z F = X Z
28 . Exercises YZ YZ F SOP = F POS = P= XYZ (,,,) P=
29 . No Redundant Groups YZ
30 . Multiple Minimal Expressions For some functions, multiple minimal expressions (multiple minimal groups) exist Pick one YZ Pick either one
31 . If time permits FORMAL TERMINOLOGY FOR KMAPS
32 . Terminology Implicant: A product term (grouping of s) that covers a subset of cases where F= the product term is said to imply F because if the product term evaluates to then F= Prime Implicant: The largest grouping of s (smallest product term) that can be made Essential Prime Implicant: A prime implicant (product term) that is needed to cover all the s of F
33 . Implicant Examples W X Y Z F YZ An implicant Not PRIME because not as large as possible
34 . Implicant Examples W X Y Z F YZ An implicant Not PRIME because not as large as possible An implicant
35 . Implicant Examples W X Y Z F YZ An implicant Not PRIME because not as large as possible An implicant An essential prime implicant An essential prime implicant (largest grouping possible, that must be included to cover all s)
36 . Implicant Examples W X Y Z F An essential prime implicant YZ An implicant Not PRIME because not as large as possible An implicant An essential prime implicant An essential prime implicant (largest grouping possible, that must be included to cover all s)
37 . Implicant Examples W X Y Z F An essential prime implicant A prime implicant, but not an ESSENTIAL implicant because it is not needed to cover all s in the function YZ An implicant Not PRIME because not as large as possible An implicant An essential prime implicant An essential prime implicant (largest grouping possible, that must be included to cover all s)
38 . Implicant Examples W X Y Z F An implicant, but not a PRIME implicant because it is not as large as possible (should expand to combo s and ) YZ An essential prime implicant (largest grouping possible, that must be included to cover all s) An essential prime implicant
39 . K-Map Grouping Rules Make groups (implicants) of,,,,... and they must be rectangular or square in shape. Include the minimum number of essential prime implicants Use only essential prime implicants (i.e. as few groups as possible to cover all s) Ensure that you are using prime implicants (i.e. Always make groups as large as possible reusing squares if necessary)
40 - & -VARIABLE KMAPS.
41 . -Variable K-Map If we have a -variable function we need a -square KMap. Will an x matrix work? Recall K-maps work because adjacent squares differ by -bit How many adjacencies should we have for a given square?!! But drawn in dimensions we can t have adjacencies. V YZ
42 . -Variable Karnaugh Maps To represent the adjacencies of a -variable function [e.g. f(v,w,x,y,z)], imagine two x K-Maps stacked on top of each other Adjacency across the two maps YZ These are adjacent YZ Traditional adjacencies still apply (Note: v is constant for that group and should be included) => v xy Adjacencies across the two maps apply (Now v is not constant) => w xy V= V= F = v xy + w xy
43 . -Variable Karnaugh Maps adjacencies for -variables (Stack of four x maps) YZ Group of Not adjacent YZ U,V=, U,V=, YZ YZ Group of U,V=, U,V=,
44 DON'T CARE OUTPUTS.
45 . Don t-cares Sometimes there are certain input combinations that are illegal (i.e. in BCD, can never occur) The outputs for the illegal inputs are don t-cares The output can either be or since the inputs can never occur Don t-cares can be included in groups of or groups of when grouping in K-Maps Use them to make as big of groups as possible Use 'Don't care' outputs as wildcards (e.g. the blank tile in Scrabble TM ). They can be either or whatever helps make bigger groups to cover the ACTUAL 's
46 . Combining Functions Given intermediate functions F and F, how could you use AND, OR, NOT to make G Notice certain F,F combinations never occur in G(x,y,z) what should we make their output in the T.T. X Y Z F F G X Y Z F F G F F G
47 . Don t Care Example D D D D GT d d d d d d DD DD DD d d d d d d DD d d d d d d GT SOP = GT POS =
48 . Don t Care Example D D D D GT d d d d d d DD DD DD d d d d d d DD d d d d d d GT SOP = GT POS =
49 . Don t Cares W X Y Z F d d d d d d YZ d d d d d d F = Z + Y Reuse d s to make as large a group as possible to cover,, & Use these d s to make a group of
50 . Don t Cares W X Y Z F d d d d d d YZ d d d d d d F = Y+Z You can use d s when grouping s and converting to POS
51 . Designing Circuits w/ K-Maps Given a description Block Diagram Truth Table K-Map for each output bit (each output bit is a separate function of the inputs) -bit unsigned decrementer (Z = X-) If X[:] = then Z[:] =, etc. X[:] -bit Unsigned Decrementer Z[:]
52 . -bit Number Decrementer X X X Z Z Z X X X X X X X X X Z = X X + X X + X X X Z = X X + X X Z = X
53 . Squaring Circuit Design a combinational circuit that accepts a -bit number and generates an output binary number equal to the square of the input number. (B = A ) Using bits we can represent the numbers from to. The possible squared values range from to. Thus to represent the possible outputs we need how many bits?
54 . -bit Squaring Circuit Inputs Outputs A A A A B B B B B B B=A AA A B = AA AA A B = AA + AA AA A B = A
55 . -bit Squaring Circuit A A A B B B B B B
56 . USING MEMORIES TO BUILD COMBINATIONAL CIRCUITS
57 . Dimensions and Operations MEMORY BASICS
58 . Memories Memories store (write) and retrieve (read) data Read-Only Memories (ROM s): Can only retrieve data (contents are initialized and then cannot be changed) Read-Write Memories (RWM s): Can retrieve data and change the contents to store new data
59 . ROM s Memories are just tables of data with rows and columns When data is read, one entire row of data is read out The row to be read is selected by putting a binary number on the address inputs A A A Address Inputs ROM Data Outputs D D D D
60 . ROM s Example Address = dec. = bin. is provided as input ROM outputs data in that row ( bin.) A A A ROM Address: = Data: Row is output D D D D
61 . Memory Dimensions Memories are named by their dimensions: Rows x Columns n rows and m columns => n x m ROM n rows => n address bits or k rows => log k address bits m cols => m data outputs A A A n- n - n - ROM... D m- D
62 . RWM s Writable memories provide a set of data inputs for write data (as opposed to the data outputs for read data) A control signal R/W (=READ / = WRITE) is provided to tell the memory what operation the user wants to perform Address Inputs Data Inputs A A A DI DI DI DI R/W x RWM Data Outputs DO DO DO DO
63 . RWM s Write example Address = dec. = bin. DI = dec. = bin. R/W = => Write op. Data in row is overwritten with the new value of bin. Address Inputs Data Inputs R/W A A A DI DI DI DI R/W x RWM DO DO DO DO Data Outputs????
64 . Look-up tables USING MEMORIES TO BUILD COMBINATIONAL FUNCTIONS
65 . Memories as Look-Up Tables One major application of memories in digital design is to use them as LUT s (Look-Up Tables) to implement logic functions This is the core technology used by FPGAs (Field- Programmable Gate Arrays) which are used pervasively in robotics, space applications, networking, and even in search engines Idea: Use a memory to hold the truth table of a function and feed the inputs of the function to the address inputs to "look-up" the answer
66 . Implementing Functions w/ Memories x Memory x Memory X Y Z F Z Y X A A A X,Y,Z inputs look up the correct answer A A A Arbitrary Logic Function D F D Use a memory with the same dimensions as 'output' side of the truth table. It's almost TOO easy.
67 . Implementing Functions w/ Memories x Memory x Memory X Y Z C S Z Y X A A A A A A Multi-bit function (One's count) D C D S ++ = D D Use a memory with the same dimensions as 'output' side of the truth table. It's almost TOO easy.
68 . -bit Squaring Circuit Q: What size memory would you use to build our -bit squaring circuit? A: x memory Q: What would you connect to the address inputs of the memory? A: A[:] Q: What bits would you program into row of the memory? A: (i.e. = ) Inputs Outputs A A A A B B B B B B B=A
69 . x Multiplier Example Determine the dimensions of the memory that would be necessary to implement a x-bit unsigned multiplier with inputs X[:] and Y[:] and outputs P[??:] A A A A A A ROM Question: How many bits are needed for P? Question: What are the contents of the numbered rows? A A... Example: X X X X = Y Y Y Y = P = X * Y = * = = P
70 . x Multiplier Example Determine the dimensions of the memory that would be necessary to implement a x-bit unsigned multiplier with inputs X[:] and Y[:] and outputs P[??:] Question: How many bits are needed for P? Question: What are the contents of the numbered rows? Y Y Y Y X X X X A A A A A A A A... ROM Example: X X X X = Y Y Y Y = P = X * Y = * = = P P
71 . Implementing Functions w/ Memories To implement a function w/ n-variables and m outputs Just place the output truth table values in the memory Memory will have dimensions: n rows and m columns Still does not scale terribly well (i.e. n-inputs requires memory w/ n outputs) But it is easy and since we can change the contents of memories it allows us to create "reconfigurable" logic This idea is at the heart of FPGAs
Spiral 1 / Unit 5. Karnaugh Maps
-. Spiral / Unit Karnaugh Maps -. Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationOutcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationOutcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps
-. -. Spiral / Unit Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least technique to improve
More informationLecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps
EE210: Switching Systems Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps Prof. YingLi Tian Feb. 21/26, 2019 Department of Electrical Engineering The City College of New York
More informationUnit 2 Session - 6 Combinational Logic Circuits
Objectives Unit 2 Session - 6 Combinational Logic Circuits Draw 3- variable and 4- variable Karnaugh maps and use them to simplify Boolean expressions Understand don t Care Conditions Use the Product-of-Sums
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean
More informationReview for Test 1 : Ch1 5
Review for Test 1 : Ch1 5 October 5, 2006 Typeset by FoilTEX Positional Numbers 527.46 10 = (5 10 2 )+(2 10 1 )+(7 10 0 )+(4 10 1 )+(6 10 2 ) 527.46 8 = (5 8 2 ) + (2 8 1 ) + (7 8 0 ) + (4 8 1 ) + (6 8
More informationSimplifying Logic Circuits with Karnaugh Maps
Simplifying Logic Circuits with Karnaugh Maps The circuit at the top right is the logic equivalent of the Boolean expression: f = abc + abc + abc Now, as we have seen, this expression can be simplified
More informationLecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University
Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University Original Source: Aby K George, ECE Department, Wayne State University Contents The Map method Two variable
More information14:332:231 DIGITAL LOGIC DESIGN. Combinational Circuit Synthesis
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all Lecture #: Combinational Circuit Synthesis I Combinational Circuit Synthesis Recall: Combinational circuit
More informationSpiral 2-4. Function synthesis with: Muxes (Shannon's Theorem) Memories
2-4. Spiral 2-4 Function synthesis with: Muxes (Shannon's Theorem) Memories 2-4.2 Learning Outcomes I can implement logic for any truth table by using Shannon's theorem to decompose the function to create
More informationContents. Chapter 3 Combinational Circuits Page 1 of 36
Chapter 3 Combinational Circuits Page of 36 Contents Combinational Circuits...2 3. Analysis of Combinational Circuits...3 3.. Using a Truth Table...3 3..2 Using a Boolean Function...6 3.2 Synthesis of
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms
Review EECS 150 - Components and Design Techniques for Digital Systems Lec 06 Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley
More informationUNIT 5 KARNAUGH MAPS Spring 2011
UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable
More informationDigital Logic Design. Combinational Logic
Digital Logic Design Combinational Logic Minterms A product term is a term where literals are ANDed. Example: x y, xz, xyz, A minterm is a product term in which all variables appear exactly once, in normal
More informationThe Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,
More informationThis form sometimes used in logic circuit, example:
Objectives: 1. Deriving of logical expression form truth tables. 2. Logical expression simplification methods: a. Algebraic manipulation. b. Karnaugh map (k-map). 1. Deriving of logical expression from
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal
More informationSimplification of Boolean Functions. Dept. of CSE, IEM, Kolkata
Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,
More informationCombinational Logic Fundamentals
Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic
More informationOptimizations and Tradeoffs. Combinational Logic Optimization
Optimizations and Tradeoffs Combinational Logic Optimization Optimization & Tradeoffs Up to this point, we haven t really considered how to optimize our designs. Optimization is the process of transforming
More informationMidterm1 Review. Jan 24 Armita
Midterm1 Review Jan 24 Armita Outline Boolean Algebra Axioms closure, Identity elements, complements, commutativity, distributivity theorems Associativity, Duality, De Morgan, Consensus theorem Shannon
More informationELC224C. Karnaugh Maps
KARNAUGH MAPS Function Simplification Algebraic Simplification Half Adder Introduction to K-maps How to use K-maps Converting to Minterms Form Prime Implicants and Essential Prime Implicants Example on
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationCHAPTER III BOOLEAN ALGEBRA
CHAPTER III- CHAPTER III CHAPTER III R.M. Dansereau; v.. CHAPTER III-2 BOOLEAN VALUES INTRODUCTION BOOLEAN VALUES Boolean algebra is a form of algebra that deals with single digit binary values and variables.
More informationfor Digital Systems Simplification of logic functions Tajana Simunic Rosing Sources: TSR, Katz, Boriello & Vahid
SE140: omponents and Design Techniques for Digital Systems Simplification of logic functions Tajana Simunic Rosing 1 What we covered thus far: Number representations Where we are now inary, Octal, Hex,
More informationCombinatorial Logic Design Principles
Combinatorial Logic Design Principles ECGR2181 Chapter 4 Notes Logic System Design I 4-1 Boolean algebra a.k.a. switching algebra deals with boolean values -- 0, 1 Positive-logic convention analog voltages
More informationIntroduction to Karnaugh Maps
Introduction to Karnaugh Maps Review So far, you (the students) have been introduced to truth tables, and how to derive a Boolean circuit from them. We will do an example. Consider the truth table for
More informationCMSC 313 Lecture 19 Combinational Logic Components Programmable Logic Arrays Karnaugh Maps
CMSC 33 Lecture 9 Combinational Logic Components Programmable Logic rrays Karnaugh Maps UMC, CMSC33, Richard Chang Last Time & efore Returned midterm exam Half adders & full adders Ripple
More informationPart 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...
Part 1: Digital Logic and Gates Analog vs Digital waveforms An analog signal assumes a continuous range of values: v(t) ANALOG A digital signal assumes discrete (isolated, separate) values Usually there
More informationDigital Circuit And Logic Design I. Lecture 4
Digital Circuit And Logic Design I Lecture 4 Outline Combinational Logic Design Principles (2) 1. Combinational-circuit minimization 2. Karnaugh maps 3. Quine-McCluskey procedure Panupong Sornkhom, 2005/2
More informationChapter 4 Optimized Implementation of Logic Functions
Chapter 4 Optimized Implementation of Logic Functions Logic Minimization Karnaugh Maps Systematic Approach for Logic Minimization Minimization of Incompletely Specified Functions Tabular Method for Minimization
More informationWorking with Combinational Logic. Design example: 2x2-bit multiplier
Working with ombinational Logic Simplification two-level simplification exploiting don t cares algorithm for simplification Logic realization two-level logic and canonical forms realized with NNs and NORs
More informationE&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev
E&CE 223 Digital Circuits & Systems Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean Algebra & Logic Gates Major topics Boolean algebra NAND & NOR gates Boolean
More informationStandard Expression Forms
ThisLecture will cover the following points: Canonical and Standard Forms MinTerms and MaxTerms Digital Logic Families 24 March 2010 Standard Expression Forms Two standard (canonical) expression forms
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 2 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering Boolean Algebra Boolean Algebra A Boolean algebra is defined with: A set of
More informationKarnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا
Karnaugh Maps مخطط آارنوف اعداد:محمد اسماعيل آلية علوم الحاسوب جامعة امدرمان الاهلية الاهداء الي آل من يسلك طريق العلم والمعرفة في هذا المجال Venn Diagrams Venn diagram to represent the space of minterms.
More informationMinimization techniques
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NSIK - 4 Minimization techniques By Prof. nand N. Gharu ssistant Professor Computer Department Combinational Logic Circuits Introduction Standard representation
More informationGate-Level Minimization
Gate-Level Minimization Dr. Bassem A. Abdullah Computer and Systems Department Lectures Prepared by Dr.Mona Safar, Edited and Lectured by Dr.Bassem A. Abdullah Outline 1. The Map Method 2. Four-variable
More informationE&CE 223 Digital Circuits & Systems. Lecture Transparencies (Boolean Algebra & Logic Gates) M. Sachdev. Section 2: Boolean Algebra & Logic Gates
Digital Circuits & Systems Lecture Transparencies (Boolean lgebra & Logic Gates) M. Sachdev 4 of 92 Section 2: Boolean lgebra & Logic Gates Major topics Boolean algebra NND & NOR gates Boolean algebra
More informationChapter 7 Logic Circuits
Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationKarnaugh Map & Boolean Expression Simplification
Karnaugh Map & Boolean Expression Simplification Mapping a Standard POS Expression For a Standard POS expression, a 0 is placed in the cell corresponding to the product term (maxterm) present in the expression.
More informationENG2410 Digital Design Combinational Logic Circuits
ENG240 Digital Design Combinational Logic Circuits Fall 207 S. Areibi School of Engineering University of Guelph Binary variables Binary Logic Can be 0 or (T or F, low or high) Variables named with single
More informationBinary logic consists of binary variables and logical operations. The variables are
1) Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets such as A, B, C, x, y, z, etc., with each variable having only two
More informationCHAPTER1: Digital Logic Circuits Combination Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits Combination Circuits 1 PRIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate.
More informationWeek-I. Combinational Logic & Circuits
Week-I Combinational Logic & Circuits Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other logic operators IC families and
More informationMC9211 Computer Organization
MC92 Computer Organization Unit : Digital Fundamentals Lesson2 : Boolean Algebra and Simplification (KSB) (MCA) (29-2/ODD) (29 - / A&B) Coverage Lesson2 Introduces the basic postulates of Boolean Algebra
More informationPrinciples of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents
B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction
More informationBoolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
More informationLogic Design Combinational Circuits. Digital Computer Design
Logic Design Combinational Circuits Digital Computer Design Topics Combinational Logic Karnaugh Maps Combinational uilding locks Timing 2 Logic Circuit logic circuit is composed of: Inputs Outputs Functional
More informationChapter 2 : Boolean Algebra and Logic Gates
Chapter 2 : Boolean Algebra and Logic Gates By Electrical Engineering Department College of Engineering King Saud University 1431-1432 2.1. Basic Definitions 2.2. Basic Theorems and Properties of Boolean
More informationKarnaugh Maps Objectives
Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between
More informationCHAPTER 12 Boolean Algebra
318 Chapter 12 Boolean Algebra CHAPTER 12 Boolean Algebra SECTION 12.1 Boolean Functions 2. a) Since x 1 = x, the only solution is x = 0. b) Since 0 + 0 = 0 and 1 + 1 = 1, the only solution is x = 0. c)
More informationSystems I: Computer Organization and Architecture
Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept
More information14:332:231 DIGITAL LOGIC DESIGN
:: DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall Lecture #: Combinational Circuit Synthesis II hat if we have input variables? V = V = of Example with variables
More informationL4: Karnaugh diagrams, two-, and multi-level minimization. Elena Dubrova KTH / ICT / ES
L4: Karnaugh diagrams, two-, and multi-level minimization Elena Dubrova KTH / ICT / ES dubrova@kth.se Combinatorial system a(t) not(a(t)) A combinatorial system has no memory - its output depends therefore
More informationKarnaugh Maps (K-Maps)
Karnaugh Maps (K-Maps) Boolean expressions can be minimized by combining terms P + P = P K-maps minimize equations graphically Put terms to combine close to one another B C C B B C BC BC BC BC BC BC BC
More informationSpiral 1 / Unit 3
-3. Spiral / Unit 3 Minterm and Maxterms Canonical Sums and Products 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Function Synthesis use Canonical Sums/Products -3.2 Outcomes I know the
More informationENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay
ENGG 23 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR Parity checking (for interest) Parity bit Parity checking Error detection, eg. Data can be Corrupted Even parity total number of s is even Odd parity
More informationMODULAR CIRCUITS CHAPTER 7
CHAPTER 7 MODULAR CIRCUITS A modular circuit is a digital circuit that performs a specific function or has certain usage. The modular circuits to be introduced in this chapter are decoders, encoders, multiplexers,
More informationII. COMBINATIONAL LOGIC DESIGN. - algebra defined on a set of 2 elements, {0, 1}, with binary operators multiply (AND), add (OR), and invert (NOT):
ENGI 386 Digital Logic II. COMBINATIONAL LOGIC DESIGN Combinational Logic output of digital system is only dependent on current inputs (i.e., no memory) (a) Boolean Algebra - developed by George Boole
More informationLogic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 06 October 24, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationMidterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes
Page 1 of 10 School of Computer Science 60-265-01 Computer Architecture and Digital Design Winter 2009 Semester Midterm Examination # 1 Wednesday, February 25, 2009 Student Name: First Name Family Name
More informationChap 2. Combinational Logic Circuits
Overview 2 Chap 2. Combinational Logic Circuits Spring 24 Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard Forms Part 2 Circuit Optimization Two-Level Optimization
More informationLogical Design of Digital Systems
Lecture 4 Table of Content 1. Combinational circuit design 2. Elementary combinatorial circuits for data transmission 3. Memory structures 4. Programmable logic devices 5. Algorithmic minimization approaches
More informationFunctions. Computers take inputs and produce outputs, just like functions in math! Mathematical functions can be expressed in two ways:
Boolean Algebra (1) Functions Computers take inputs and produce outputs, just like functions in math! Mathematical functions can be expressed in two ways: An expression is finite but not unique f(x,y)
More informationUNIT 4 MINTERM AND MAXTERM EXPANSIONS
UNIT 4 MINTERM AND MAXTERM EXPANSIONS Spring 2 Minterm and Maxterm Expansions 2 Contents Conversion of English sentences to Boolean equations Combinational logic design using a truth table Minterm and
More informationSpiral 2-1. Datapath Components: Counters Adders Design Example: Crosswalk Controller
2-. piral 2- Datapath Components: Counters s Design Example: Crosswalk Controller 2-.2 piral Content Mapping piral Theory Combinational Design equential Design ystem Level Design Implementation and Tools
More informationDIGITAL ELECTRONICS & it0203 Semester 3
DIGITAL ELECTRONICS & it0203 Semester 3 P.Rajasekar & C.M.T.Karthigeyan Asst.Professor SRM University, Kattankulathur School of Computing, Department of IT 8/22/2011 1 Disclaimer The contents of the slides
More informationLecture 7: Karnaugh Map, Don t Cares
EE210: Switching Systems Lecture 7: Karnaugh Map, Don t Cares Prof. YingLi Tian Feb. 28, 2019 Department of Electrical Engineering The City College of New York The City University of New York (CUNY) 1
More informationLecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions
EE210: Switching Systems Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions Prof. YingLi Tian Feb. 15, 2018 Department of Electrical Engineering The City College of New York The
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active
More informationEECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive
EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive March 30, 2010 John Wawrzynek Spring 2010 EECS150 - Lec19-cl1 Page 1 Boolean Algebra I (Representations of Combinational
More informationWEEK 3.1 MORE ON KARNAUGH MAPS
WEEK 3. MORE ON KARNAUGH MAPS Don t Cares Sometimes, we might have inputs and it doesn t matter what the output is; i.e., we don t care what the output is. These situations are called don t cares. Rather
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101>
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 2- Chapter 2 :: Combinational Logic Design Digital Design and Computer Architecture David Money Harris and
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps
Introduction to Digital Logic Missouri S&T University CPE 2210 Karnaugh Maps Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology
More informationBoolean Algebra and Logic Simplification
S302 Digital Logic Design Boolean Algebra and Logic Simplification Boolean Analysis of Logic ircuits, evaluating of Boolean expressions, representing the operation of Logic circuits and Boolean expressions
More informationThe Design Procedure. Output Equation Determination - Derive output equations from the state table
The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types
More informationSample Marking Scheme
Page 1 of 10 School of Computer Science 60-265-01 Computer Architecture and Digital Design Fall 2008 Midterm Examination # 1 B Wednesday, November 5, 2008 Sample Marking Scheme Duration of examination:
More informationSlide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 3 for ENEL 353 Fall 2016 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2016 SN s ENEL 353 Fall 2016 Slide Set 3 slide
More informationZ = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table
Lesson Objectives In this lesson, you will learn about What are combinational circuits Design procedure of combinational circuits Examples of combinational circuit design Combinational Circuits Logic circuit
More information( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function
Question Paper Digital Electronics (EE-204-F) MDU Examination May 2015 1. (a) represent (32)10 in (i) BCD 8421 code (ii) Excess-3 code (iii) ASCII code (b) Design half adder using only NAND gates. ( c)
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2017 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables,,... represent classes
More informationCMSC 313 Lecture 19 Homework 4 Questions Combinational Logic Components Programmable Logic Arrays Introduction to Circuit Simplification
CMSC 33 Lecture 9 Homework 4 Questions Combinational Logic Components Programmable Logic rrays Introduction to Circuit Simplification UMC, CMSC33, Richard Chang CMSC 33, Computer Organization
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More information7.1. Unit 7. Minterm and Canonical Sums 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Simplification using Boolean Algebra
7.1 Unit 7 Minterm and Canonical Sums 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Simplification using Boolean Algebra CHECKERS / DECODERS 7.2 7.3 Gates Gates can have more than 2 inputs
More informationFundamentals of Boolean Algebra
UNIT-II 1 Fundamentals of Boolean Algebra Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators and
More informationChapter 2 (Lect 2) Canonical and Standard Forms. Standard Form. Other Logic Operators Logic Gates. Sum of Minterms Product of Maxterms
Chapter 2 (Lect 2) Canonical and Standard Forms Sum of Minterms Product of Maxterms Standard Form Sum of products Product of sums Other Logic Operators Logic Gates Basic and Multiple Inputs Positive and
More informationTotal Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18
University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total
More informationCHAPTER 7. Solutions for Exercises
CHAPTER 7 Solutions for Exercises E7.1 (a) For the whole part we have: Quotient Remainders 23/2 11 1 11/2 5 1 5/2 2 1 2/2 1 0 1/2 0 1 Reading the remainders in reverse order we obtain: 23 10 = 10111 2
More informationEE 209 Spiral 1 Exam Solutions Name:
EE 29 Spiral Exam Solutions Name:.) Answer the following questions as True or False a.) A 4-to- multiplexer requires at least 4 select lines: true / false b.) An 8-to- mux and no other logic can be used
More informationCS/EE 181a 2010/11 Lecture 4
CS/EE 181a 21/11 Lecture 4 General topic of today s lecture: Logic Optimization Karnaugh maps. Quine-McCluskey tabulation method (not in detail). Non series-parallel networks (some care is required). Reference
More informationCombinational Logic Design Principles
Combinational Logic Design Principles Switching algebra Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Switching algebra Axioms of switching algebra Theorems
More informationCHAPTER 7. Exercises 17/ / /2 2 0
CHAPTER 7 Exercises E7. (a) For the whole part, we have: Quotient Remainders 23/2 /2 5 5/2 2 2/2 0 /2 0 Reading the remainders in reverse order, we obtain: 23 0 = 0 2 For the fractional part we have 2
More informationSignals and Systems Digital Logic System
Signals and Systems Digital Logic System Prof. Wonhee Kim Chapter 2 Design Process for Combinational Systems Step 1: Represent each of the inputs and outputs in binary Step 1.5: If necessary, break the
More information15.1 Elimination of Redundant States
15.1 Elimination of Redundant States In Ch. 14 we tried not to have unnecessary states What if we have extra states in the state graph/table? Complete the table then eliminate the redundant states Chapter
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Boolean Logic Stephen A. Edwards Columbia University Summer 2015 Boolean Logic George Boole 1815 1864 Boole s Intuition Behind Boolean Logic Variables X,,... represent
More informationLecture 2 Review on Digital Logic (Part 1)
Lecture 2 Review on Digital Logic (Part 1) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Grading Engagement 5% Review Quiz 10% Homework 10% Labs 40%
More information