Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

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1 Parity Checker Example A string of bits has even parity if the number of 1 s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even and outputs a 1 if odd: EECS150 - Digital Design Lecture 9 - Finite State Machines 1 February 15, 25 John Wawrzynek Can you guess a circuit that performs this function? Spring 25 EECS150 - Lec09-FSM1 Page 1 Spring 25 EECS150 - Lec09-FSM1 Page 2 bit stream IN CLK Parity Checker OUT State Transition Diagram circuit is in one of two states. transition on each cycle with each new input, over exactly one arc (edge). Output depends on which state the circuit is in. 0 if even parity 1 if odd parity example: even even odd even odd odd even time Spring 25 EECS150 - Lec09-FSM1 Page 3 State Transition Table: present next state OUT IN state EVEN 0 0 EVEN EVEN 0 1 ODD ODD 1 0 ODD ODD 1 1 EVEN Invent a code to represent states: Let 0 = EVEN state, 1 = ODD state present state (ps) OUT IN next state (ns) Derive logic equations from table (how?): OUT = PS NS = PS xor IN Spring 25 EECS150 - Lec09-FSM1 Page 4 1

2 Logic equations from table: OUT = PS NS = PS xor IN Circuit Diagram: XOR gate for ns calculation DFF to hold present state no logic needed for output ps ns Review of Design Steps: 1. Specify circuit function (English) 2. Draw state transition diagram 3. Write down symbolic state transition table 4. Write down encoded state transition table 5. Derive logic equations 6. Derive circuit diagram FFs for state CL for NS and OUT Spring 25 EECS150 - Lec09-FSM1 Page 5 Spring 25 EECS150 - Lec09-FSM1 Page 6 Finite State Machines (FSMs) FSM Implementation FSM circuits are a type of sequential circuit: output depends on present and past inputs fect of past inputs is represented by the current state Behavior is represented by State Transition Diagram: traverse one edge per clock cycle. FFs form state register number of states 2 number of flip-flops CL (combinational logic) calculates next state and output Remember: The FSM follows exactly one edge per cycle. Spring 25 EECS150 - Lec09-FSM1 Page 7 Spring 25 EECS150 - Lec09-FSM1 Page 8 2

3 Combination Lock Example Announcements Exam next Tuesday (2/22) in class: Special review session Monday (2/21) 5-7pm, 125 Cory Check webpage for information on exam room assignment. Exam coverage HW / Quiz Used to allow entry to a locked room: 2-bit serial combination. Example 01,: 1. Set switches to 01, press ENTER 2. Set switches to, press ENTER 3. OPEN is asserted (OPEN=1). If wrong code, ERROR is asserted (after second combo word entry). Press Reset at anytime to try again. Spring 25 EECS150 - Lec09-FSM1 Page 9 Spring 25 EECS150 - Lec09-FSM1 Page Combinational Lock STD Symbolic State Transition Table RESET ENTER COM1 COM2 Preset State Next State OPEN ERROR 0 0 * * START START * START BAD * START OK * * OK1 OK * 0 OK1 BAD * 1 OK1 OK * * * OK2 OK * * BAD1 BAD * * BAD1 BAD * * * BAD2 BAD * * * * START 0 0 Assume the ENTER button when pressed generates a pulse for only one clock cycle. Spring 25 EECS150 - Lec09-FSM1 Page Decoder logic for checking combination (01,): Spring 25 EECS150 - Lec09-FSM1 Page 12 3

4 ENTER COM1 COM2 PS2 PS1 PS0 NS2 NS1 NS Encoded ST Table Assign states: START=0, OK1=1, OK2=0 BAD1=0, BAD2=1 Omit reset. Assume that primitive flip-flops has reset input. Rows not shown have don t cares in output. Correspond to invalid PS values. ab = ab = ab = NS2 NS1 NS ab = ab = ab = 01 What are the output functions for OPEN and ERROR? Spring 25 EECS150 - Lec09-FSM1 Page ab = ab = ab = General FSM form: FSM Implementation Notes All examples so far generate output based only on the present state: Commonly name Moore Machine (If output functions include both present state and input then called a Mealy Machine) Spring 25 EECS150 - Lec09-FSM1 Page 14 State Encoding One-hot encoding of states. One FF per state. State Encoding In general: # of possible FSM state = 2 # of FFs Example: state1 = 01, state2 =, state3 =, state4 = However, often more than log 2 (# of states) FFs are used, to simplify logic at the cost of more FFs. Extreme example is one-hot state encoding. Why one-hot encoding? Simple design procedure. Circuit matches state transition diagram (example next page). Often can lead to simpler and faster next state and output logic. Why not do this? Can be costly in terms of FFs for FSMs with large number of states. FPGAs are FF rich, therore one-hot state machine encoding is often a good approach. Spring 25 EECS150 - Lec09-FSM1 Page 15 Spring 25 EECS150 - Lec09-FSM1 Page 16 4

5 Even Parity Checker Circuit: One-hot encoded FSM One-hot encoded combination lock Circuit generated through direct inspection of the STD. In General: FFs must be initialized for correct operation (only one 1) Spring 25 EECS150 - Lec09-FSM1 Page 17 Spring 25 EECS150 - Lec09-FSM1 Page 18 General FSM Design Process with Verilog Implementation Design Steps: 1. Specify circuit function (English) 2. Draw state transition diagram 3. Write down symbolic state transition table 4. Assign encodings (bit patterns) to symbolic states 5. Code as Verilog behavioral description Use parameters to represent encoded states. Use separate always blocks for register assignment and CL logic block. Use case for CL block. Within each case section assign all outputs and next state value based on inputs. Note: For Moore style machine make outputs dependent only on state not dependent on inputs. Spring 25 EECS150 - Lec09-FSM1 Page 19 Moore FSMs in Verilog module FSM1(clk, rst, in1, in2,, out1, out2, ); input clk, rst, in1, in2, ; output out1, out2, ; parameter dault=2'bxx; parameter s1=2'b; parameter s2=2'b01; reg out1, out2, ; reg [1:0] ps, ns; If you deviate from this template, do so only with care. For example, for some FSMs you might simplify the code by factoring out common output assignments from the cases: clk) if (rst) ps <= s0; else ps <= ns; in1 in2 ) case (ps) s1 : begin out1 = ; out2 = ; if (in1 && in2 ) ns = s2; else ns = s2; end s2 : begin end dault: begin out1 = 1 bx; ns = dault; end in1 in2 ) begin out1 = 1 b0; case (ps) sn: begin out1 = 1 b1; Similar example is unlock and error outputs in combo lock. Spring 25 EECS150 - Lec09-FSM1 Page 20 5

EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?