Chapter 14 Sequential logic, Latches and Flip-Flops

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1 Chapter 14 Sequential logic, Latches and Flip-Flops Flops

2 Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

3 JK Flip-Flop ve edge triggered Output Q and Q Clock -ve Edge triggered circuit J K clear R S Preset J Clock K PR SR Latch Q Q Q Q CLR Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

4 JK Flip-Flop + ve edge triggered Output Q and Q J clear R Q Clock +ve Edge triggered circuit K S Preset J Clock K PR JK FF Q Q Q CLR Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

5 JK Flip Flop 1. It has edge trigger clock input so that the output state changes only on a clock edge 2. The NANDs S input of level clocked SR latch labeled as J input and R input as K input. 3. Second input of both NANDs is common 4. Clock input has an additional circuitry to make the J and K inputs transparent at an instance corresponding to an edge at the clock input Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

6 JK Flip Flop Three input cross coupled NANDs Third input of lower NAND connects the Q output Third input of upper NAND connects the Q output. There is no unstable condition in J-K FF state table Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

7 Clock Symbolic representation A bubble followed by a triangle at a clock input represents negative edge triggered clock and output will correspond to the J and K inputs at that -ve edge instance only A triangle at a clock input represents positive edge triggered clock and output will correspond to the J and K inputs at that +ve edge instance only Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

8 Clock edge Symbolic representation Down side arrow corresponds -ve edge instance (0 to 1 transition only) Up side arrow corresponds +ve edge instance (1 to 0 transition only) Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

9 J = 0 and K = 0 No change state Output Q remains same as before even after the clock edge when J = 0 and K =0 Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

10 J = 0, K = 0 Inputs Output State Clock Q n J Q n K Q n+1 Q n+1 X Q n Q n No change X Q n Q n No change X means either 1 or 0 or +ve edge or -ve edge input, Q n+1 means next state after n th clock input Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

11 J = 1 and K = 0 (Q set to 1) Output Q sets to 1 and Q n becomes = 0 after the clock edge when J = 1 and K =0 Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

12 J = 1, K = 0 -ve edge triggered JK Inputs Output State Clock Q n J Q n K Q n+1 Q n Q n Q n No change Q n Q n No change X 1 X 0 Q n Q n No change X 1 X Sets to 1 X means either 1 or 0 input, Q n+1 means next state after n th clock input Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

13 J = 0 and K = 1 (Q reset to 1) Output Q resets to 0 and Q n becomes = 1 after the clock edge when J = 0 and K = 1 Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

14 J = 0, K = 1 -ve edge triggered JK Inputs Output State Clock Q n J Q n K Q n+1 Q n Q n Q n No change Q n Q n No change X 0 X 1 Q n Q n No change X 0 X Resets to 0 X means either 1 or 0 input, Q n+1 means next state after n th clock input Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

15 J = 1 and K = 1 (Q Toggles) Output Q resets to 0 and Q n becomes = 1 in case Q was 1 earlier Q n was 0 and after the clock edge when J = 1 and K = 1 Output Q sets to 1 and Q n becomes = 0 in case Q was 0 earlier Q n was 1 and after the clock edge when J = 1 and K = 1 Q toggles (complements the n th state after the n th clock transition) Q n+1 Q n Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

16 J = 1, K = 1 -ve edge triggered JK Inputs Output State Clock Q n J Q n K Q n+1 Q n Q n Q n No change Q n Q n No change X 1 X 1 Q n Q n No change 1 1 Q n Q n Toggles X means either 1 or 0 input, Q n+1 means next state after n th clock input Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

17 Use of Clear and Preset Inputs JK FF may have connections to the two inputs of cross coupled NANDs. It can be used as R (clear) and S (preset), to preset Q to 1 or to reset Q to 0. Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

18 Summary

19 We learnt that in JK edge triggered FF: When J = 1 and K =1, the output of flip-flop toggles (changes to opposite state) on clock edge. When J = 0 and K =0, the output of flip-flop does not change on clock edge. When J = 0 and K =1, the output Q resets to 0 after clock edge. When J = 1 and K =0, the output Q sets to 1 after clock edge Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

20 End of Lesson 4 on JK Flip Flop

21 THANK YOU Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education,

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