IE1204 Digital Design. L10: State Machines (Part 2) Masoumeh (Azin) Ebrahimi Elena Dubrova

Transcription

1 IE1204 Digital Design L10: State Machines (Part 2) Masoumeh (Azin) Ebrahimi Elena Dubrova KTH / ICT / ES

2 This lecture BV pp , IE1204 Digital Design, Autumn2015 2

3 Sequential System a (t) f (a (t)) A sequential system has a built-in memory - the output depends therefore BOTH on the current and previous value(s) of the input signal Lecture 8 - Lecture 13 IE1204 Digital Design, Autumn2015 3

4 Basic method for the design of state machines 1. Analyze the specification of the circuit 2. Create state diagrams 3. Set up the state table 4. Minimize state table (this lecture) 5. Assign codes for states 6. Choose the type of flip-flops 7. Realize the circuit using Karnaugh maps IE1204 Digital Design, Autumn2015 4

5 Moore Machine State Input signals NEXT STATE DECODER STATE REGISTER OUTPUT DECODER Output signals Clk In a Moore-type machine output signals depend only on the current state IE1204 Digital Design, Autumn2015 5

6 Input vs. output - Moore State changed here (at clock edge) The input sequence In 1 In 2 O 1 O 2 The output sequence Output visible after the state has changed IE1204 Digital Design, Autumn2015 6

7 Mealy-type machine State Input signals NEXT STATE DECODER STATE REGISTER OUTPUT DECODER Output signals Clk In a Mealy machine, output signals depend on both the current state and inputs IE1204 Digital Design, Autumn2015 7

8 Input vs. output - Mealy State changed here (at clock edge) The input sequence In 1 In 2 O 1 O 2 The output sequence Output appears directly after the input has changed IE1204 Digital Design, Autumn2015 8

9 Unused state Sometimes you get more states when you need when selecting a code Unused states must be taken care of so that the state machine does not hangs at the start-up (if reset is not used) Reset State w= 0 State identifier A z= 0 w= 1 w= 0 C z= 1 w= 1 B z= 0 w= 0 w= 1 The state transition Value of output signal Next state Present state w =0 w =1 Output z y 2 y 1 Y 2 Y 1 Y 2 Y 1 A B C Unused State 11 dd dd d IE1204 Digital Design, Autumn2015 9

10 Example: (0,0,1) sequence generator 3 states => 2 flip-flops. One unused state. Dangerous transition (Machine hangs) S3 - S1 0 S0 0 If the machine falls in this position, we want it to find move to another state as soon as possible S2 1 IE1204 Digital Design, Autumn

11 Next-state function S0 S1 S2 Current Output Next state state signal y 2 y 1 z Y 2 Y (not 11) S3 - S1 0 S0 0 S2 1 IE1204 Digital Design, Autumn

12 Karnaugh maps S0 S1 S2 Current state Output signal Next state y2y1 z Y2 Y (not 11) y 1 y y 1 y 1 y y Y 2 = y 1 Y 1 = y 2 y 1 z = y 2 IE1204 Digital Design, Autumn

13 State table after Karnaugh minimization S0 S1 S2 Current state Output signal y 2 y 1 z Y 2 Y Next state The unused state goes to S2 S3 1 S1 0 S0 0 (0,0,1) sequence generator S2 1 IE1204 Digital Design, Autumn

14 Logic circuit for the sequence The implementation uses D flip-flops z y 2 Y 2 Y 1 y 1 y 2 y 1 Clk Y 2 = y 1 Y 1 = y 2 y 1 z = y 2 IE1204 Digital Design, Autumn

15 Logic circuit in the structure of Moore machine Y 1 = y 2 y 1 Y 2 = y 1 Combinational circuit Flip-flops Combinational circuit Inputsignals Outputsignals z = y 2 Clk Y 1 y 1??? Y 2 y 2 z Clk IE1204 Digital Design, Autumn

16 Logic circuit for the sequence z Clk y 2 Y 2 Y 1 y 2 y 1 y 1 Combinational circuit Clk Flip-flops Combinational circuit Inputsignals Outputsignals Y 1 = y 2 y 1 Y1 y1 Y 2 = y 1 z = y 2 Y 2 y2 z Clk IE1204 Digital Design, Autumn

17 State minimization When designing complex state machines, it often happens that there are equivalent states that can be grouped together to obtain a more efficient implementation Two states S 1 are S 2 are called equivalent if and only if, for every possible input sequence, the same output will be produced regardless of whether S 1 or S 2 is the initial state IE1204 Digital Design, Autumn

18 State minimization The following example illustrates one minimization method which is can be used for state minimization This method identifies states which are not equivalent (this is often easier) First, we introduce some terminology IE1204 Digital Design, Autumn

19 0- and 1-sucessors If input is applied to a state machine in state S 1 and the result is that the machine moves to state S 2, we say that S 2 is a 0- successor of S 1 S1 If input is applied to a state machine in state S 1 and the result is that the machine moves to state S 3, we say that S 3 is a 1- successor of S 1 We will refer to successors as k-sucessors, where k can be 0 or 1 w=0 w=1 S2 S3 IE1204 Digital Design, Autumn

20 State minimization Basic idea Two states are not equivalent if they have different output values A z = 1 B z = 0 IE1204 Digital Design, Autumn

21 State minimization Basic idea Two states are not equivalent if at least one of their k-sucessors are not equivalent A z = 1 B z = 1 C z = 1 D z = 0 IE1204 Digital Design, Autumn

22 A z = 1 Example State minimization B z = 1 D z = 1 C z = 0 E z = 0 F z = 0 G z = 0 (Moore Machine) 7- states uses 3 flip-flops (2 3 = 8) IE1204 Digital Design, Autumn

23 State table A z = 1 C z = 0 B z = 1 F z = 0 D z = 1 G z = 0 Present Next state Output state w =0 w =1 z A B C 1 E z = 0 IE1204 Digital Design, Autumn

24 State table A z = 1 B z = 1 D z = 1 Present Next state Output state w =0 w =1 z C z = 0 E z = 0 F z = 0 G z = 0 A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 IE1204 Digital Design, Autumn

25 Partition The minimization procedure first considers the state of a machine as a set and then breaks this set into partitions that are not equivalent. A partition consists of one or more blocks each block contains states that may be equivalent different blocks contain states that are definitely not equivalent IE1204 Digital Design, Autumn

26 Example state minimization Start Just one block containing all states P 1 = (ABCDEFG) IE1204 Digital Design, Autumn

27 Example state minimization P 1 = (ABCDEFG) Stage 1: Which states have different outputs? ABD has output z = 1 CEFG have output z = 0 => P 2 = (ABD) (CEFG) A z = 1 B z = 0 States A, B, D can therefore never be equivalent to any of the conditions C, E, F, G so they form different groups IE1204 Digital Design, Autumn

28 w=0 Stage 2 ABD w=1 CEFG Example state minimization Which states have different k-successors? Block ABD 0-successor: A B, B D, D B (all transitions go to the same block) 1-successor: A C, B F, D G (all transitions go to the same block) Block CEFG P 2 = (ABD) (CEFG) 0-successor: C F, E F, F E, G F (all transitions go to the same block) 1-successor: C E, E C, F D, G G (F D goes to another block) => P 3 = (ABD) (CEG) (F) A z = 1 C z = 1 IE1204 Digital Design, Autumn B z = 1 D z = 0

29 w=0 Stage 2 ABD w=1 CEFG Example state minimization Which states have different k-successors? Block ABD 0-successor: A B, B D, D B (all transitions go to the same block) 1-successor: A C, B F, D G (all transitions go to the same block) Block CEFG P 2 = (ABD) (CEFG) 0-successor: C F, E F, F E, G F (all transitions go to the same block) 1-successor: C E, E C, F D, G G (F D goes to another block) => P 3 = (ABD) (CEG) (F) A z = 1 C z = 1 IE1204 Digital Design, Autumn B z = 1 D z = 0

30 w=0 w=1 w=0 ABD w=1 CEG F Step 3 w=0 Example state minimization P3= (ABD) (CEG) (F) What states have different k-successors? w=1 Block ABD 0-successor: A B, B D, D B (all transitions go to the same block) 1-successor: A C, B F, D G (B F goes to another block) => P4= (AD) (B) (CEG) (F) Block (CEG) 0-successor: C F, E F, G F (all transitions go to the same block) 1-successor: C E, E C, G G (all transitions go to the same block) => P4= (AD) (B) (CEG) (F) IE1204 Digital Design, Autumn

31 w=1 Example state minimization P4= (AD) (B) (CEG) (F) Next partition P 5 becomes the same as P 4. Thus the procedure is finished. AD w=0 w=0 B CEG States in each block are equivalent w=1 if they were not, their k-successors would have to be in different blocks A becomes the representive of AD and C represents CEG. w=1 w=0 F w=0 w=1 P 4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F) IE1204 Digital Design, Autumn

32 Final state table Present Next state Output state w =0 w =1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Present Next State Output state w= 0 w= 1 z A B C 1 B A F 1 C F C 0 F C A 0 Final State Table P 4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F) IE1204 Digital Design, Autumn

33 Final state table Present Next state Output state w =0 w =1 z A B C 1 B D F 1 C F E 0 D B G 1 E F C 0 F E D 0 G F G 0 Present Next State Output state w= 0 w= 1 z A B C 1 B A F 1 C F C 0 F C A 0 Final State Table P 4 = (AD)(B)(CEG)(F) = (A)(B)(C)(F) IE1204 Digital Design, Autumn

34 Final state diagram Present Next State state w=0 w= 1 Output z A B C 1 B A F 1 C F C 0 F C A 0 A z = 1 C z = 0 B z = 1 F z = 0 4 states needs 2 flip-flops (2 2 = 4). IE1204 Digital Design, Autumn

35 Comparison A z = 1 B z = 1 D z = 1 A z = 1 B z = 1 C z = 0 E z = 0 F z = 0 G z = 0 C z = 0 Only 2 flip-flops are needed to implement 4 states in the minimized state table 3 flip-flops are needed to implement 7 states in the original state table F z = 0 IE1204 Digital Design, Autumn

36 Some thought! Fewer state does not necessarily lead to a simpler design! The advantage of state minimization is instead that it makes it easier to create the initial state diagram, when you do not have to get it to be minimal from the beginning! IE1204 Digital Design, Autumn

37 Analysis of synchronous sequential circuits Given an implementation of a synchronous circuit, we can produce its function by making the synthesis steps in a reverse order! 1. Get expressions for next state decoder output decoder 2. Get the state table 3. Draw the state diagram IE1204 Digital Design, Autumn

38 Example: Analysis of a synchronous sequential circuit Y 1 D Q y 1 z w Clock Resetn Y 2 D Q Q Q y 2 It is difficult to figure out directly from the schematic how a sequential circuit behaves! IE1204 Digital Design, Autumn

39 Example: Moore-machine! IE1204 Digital Design, Autumn

40 Example: Analysis of a synchronous sequential circuit 1. Get expressions for next state decoder output decoder w y 1 w y 2 w y 1 wy 2 wy 1 wy1 Y 1 Y 2 Y Y 1 2 = = wy wy wy wy 2 2 y 1 y 2 z = y 1 y 2 z IE1204 Digital Design, Autumn

41 Example: Analysis of a synchronous sequential circuit 2. Get the state table Next State Present state w= 0 w= 1 Output y 2 y 1 z Y 2 Y 1 Y 2 Y A: 00 B: 01 C: 10 D: 11 Present Next state Output state w= 0 w= 1 z A A B 0 B A C 0 C A D 0 D A D 1 Y 2 + wy z = y 1 y = wy1 2 Y 1= wy1+ wy2 2 IE1204 Digital Design, Autumn

42 Example: Analysis of a synchronous sequential circuit 3. Draw state diagram Left as exercise for students... (but check the state table to make sure it is a bit sequence detector for three subsequent 1s) Present Next state Output state w= 0 w= 1 z A A B 0 B A C 0 C A D 0 D A D 1 A z = 0 C z = 0 w =1 B z = 0 D z = 1 IE1204 Digital Design, Autumn

43 State diagram Present Next state Output state w= 0 w= 1 z A A B 0 B A C 0 C A D 0 D A D 1 Sometimes you may need to change the order of the states to get a clearer chart. A z = 0 C z = 0 w =1 w =1 w =1 B z = 0 D z = 1 w =1 IE1204 Digital Design, Autumn

44 State diagram Present Next state Output state w= 0 w= 1 z A A B 0 B A C 0 C A D 0 D A D 1 C and D have changed places resulting in no intersecting state arrows. w =1 A z = 0 D z = 1 w =1 w =1 B z = 0 C z = 0 IE1204 Digital Design, Autumn

45 ASM Charts State transition diagrams are convenient for describing the behavior of small state machines only To describe larger state machines, another type of diagrams, called Algorithmic State Machine (ASM) charts are often used An ASM is a flow diagram consisting of three types of elements: state box, decision box and conditional output box 0 0 A B C Reset w w z w IE1204 Digital Design, Autumn

46 ASM Charts State Name Output signals or actions (Moore type) 0 (False) Condition 1 (True) expression (B) Decision box (A) State Box Conditional outputs or actions (Mealy type) (C) Conditional output box IE1204 Digital Design, Autumn

47 ASM Charts State Box Represents a state in a FSM Output values for state are given here (Moore outputs) Decision Box Depending on the values of the input signals, it determines a transition to the next state Conditional outputs Box Specifies the values of the outputs at a state transition (Mealy outputs) IE1204 Digital Design, Autumn

48 ASM chart for 11 sequence detector (Moore) Reset Reset A A z= 0 B z= 0 0 B w 1 0 w 1 C z= 1 C z 0 1 w z = 1 only in the state C IE1204 Digital Design, Autumn

49 ASM chart for 11 sequence detector (Mealy) Reset Reset z = 0 A z = 0 A B z = 1 0 w 1 z = 0 B z 0 1 w z = 1 only when the state transition B-to-B with takes place IE1204 Digital Design, Autumn

50 Formal model for sequential circuits To treat state machines in a formal way, we need a formal model The following model can describe both Moore and Mealy machines IE1204 Digital Design, Autumn

51 Formal model for sequential circuits w 1 z 1 Inputs w n Combinational Circuit z m Outputs y k Y k Current-state variables Next-state variables y 1 Y 1 IE1204 Digital Design, Autumn

52 Formal model for sequential circuits A synchronous sequential circuit can be formally defined as M = ( W, Z, S, j, l) W, Z, and S are finite, nonempty sets of inputs, outputs and states, respectively φ is the state transition function, such as S(t+1) = φ[w(t), S(t)] λ is the output function, such as λ(t) = λ(s(t)) for the Moore model and λ(t) = λ(w(t), S(t)) for the Mealy model IE1204 Digital Design, Autumn

53 W Z S y Y inputs outputs states present-state Formal model for sequential circuits = = { w1, w2,..., wm} { z1, z2,..., zm} { S1, S2,..., Sm} -variables = { y1, y2,..., ym} = { Y, Y,..., Y } = next-state-variables 1 2 m M = ( W, Z, S, j, l) S( t l l Moore Mealy + Dt) = Y 1... Y m ( t) = l( S( t)) ( t) = l( W ( t), S( t)) = j( W ( t), S( t)) IE1204 Digital Design, Autumn

54 Bottle dispenser Bottle dispenser consists of several parts COIN RECEIVER DROP BOTTLE COIN RETURN Machine accepts only the following coins: 1 Euro, 50 Cent, 10 Cent The vending machine only returns 10 Cent coins IE1204 Digital Design, Autumn

55 Signal Properties DROP_READY is active for one clock cycle after the bottle has been ejected CHANGER_READY is active for one clock cycle after a 10 Cent coin is ejected Because of the mechanical properties, the following signals are active and inactive for several clock cycles: (active for several clock cycles after the coin drop) DROP_READY (active for several clock periods after bottle drop) CHANGER_READY (inactive for several clock periods after coin return) IE1204 Digital Design, Autumn

56 Flow diagram of control system No Total <1 Reset Coin registered? Yes Total? Coin 10 Cent, 50 Cent, 1 Euro Coin return 10 Cent Bottle Price 1 Euro Total = 1 Total> 1 Eject bottle Reset sum Return 10 Cent Decrease sum IE1204 Digital Design, Autumn

57 State diagram (Moore) (a) (b) (a) (b) (c) Wait for coin Register coin Coin is registered (3 cases) LT_I_EURO (c) (d) (e) Drop bottle Reset sum EQ_I_EURO GT_I_EURO (f) Return 10 Cent DROP READY DROP (d) (f) CHANGER READY RETURN_10_CENT (g) Decrease sum with 10 Cent DROP READY (e) CLR_ACC (g) DEC_ACC CHANGER_READY Upon entry into the state, signal becomes active When exiting the state, signal becomes inactive IE1204 Digital Design, Autumn

58 State diagram (a) (b) State assignment with no claim for optimality (Ad hoc) (a) next to (b) DROP READY LT_I_EURO EQ_I_EURO DROP (d) (c) GT_I_EURO (f) CHANGER READY RETURN_10_CENT (b) next to (c) (d) next to (e) (f) next to (g) For all these cases, only one variable changes AB DROP READY CHANGER_READY (e) (g) C 0 a - d f 1 b c e g CLR_ACC DEC_ACC ( - = don t care) IE1204 Digital Design, Autumn

59 State diagram DROP READY LT_I_EURO EQ_I_EURO DROP DROP READY (d) 110 (e) 111 CLR_ACC (a) 000 (b) 001 (c) 011 GT_I_EURO (f) 100 (g) 101 DEC_ACC CHANGER READY RETURN_10_CENT CHANGER_READY The state diagram contains all information required to generate an implementation Assumption: D flip-flops are used as state register 7 states: 3 flip-flops are needed The state variable order is ABC, i.e. state (c) is A = 0, B = 1,C = 1 IE1204 Digital Design, Autumn

60 Unused state?! DROP READY LT_I_EURO EQ_I_EURO DROP DROP READY (d) 110 (e) 111 CLR_ACC (a) 000 (b) 001 (c) 011 GT_I_EURO (f) 100 (g) 101 DEC_ACC (h) 010 CHANGER READY RETURN_10_CENT CHANGER_READY If fall into the unused state (h) we are stuck!! Possible ways out: going to (c) and continue. going to (d) and offering soft drinks!! going to (e) and resetting any previous payment. Which option do you prefer for your design?! Which option leads to a simpler design? IE1204 Digital Design, Autumn

61 Construction of next-state and output decoders (Moore machine) Combinational circuit Flip-flops Combinational circuit Inputsignals Outputsignals Clk LT_I_EURO EQ_I_EURO GT_I_EURO DROP_READY CHANGER_READY A B Next State Decoder D A D B D C D D D B C A Output Decoder DROP RETURN_I0_CENT CLR_ACC DEC_ACC C Clk At next step, we develop the logic for the next state (D A, D B, D C ) and outputs IE1204 Digital Design, Autumn

62 Construction of next-state and output decoders Input-signals Next state decoder (Combination al circuit) Clk Flip-flops Output decoder (Combination al circuit) Output-signals?? LT_I_EURO EQ_I_EURO GT_I_EURO DROP_READY CHANGER_READY A B Next State Decoder D A D B D C D D D B C A Output Decoder DROP RETURN_I0_CENT CLR_ACC DEC_ACC C Clk At next step, we develop the logic for the next state (D A, D B, D C ) and outputs IE1204 Digital Design, Autumn

63 Decoder: Next state - D A LT_I_EURO EQ_I_EURO (a) 000 (b) 001 (c) 011 GT_I_EURO C D A AB (=) + (>) 0 0 (=) : EQ_1_EURO (>) : GT_1_EURO DROP READY DROP (d) 110 (f) 100 CHANGER READY RETURN_10_CENT DROP READY (e) 111 (g) 101 CHANGER_READY D A = AB( = ) + AB( > ) + AC CLR_ACC DEC_ACC IE1204 Digital Design, Autumn

64 Variable-Entered Mapping (VEM) Variable-Entered Mapping can help to draw and minimize Karnaugh diagrams with many variables. In this example there are several variables as: Coin_Present, Drop_Ready, Changer_Ready, GT, LT, EQ. Instead of opening an "extra dimension" we write a variable into the Karnaugh map You must be extra careful when drawing circuits so that you do not forget a variable combination! D A AB C (=) + (>) 0 0 IE1204 Digital Design, Autumn

65 Decoder: Next state - D B LT_I_EURO EQ_I_EURO (a) 000 (b) 001 (c) 011 GT_I_EURO C D B AB CP (=) 0 1 (=) : EQ_1_EURO CP : DROP READY DROP (d) 110 (f) 100 CHANGER READY RETURN_10_CENT DROP READY (e) 111 CLR_ACC (g) 101 DEC_ACC CHANGER_READY D B = AB( = ) + BC + BC(CP) + ABC IE1204 Digital Design, Autumn

66 Decoder: Next state- D C DROP READY LT_I_EURO EQ_I_EURO DROP (d) 110 (a) 000 (b) 001 (c) 011 GT_I_EURO (f) 100 CHANGER READY C RETURN_10_CENT D C AB CP - DR CR CP : DR: DROP_READY CR: CHANGER_READY DROP READY (e) 111 CLR_ACC (g) 101 DEC_ACC CHANGER_READY D C = AC(CP) + BC(DR) + AB(CR) + BC IE1204 Digital Design, Autumn

67 Decoder: Output signals DROP READY LT_I_EURO EQ_I_EURO DROP DROP READY (d) 110 (e) 111 CLR_ACC (a) 000 (b) 001 (c) 011 GT_I_EURO (f) 100 (g) 101 DEC_ACC CHANGER READY RETURN_10_CENT CHANGER_READY Output decoder is trivial, since its value is directly dependent on the current state DROP = CLR_ACC = ABC RETURN_10_ DEC_ACC ABC = CENT = ABC ABC IE1204 Digital Design, Autumn

68 Logic Design LT_I_EURO EQ_I_EURO GT_I_EURO DROP_READY CHANGER_READY A B Next State Decoder D A D B D C D D D B C A Output Decoder DROP RETURN_I0_CENT CLR_ACC DEC_ACC C Clk Now you can design Next State Decoder and Output Decoder by knowing the logic function of D a, D b, D c, and logic funtion of outputs Drop, Return_10_Cent, CLR_ACC, and DEC_ACC. IE1204 Digital Design, Autumn

69 Summary State minimization Analysis of a synchronous sequential circuit ASM charts Formal model for sequential circuits Next lecture: BV pp , , IE1204 Digital Design, Autumn