Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1

Size: px

Start display at page:

Download "Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1"

Erika Quinn
6 years ago
Views:

1 W Combinational circuit Flip-flops Combinational circuit Z cycle: t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t : : Figure 8.. The general form of a sequential circuit. Figure 8.2. Sequences of input and output signals. = = A = = B = ext state Output state = = = = C = A A B B A C C A C = Figure 8.3. State diagram of a simple sequential circuit. Figure 8.4. State table. Combinational circuit Y Y 2 y Combinational circuit ext state state = = Output y Y Y 2 Y Y 2 A B C dd dd d Figure 8.5. A general sequential circuit. Figure 8.6. A state-assigned table.

2 y Ignoring don't cares Using don't cares d d Y = y y 2 Y = y y 2 Y 2 y d d Y = y y + y 2 2 Y = y + 2 = ( y + y ) 2 Y y y d = y y 2 = n Figure 8.7. erivation of logic expressions. Figure 8.8. Sequential circuit derived in Figure 8.7. t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t y Control circuit R out R in R 2 out R 2 in R 3 out R 3 in one Figure 8.9. Timing diagram. Figure 8.. Signals needed in Example 8.. = A o transfer = = = B R 2 out =, R 3 in = = = C R out =, R 2 in = ext state Outputs state = = A A B B C C C A A = = R 3 out =, R in =, one = Figure 8.. State diagram. Figure 8.2. State table.

3 state extstate Outputs y Y = y + y A B C y Y 2 = y + y Figure 8.3. State-assigned table. Figure 8.4. erivation of next-state expressions. Y y R in R 3 out y one R out ext state state = = Output y Y 2 Y Y 2 Y Y 2 R 2 in A B C dd dd d R 2 out R 3 in Figure 8.5. Sequential circuit derived in Figure 8.4. Figure 8.6. Improved state assignment for the sequential circuit in Figure 8.4. Y 2 state extstate Outputs Y y A B C n Figure 8.7. Final circuit for the improved state assignment. Figure 8.8. Improved state assignment for the sequential circuit in Figure 8.2.

4 y y Y = + y Y 2 = y extstate state = = Output y 3 y Y 3 Y 2 Y Y 3 Y 2 Y A B C Figure 8.9. erivation of next-state expressions. Figure 8.2. One-hot state assignment for the sequential circuit in Figure 8.4. state extstate Outputs cycle: t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t : : Figure 8.2. One-hot state assignment for the sequential circuit in Figure 8.2. Figure Sequences of input and output signals. = = ext state Output state = = = = = = A B = = A A B B A B = = Figure State diagram. Figure State table.

5 y ext state Output state = = = = n y Y Y (a) Circuit A B y t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t (b) Timing diagram Figure State-assigned table. Figure Implementation of FSM in Figure Z y = n (a) Circuit A = R2 out =, R3 in = y Z t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t B = = C = = R out =, R2 in = R3 out =, R in =, one = (b) Timing diagram Figure Circuit that implements the specification in Figure 8.2. Figure State diagram for Example 8.4. module simple (, n,, ); input, n, ; output ; reg [2:] y, Y; parameter [2:] A = 2'b, B = 2'b, C = 2'b; n Gnd // efine the next state combinational circuit or y) case (y) A: if () Y = B; else Y = A; B: if () Y = C; else Y = A; C: if () Y = C; else Y = A; default: Y = 2'bxx; endcase EPM // efine the sequential block n or posedge ) if (n == )y <= A; elsey <= Y; // efine output assign = (y == C); endmodule V Figure Verilog code for the FSM in Figure 8.3. Figure 8.3. An FSM circuit in a small CPL.

6 module simple (, n,, ); input, n, ; output ; reg ; reg [2:] y, Y; parameter [2:] A = 2'b, B = 2'b, C = 2'b; // efine the next state combinational circuit or y) begin case (y) A: if () Y = B; else Y = A; B: if () Y = C; else Y = A; C: if () Y = C; else Y = A; default: Y = 2'bxx; endcase = (y == C); //efine output end // efine the sequential block n or posedge ) if (n == ) y <= A; else y <= Y; Figure Simulation results. endmodule Figure Second version of code for the FSM in Figure 8.3. module simple (, n,, ); input, n, ; output ; reg [2:] y; parameter [2:] A = 2'b, B = 2'b, C = 2'b; // efine the sequential block n or posedge ) if (n == ) y <= A; else case (y) A: if () y <= B; else y <= A; B: if () y <= C; else y <= A; C: if () y <= C; else y <= A; default: y <= 2'bxx; endcase // efine output assign = (y == C); endmodule Figure Third version of code for the FSM in Figure 8.3. Figure Simulation results for the Mealy machine. A Shift register Shift register B a b Adder FSM s Shift register Sum = A + B Figure Potential problem ith asynchronous inputs to a Mealy FSM. Figure Block diagram of a serial adder.

7 G ( ab s ) H ext state Output s state ab = G G G G H H G H H H G: H: carry-in = carry-in = Figure 8.4. State diagram for the serial adder. Figure 8.4. State table for the serial adder. ext state Output state ab = y Y s a b Full adder Y carry-out y s Figure State-assigned table for the serial adder. Figure Circuit for the adder FSM. G s = H s = extstate Output state ab = s G G G G H G G G G H H G H H H H G H H H G s = H s = Figure State diagram for the Moore-type serial adder FSM. Figure State table for the Moore-type serial adder FSM.

8 extstate state ab = Output y s Y 2 Y a b Full adder Sum bit Carry-out Y y s Y 2 Figure State-assigned table for the Moore-type serial adder FSM. Figure Circuit for the Moore-type serial adder FSM. module shiftrne (R, L, E,,, ); parameter n = 8; input [n-:] R; input L, E,, ; output [n-:] ; reg [n-:] ; integer k; a 7 a L E L E 3 2 Counter 3 2 ) if (L) <= R; else if (E) begin for (k = n-; k > ; k = k-) [k-] <= [k]; [n-] <= ; end b 7 b L E Adder FSM Run L E endmodule Sum 7 Sum Figure Code for a left-to-right shift register ith an enable input. Figure 8.5a. Synthesied serial adder. ext state Output state = = A B C B F C F E B G E F C F E G F G Figure 8.5b. Simulation results for the synthesied serial adder. Figure 8.5. State table for Example 8.6.

9 sense sense extstate Output state = = A B C B A F C F C F C A (a) Timing diagram sense (b) Circuit that generates Figure Minimied state table for Example 8.6. Figure Signals for the vending machine. S4 S2 S5 S S3 S6 S7 ext state Output state = S S S3 S2 S2 S2 S4 S5 S3 S3 S6 S7 S4 S S5 S3 S6 S6 S8 S9 S7 S S8 S S9 S3 S8 S9 Figure State diagram for Example 8.7. Figure State table for Example 8.7. ext state Output state = S S S3 S2 S2 S2 S4 S5 S3 S3 S2 S4 S4 S S5 S3 S S3 S2 S5 S4 Figure Minimied state table for Example 8.7. Figure Minimied state diagram for Example 8.7.

10 S ext state Output state = = = = S3 A B C B C F E B G E F C F E G F S2 Figure Mealy-type FSM for Example 8.7. Figure Incompletely specified state table for Example 8.8. = = = = = = = = A/ B/ C/2 /3 H/7 = = G/6 = = F/5 = = E/4 = = ext state state = = Output A A B B B C C C 2 E 3 E E F 4 F F G 5 G G H 6 H H A 7 Figure 8.6. State diagram for a counter. Figure 8.6. State table for the counter. ext state Count state = = y y 2 Y 2 Y Y Y 2 Y Y A B C E F G H y y y y y y Y = y + y Y = y + y y + y y Y 2 = + y + y + y y Figure State-assigned table for the counter. Figure arnaugh maps for flip-flops for the counter.

11 J y Flip-flop inputs Count state = = y y 2 Y 2 Y Y J 2 2 J J Y 2 Y Y J 2 2 J J d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d J J y n Figure Excitation table for the counter ith J flip-flops. Figure Circuit diagram using J flip-flops. J y ext Output state state 2 J J y A B B C C E E F F G G H H A n Figure Factored-form implementation of the counter. Figure State table for the counterlike example. ext Output state state 2 y y Y 2 Y Y 2 Figure 8.7. State-assigned table. Figure 8.7. Circuit for the counterlike example.

12 r r 2 r 3 Idle Idle xx xx r r gnt g = gnt g = xx xx x r 2 r r r 2 gnt2 g 2 = gnt2 g 2 = xx xx r 3 r 2 r r 2 r 3 gnt3 g 3 = gnt3 g 3 = xx r 3 Figure State diagram for the arbiter. Figure Alternative style of state diagram for the arbiter. Figure Simulation results for the arbiter circuit. Figure Output delays in the arbiter circuit. Y y Y 2 n Figure Output delay hen using one-hot encoding. Figure Circuit for Example 8.9.

13 ext State Output state = = y Y 2 Y Y 2 Y ext state Output state = = J J y (a) State-assigned table A A B B A C C A A (b) State table J 2 2 J n Figure Tables for the circuit in Example 8.9. Figure 8.8. Circuit for Example 8.. Flip-flop inputs state = = Output y J 2 2 J J 2 2 J y T 2 T n Figure 8.8. Excitation table for the circuit in Figure 8.8. Figure Circuit for Example 8.. State name Flip-flop inputs state = = Output y T 2 T 2 Output signals or actions (Moore type) (a) State box (False) Condition (True) expression Conditional outputs or actions (Mealy type) (b) ecision box (c) Conditional output box Figure Excitation table for the circuit in Figure Figure Elements used in ASM charts.

14 A Idle r gnt g r B r 2 gnt2 g 2 r 2 r 3 gnt3 g 3 r 3 Figure ASM chart for the FSM in Figure Figure ASM chart for the arbiter. Inputs n Combinational circuit m Outputs ext state state = = Output y Y 2 Y Y 2 Y y k Y k -state variables ext-state variables y Y Figure The general model for a sequential circuit. Figure P8.. State-assigned table for problems 8. and 8.2. Figure P8.2. Circuit for problem 8.29.

Chapter 6. Synchronous Sequential Circuits

Chapter 6. Synchronous Sequential Circuits Chapter 6 Synchronous Sequential Circuits In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs. In a sequential circuit, the values of the outputs