Chapter 15 SEQUENTIAL CIRCUITS ANALYSIS, STATE- MINIMIZATION, ASSIGNMENT AND CIRCUIT IMPLEMENTATION
|
|
|
- Eugene Spencer
- 6 years ago
- Views:
Transcription
1 Chapter 15 SEQUENTIAL CIRCUITS ANALYSIS, STATE- MINIMIZATION, ASSIGNMENT AND CIRCUIT IMPLEMENTATION
2 Lesson 2 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
3 Outline Procedure Excitation table Transition table State table State Diagram Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
4 Analysis Procedure Clocked Sequential circuit 1. Draw logic circuit diagram 2. Perform state variable assignments and excitation variable(means FF inputs) assignments 3. Find the expressions for excitations from flip-flop characteristic equations as per the excitations variables and make an excitation table. [Find Q = F Q (X, Q) and Y.] Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
5 Analysis Procedure 4. Make transition table from the expressions for Y = F (X, Q) in case o of Mealy model and Y = F (X) in o case of Moore model. 5. Perform state minimization and make minimal state table. 6. Draw the state diagram. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
6 Outline Procedure Excitation table Transition table State table State Diagram Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
7 Excitation table Tabular representation of X and Q at the FFs and of Y as per F Q for the combination circuit at the output stages. Gives present states and the inputs given at the memory section. Gives the memory-section outputs that follow the excitations Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
8 Excitation Table for Y = X. Q2 +Q1; Q1 =D and Q2 = Q n+1 = J. Q n + K. Q n State Excitation Inputs Y (Q 1,Q 2) [D, (J, K)] X=0 [D, (J, K)] X=1 X=0 X =1 (0, 0) 0, (0, 0) 1, (0,1) 0 0 (0, 1) 0, (0, 0) 1, (0,1) 1 0 (1, 0) 0, (1, 0) 1, (1,1) 1 1 (1, 1) 0, (1, 0) 1, (1,1) 1 1 Y is present output state after the X inputs but before transition Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
9 Excitation Table Rows Number of rows in each column equals 2 m where m is the number of flip-flops because each flip-flop has one Q output and m flipflops will have 2 m different combinations of the states at the Qs. For example, if (Q1, Q2) are the Qs of two FFs, then (Q1, Q2) = (0, 0), (0, 1), (1, 0) and (1, 1) are the four combinations possible for the four different states of the memory section present outputs Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
10 Excitation Table Columns First column present state (Q1, Q2) in its each row The number of columns for the excitation inputs Q equals the number of possible combinations of external inputs in the set X. It equals 2 i if there are i distinct literal to represent the inputs when there are i inputs X 0, X 1, X i 1. If i = 1, then columns 2 and 3 will be for X = 0 and X =1, as there are two possible values of X. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
11 Excitation Inputs For each set of inputs, there is a set of excitation inputs to the memory section, for example, corresponding to each set of external inputs, there will be four sets of inputs to (D1, D2) in case of two D-FFs at the memory section Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
12 Mealy Model Excitation Inputs If (X1, X2) are the external input to the memory section then (X1, X2) = (0, 0), (0, 1), (1, 0) and (1, 1) are the four combinations possible for the four different states of the memory section present outputs, which are also inputs for excitation on next clock instance. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
13 Moore Model Excitation Inputs The number of column = 1 for a set of Q inputs Q as in Moore model Q depends on Qs only. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
14 Output Y in Mealy Model Excitation Table The number of columns for the output Y also equals the number of possible 2 i combinations of external inputs in the set X. Suppose output stage has two outputs, Y1 and Y2. Then there will be 4 columns for the four sets of the external inputs and each column having entries for values of (Y1, Y2) Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
15 Moore Model Excitation Table The number of column = 1 for the output Y as in Moore model Y depends on Qs only. The column entries for values of (Y1, Y2) as per the combinational circuit between the memory section output Qs and Ys Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
16 Outline Procedure Excitation table Transition table State table State Diagram Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
17 Transition table A tabular representation of F and F. Q o It shows how the sequential circuit FF will respond to all the present inputs Xs and Qs and will generate Ys from the Q s. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
18 Transition Table for Y = X. Q2 +Q1; Q1 =D and Q2 = Q n+1 = J. Q n + K. Q n State Transition Outputs Y (Q 1,Q 2) [Q1,Q2 ] X=0 [Q1,Q2 ] X=1 X=0 X =1 (0, 0) 0, 0 1, (0, 1) 0, 1 1, (1, 0) 0, 1 1, (1, 1) 0, 1 0, Y is present output state after the X inputs but before transition Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
19 Transition Table Rows Number of rows in each column equals 2 m where m is the number of flip-flops because each flip-flop has one Q output and m flipflops will have 2 m different combinations of the states at the Qs. For example, if (Q1, Q2) are the Qs of two FFs, then (Q1, Q2) = (0, 0), (0, 1), (1, 0) and (1, 1) are the four combinations possible for the four different states of the memory section present outputs Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
20 Transition Table Columns First column present state (Q1, Q2) in its each row The number of columns for the transition outputs Q equals the number of possible combinations of external inputs in the set X. It equals 2 i if there are i distinct literal to represent the inputs when there are i inputs X 0, X 1, X i 1. If i = 1, then columns 2 and 3 will be for X = 0 and X =1, as there are two possible values of X. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
21 Transition Outputs For each set of FF-inputs, there is a set of transition outputs of the memory section, for example, corresponding to each set of external inputs, there will be two sets of outputs to (Q1, Q2) in case of two FFs (one D and one J-K) at memory section Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
22 Y Outputs If (X1, X2) are the external input to the memory section then (X1, X2) = (0, 0), (0, 1), (1, 0) and (1, 1) are the four combinations possible for the four different states of the memory section present outputs Y. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
23 Moore and Mealy Model Transition tables Moore Model The number of column = 1 each for the transition output set Q and output Y, as in Moore model Y depends on Qs only. Mealy Model The column entries for values of (Y1, Y2) and set of Q s will be 2 each when there is only one external input Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
24 Outline Procedure Excitation table Transition table State table State Diagram Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
25 State Table State table can made easily A set of present Q0, Q1,.. denotes a state Each set assigned a state-name S i as follows: (Q1, Q2) = (0,0) S 0 (Q1, Q2) = (0,1) S 1 (Q1, Q2) = (0,0) S 2 (Q1, Q2) = (0,0) S 3 Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
26 State table 1. Tabular representation of Q, Q at given Y in terms of S0, S1, S2,...states assigned to the sets of the Qs at FFs 2. Gives in terms of S0, S1, S2,...the memory-section outputs that follow the state transitions after excitation inputs Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
27 State Table for Y = X. Q2 +Q1; Q1 =D and Q2 = Q n+1 = J. Q n + K. Q n State Next State Outputs Y (Q 1,Q 2) [Q1, Q2] X=0 [Q1, Q2] X=1 X=0 X =1 S 0 S 0 S S 1 S 1 S S 2 S 1 S S 3 S 1 S Y is present output state after the X inputs but before transition Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
28 Number of maximum possible states There are z (=2 m ) maximum possible states S 0, S 1,, S in a sequential m 1 circuit with m-ffs Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
29 State Table Rows Number of row in state table = z, one row for each state For m = 2, rows are for S0, S1, S2 and S3, each corresponding to a state of the circuit. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
30 State Table Columns First column S0, S1, S2 and S3 for four rows The number of columns for State-outputs equals the number of possible combinations of external inputs in the set X. It equals 2 i if there are i distinct literal to represent the inputs when there are i inputs X 0, X 1, X i 1. If i = 1, then columns 2 and 3 will be for X = 0 and X =1, as there are two possible values of X. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
31 Number of Y Output columns Same as number of columns for next state before Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
32 State minimization from state table We shall learn it in next lesson Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
33 Outline Procedure Excitation table Transition table State table State Diagram Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
34 State Diagram A set of present Q0, Q1,.. is denoted by a state. A state diagram is a diagrammatic representation of state table to show the transitions from present state to next state. A state diagram is drawn after state minimization at the state table Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
35 Number of Nodes A circle shows a node The number of nodes = number of rows in the state table. For two flip-flops, there are four states S1, S2, S3 and S4. So four circles are drawn for the four nodes Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
36 Directed Arc A directed arc from the present state node to the next state node shows a transition Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
37 Directed arcs to next state A small diameter directed circular arc, which starts from node and ends at the same node represents a transition in which the state remains unchanged [S i remains S i ] The number of directed circular arcs equals the number of transitions in which the state does not change Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
38 Directed arcs to next state A small diameter directed arc, which starts from node and ends at another node represents a transition in which the state changed [S i becomes S j ] The number of directed arcs to another node equals the number of transitions in which the state changes Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
39 Mealy Model state diagram Each state S 0 or S 1,... is labeled as S 0 or S 1 at the center of circle, which is representing the node Each arc or circular arc is labeled as X/Y [present input X and output Y]. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
40 Mealy Model state diagram Each arc or circular arc can have more then one set of (pre-transition input/ output) labeled on it if there are more than one sets of pre-transition input/ output that are having the same transition from one node to another. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
41 Moore Model state diagram Each state S 0 or S 1,... is labeled as S 0 or S 1 at the center of circle, which is representing the node Each arc or circular arc is labeled by present input from Qs. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
42 Moore Model state diagram Each arc or circular arc has one set of (pre-transition input) labeled on it if there are more than one sets of (pretransition input) that are having the same transition from a node to another. Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
43 Summary
44 Analysis of logic clocked sequential circuit is in steps: Making excitation table Making state transition table Making State table Reducing the table after a state minimization process Draw state diagram using circles and directed arcs
45 End of Lesson 2 on ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT
46 THANK YOU Ch15L2- "Digital Principles and Design", Raj Kamal, Pearson Education,
Chapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 JK Flip-Flop ve edge triggered Output Q and
Lecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
Clocked Synchronous State-machine Analysis
Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input
ELE2120 Digital Circuits and Systems. Tutorial Note 9
ELE2120 Digital Circuits and Systems Tutorial Note 9 Outline 1. Exercise(1) Sequential Circuit Analysis 2. Exercise (2) Sequential Circuit Analysis 3. Exercise (3) Sequential Circuit Analysis 4. Ref. Construction
Digital Circuits and Systems
EE201: Digital Circuits and Systems 4 Sequential Circuits page 1 of 11 EE201: Digital Circuits and Systems Section 4 Sequential Circuits 4.1 Overview of Sequential Circuits: Definition The circuit whose
6 Synchronous State Machine Design
Design of synchronous counters. Based on the description of the problem, determine the required number n of the FFs - the smallest value of n is such that the number of states N 2 n and the desired counting
11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of
EE 2449 Experiment 11 Jack Levine and Nancy Warter-Perez CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 11 SEQUENTIAL CIRCUITS
Finite State Machine. By : Ali Mustafa
Finite State Machine By : Ali Mustafa So Far We have covered the memory elements issue and we are ready to implement the sequential circuits. We need to know how to Deal(analyze) with a sequential circuit?
The Design Procedure. Output Equation Determination - Derive output equations from the state table
The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types
Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..
Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
Synchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
Sequential Circuit Analysis
Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll
Logical design of digital systems
21062017 lectures Summer Semester 2017 Table of content 1 Combinational circuit design 2 Elementary combinatorial circuits for data transmission 3 Memory structures 4 Programmable logic devices 5 Algorithmic
Lecture 8: Sequential Networks and Finite State Machines
Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University
Chapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Sequential circuit: A circuit that includes memory elements. In this case the output depends not only on the current input but also on the past inputs. Memory A synchronous
Sequential Synchronous Circuit Analysis
Sequential Synchronous Circuit Analysis General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time
Synchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
Chapter 4 Part 2 Sequential Circuits
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 4 Part 2 Sequential Circuits Originals by: Charles R. Kime and Tom Kamisnski
Problem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
Finite State Machine (FSM)
Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State
ECE380 Digital Logic. Synchronous sequential circuits
ECE38 Digital Logic Synchronous Sequential Circuits: State Diagrams, State Tables Dr. D. J. Jackson Lecture 27- Synchronous sequential circuits Circuits here a clock signal is used to control operation
EEE2135 Digital Logic Design
EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the
FSM model for sequential circuits
1 FSM model for sequential circuits The mathematical model of a sequential circuit is called finite-state machine. FSM is fully characterized by: S Finite set of states ( state ~ contents of FFs) I Finite
Lecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
Sequential logic and design
Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by
CprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,
Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER
Synchronous Sequential Logic Part I BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Sequential Logic Digital circuits we have learned, so far, have been combinational no memory,
Different encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page of COE 22: Digital Logic Design (3--3) Term (Fall 22) Final Exam Sunday January
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
or 0101 Machine
Synchronous State Graph or Synchronous State Graph or Detector Design a state graph for a machine with: One input X, one output Z. Z= after receiving the complete sequence or Overlapped sequences are detected.
3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value
EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following
COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Important Design Concepts State Reduction and Assignment Design
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
Chapter 5. Karnaugh Map and Minimization Procedures
hapter 5 Karnaugh Map and Minimization Procedures Lesson 1 KARNAUGH MAP h05l1-"digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Three variable Karnaugh map Four variable Karnaugh
Fundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
Lecture (08) Synchronous Sequential Logic
Lecture (08) Synchronous Sequential Logic By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II Analysis of Clocked Sequential Circuits The behavior of a clocked sequential
ELE2120 Digital Circuits and Systems. Tutorial Note 10
ELE2120 Digital Circuits and Systems Tutorial Note 10 Outline 1. 1. Sequential Circuit Design 2. 2. Design procedure: a complete example illustration Sequential circuit analysis & design In sequential
Synchronous Sequential Logic Part I
Synchronous Sequential Logic Part I Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Sequential Logic Digital circuits we have learned, so far, have been combinational no memory, outputs are entirely
COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 3 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives State Reduction and Assignment Design of Synchronous Sequential
Synchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
Chapter 18 FUNDAMENTAL MODE SEQUENTIAL CIRCUITS
Chapter 18 FUNDAMENTAL MODE SEQUENTIAL CIRCUITS Lesson 3 Races 2 Race condition Cycles of races Critical races Outline 3 Excitation Table for Y O = X. Q2 +Q1; Q1 =D and Q2 = Q n+1 = J. Q n + K. Q n State
EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007
EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler
Analysis of Clocked Sequential Circuits
Objectives Analysis of Clocked Sequential Circuits The objectives of this lesson are as follows: Analysis of clocked sequential circuits with an example State Reduction with an example State assignment
PAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS:
EKURHULENI TECH COLLEGE. No. 3 Mogale Square, Krugersdorp. Website: www. ekurhulenitech.co.za Email: info@ekurhulenitech.co.za TEL: 011 040 7343 CELL: 073 770 3028/060 715 4529 PAST EXAM PAPER & MEMO N3
UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
Digital Logic Design. Midterm #2
EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm - igital Logic esign Midterm #2 Problems Points. 5 2. 4 3. 6 Total 5 Was the exam fair? yes no EECS: igital Logic esign r. nthony. Johnson s7m2s_dild7.fm
Lecture 17: Designing Sequential Systems Using Flip Flops
EE210: Switching Systems Lecture 17: Designing Sequential Systems Using Flip Flops Prof. YingLi Tian April 11, 2019 Department of Electrical Engineering The City College of New York The City University
ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
Total time is: 1 setup, 2 AND, 3 XOR, 1 delay = (1*1) + (2*2) + (3*3) + (1*1) = 15ns
Clock Period/ Delay Analysis: Find longest possible path (time-wise) between two flip-flops. If 2ns for AND and 3ns for XOR, with T delayff = 1ns and T setupff = 1 ns. So the total time is: 1 setupff +
CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008
CSE 14 Midterm 2 Tajana Simunic Rosing Spring 28 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages.
Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.
Week-5 Sequential Circuit Design Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA. Storing a value: SR = 00 What if S = 0 and R = 0? The equations on the
Chapter 6 Introduction to state machines
9..7 hapter 6 Introduction to state machines Dr.-Ing. Stefan Werner Table of content hapter : Switching Algebra hapter : Logical Levels, Timing & Delays hapter 3: Karnaugh-Veitch-Maps hapter 4: ombinational
COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University
1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the
Sequential Circuit Design
Sequential Circuit esign esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination
Digital Design 2010 DE2 1
1 Underviser: D. M. Akbar Hussain Litteratur: Digital Design Principles & Practices 4 th Edition by yj John F. Wakerly 2 DE2 1 3 4 DE2 2 To enable students to apply analysis, synthesis and implementation
Sequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process
Parity Checker Example A string of bits has even parity if the number of 1 s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even
Analysis and Design of Sequential Circuits: Examples
COSC3410 Analysis and Design of Sequential Circuits: Examples J. C. Huang Department of Computer Science University of Houston Sequential machine slide 1 inputs combinational circuit outputs memory elements
Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing
IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of
Digital Logic Design - Chapter 5
Digital Logic Design - Chapter 5 S. Design a 2-bit binary up counter a) using positive-edge-triggered D flip-flops. b) using positive-edge-triggered T flip-flops. c) using positive-edge-triggered JK flip-flops.
Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90
Final Exam ECE 25, Spring 2008 Thursday, June 12, 2008 Name: PID: Problem Points Score 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 Total 90 1) Number representation (10 pts) a) For each binary vector
Chapter 9 Asynchronous Sequential Logic
9.1 Introduction EEA051 - Digital Logic 數位邏輯 Chapter 9 Asynchronous Sequential Logic 吳俊興高雄大學資訊工程學系 December 2004 Two major types of sequential circuits: depending on timing of their signals Asynchronous
Chapter 7 Sequential Logic
Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics
CSE 140: Components and Design Techniques for Digital Systems. Lecture 9: Sequential Networks: Implementation
CSE 4: Components and Design Techniques for Digital Systems Lecture 9: Sequential Networks: Implementation CK Cheng Dept. of Computer Science and Engineering University of California, San Diego Implementation
14:332:231 DIGITAL LOGIC DESIGN
14:332:231 IGITL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering all 2013 Lecture #17: locked Synchronous -Machine nalysis locked Synchronous Sequential ircuits lso known as
Review for Final Exam
CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has
FSM Optimization. Counter Logic Diagram Q1 Q2 Q3. Counter Implementation using RS FF 10/13/2015
/3/5 CS: Digital Design http://jatinga.iitg.ernet.in/~asahu/cs FSM Optimization A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Outline Last Class: Comb. Cirt. Complexity (CCC)
EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK
Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall 2014-2015 Midterm Examination CLOSED BOOK Kewal K. Saluja
Lecture 3 Review on Digital Logic (Part 2)
Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal
Synchronous Sequential Logic. Chapter 5
Synchronous Sequential Logic Chapter 5 Other Flip Flops D flip flops requires smallest number of gates. Thus, they are commonly used Other flip flops are JK flip flops T flip flops
Chapter 7. Synchronous Sequential Networks. Excitation for
Chapter 7 Excitation for Synchronous Sequential Networks J. C. Huang, 2004 igital Logic esign 1 Structure of a clocked synchronous sequential network Mealy model of a clocked synchronous sequential network
Synchronous Sequential Circuit Design
Synchronous Sequential Circuit Design 1 Sequential circuit design In sequential circuit design, we turn some description into a working circuit We first make a state table or diagram to express the computation
Chapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)
Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation
ASYNCHRONOUS SEQUENTIAL CIRCUITS
ASYNCHRONOUS SEQUENTIAL CIRCUITS Sequential circuits that are not snchronized b a clock Asnchronous circuits Analsis of Asnchronous circuits Snthesis of Asnchronous circuits Hazards that cause incorrect
Digital Logic Design - Chapter 4
Digital Logic Design - Chapter 4 1. Analyze the latch circuit shown below by obtaining timing diagram for the circuit; include propagation delays. Y This circuit has two external input and one feedback
P2 (10 points): Given the circuit below, answer the following questions:
P1 (10 points): Given the function f(a, b, c, d) = m(3,4,5,10,14) + D(6,7): A: Fill in the timing diagram for f. B: Implement f using only 2-1 MUXes. Your circuit should not include more than four 2-1
14.1. Unit 14. State Machine Design
4. Unit 4 State Machine Design 4.2 Outcomes I can create a state diagram to solve a sequential problem I can implement a working state machine given a state diagram STATE MACHINES OVERVIEW 4.3 4.4 Review
Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
Menu. Master-Slave Flip-Flop
Menu Clocks and Master-lave Flip-Flops J-K and other Flip-Flops Truth table & excitation table Adders (see [Lam: pg 130]) Counters Look into my... 1 CLK Master-lave Flip-Flop Master-lave Latch/Flip-Flop
CPE100: Digital Logic Design I
Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe1/ CPE1: Digital Logic Design I Section 14: Dr. Morris Sequential Logic Design Chapter 3 Chapter
Mealy & Moore Machines
Mealy & Moore Machines Moore Machine is a finite-state machine whose output values are determined solely by its current state and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the
CSE140: Digital Logic Design Registers and Counters
CSE14: Digital Logic Design Registers and Counters Prof. Tajana Simunic Rosing 38 Where we are now. What we covered last time: ALUs, SR Latch Latches and FlipFlops (FFs) Registers What we ll do next FSMs
Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1
Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential
Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
![Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution](/thumbs/79/79145081.jpg "Vidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution")
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
University of Minnesota Department of Electrical and Computer Engineering
University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID
Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1
Synchronous Sequential Circuit Design Dr. Ehab A. H. AL-Hialy Page Motivation Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC) Outputs are Function of State (and Inputs)
Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts
ed Sequential Circuits 2 Contents nalysis by signal tracing & timing charts State tables and graphs General models for sequential circuits sequential parity checker Reading Unit 3 asic unit Unit : Latch
FYSE420 DIGITAL ELECTRONICS
FYSE42 IGITAL ELECTRONICS Lecture 4 [] [2] [3] IGITAL LOGIC CIRCUIT ANALYSIS & ESIGN Nelson, Nagle, Irvin, Carrol ISBN -3-463894-8 IGITAL ESIGN Morris Mano Fourth edition ISBN -3-98924-3 igital esign Principles
DE58/DC58 LOGIC DESIGN DEC 2014
Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc.
Finite State Machines Introduction Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc. Such devices form
10/12/2016. An FSM with No Inputs Moves from State to State. ECE 120: Introduction to Computing. Eventually, the States Form a Loop
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering An FSM with No Inputs Moves from State to State What happens if an FSM has no inputs? ECE 120: Introduction to Computing
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Following the slides of Dr. Ahmed H. Madian Lecture 10 محرم 1439 ه Winter
MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals
The Karnaugh Map COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Boolean Function Minimization The Karnaugh Map (K-Map) Two, Three,