5 State Minimisation. university of applied sciences hamburg. Digital Systems. Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz

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1 5 State Minimisation In an early design phase when a word description of a sequential circuit's function is transformed into a FSM state diagram or state table redundant states may arise. State minimisation has to achieve a FSM with the same output behaviour corresponding to the original state transition table but with a smaller number of states. The removal of redundant states is important because of several reasons: ost: The number of memory elements is directly related to the number of states. The number of gates which form the combinational logic for next state and output derivation may increase in general with the number of states. omplexity: The more states the circuit contains, the more complex the design and its associated implementation will become. Failure analysis: diagnostic routines are often predicated on the assumption that no redundant states exist. B. Schwarz 5-1

2 Redundant states will be removed by grouping and substituting equivalent states without altering the circuits behaviour. States are equivalent if we cannot distinguish in which of two or more states a sequential circuit starts by applying input sequences and observing the outputs. efinition of state equivalence Let S k and S l be the next states of a FSM when input I p is applied while the sequential circuit is in states S i and S j respectively. Then S i and S j are equivalent if and only if for every possible input I p, 1. The output produced by the state S i is equal to the output produced by sate S j. 2. The next states S k and S l are equivalent. The first condition is necessary. If S k and S l are not equivalent there is an input sequence I 1,I 2... I m that produces a different output sequence for S i as a starting state than for S j as starting state. Hence S i and S j cannot be equivalent unless the second condition is satisfied. These two conditions form the basis for all state reduction techniques. B. Schwarz 5-2

3 5.1 Partitioning Method The partitioning approach is a successive determination of partitions P K, K = 1, 2, 3,..., l, in which each P K is composed of a number of blocks, each of which consists of a group of one or more states. The states contained within a block of P K are K- equivalent. I. e. given a FSM with 5 states S 1,..., S 5 and P K = (S 1 S 3 ) (S 2 S 4 ) (S 5 ), then P K contains three blocks with state pairs S 1 - S 3 and S 2 - S 4 are K-equivalent. Procedure with three steps: Step 1: The first partition P 1 is formed by placing two or more states in the same block of P 1 if and only if their output is identical for each input. For the example on the next page we have P 1 = (AB)(E), and hence the states within each block are 1-equivalent. This step guarantees that each block in P 1 satisfies condition 1. Step 2: Successive partitions P K,K = 2, 3, 4..., l, are derived by placing two or more states in the same block of P K if and only if for each input value their next states all B. Schwarz 5-3

4 lie in a single block of P K-1. This iterative procedure is suggested by condition 2 for equivalent states. Step 3: When P K+1 = P K, which means a partition repeats, the states in each block of P K that are K-equivalent are (K+1)-equivalent, (K+2)-equivalent and so on. The last partition P K is said to be an equivalence partition. ondition 2 for equivalent states is now satisfied by P K. B. Schwarz 5-4

5 1. Example: State Next State X=0 X=1 A /1 B/0 B /1 E/0 E/0 /0 E E/0 A/1 State Table Partition Next States P 0 Output for X = 0 Output for X = 1 Partition Blocks (ABE) Action Seperate (AB) and (E) Seperate (AB) and (E) P 1 NS for X = 0 NS for X = 1 (AB) (E) B E BEE BA Seperate (A) and (B) P 2 NS for X = 0 (A) (B) (E) B E NS for X = 1 B EE BA Seperate () and (E) P 3 NS for X = 0 NS for X = 1 (A) (B) () (E) B E B EE B A P 4 = P 3 (A) (B) () (E) State equivalence by partitioning B. Schwarz 5-5

6 omments on the partitioning procedure for the 1. Example: Partition P 2 is obtained by examining each block of P 1. In the first block of P 1 the next states for A, B and with X = 0 all lie in the same block of P 1. For X = 1 the next state of A lies in a different block of P 1 than the next states of B and. Therefore the block (AB) contained in P 1 is split into the blocks (A) (B) in P 2. In the second block of P 1 the next states for and E lie in the same block of P 1 for both X values. Hence and E will remain in the same block of P 2. P 2 = (A) (B) (E), the states within each block are 2-equivalent. Partition P 3 is obtained by examining each block of P 2. The next states of B and lie in the same block of P 2 for each input and hence the block (B) remains in P 3. The next states for and E with x = 1 now lie in different blocks of P 2 and hence these two states must be separated into different blocks of P 3. P 3 = (A) (B) () (E), the states B and are 3-equivalent. B. Schwarz 5-6

7 2. Example: State table reduction for a Mealy FSM S X/Y 1/1 A 0/1 0/1 B 1/0 1/1 S A B 0/1 1/0 State Table S + /Y X=0 X=1 /1 /0 A/1 /0 A/1 /0 0/0 Partition Next States P 0 Y for X = 0 Y for X = 1 P 1 Partition Blocks (A) (B) () NS for X = 0 A B NS for X = 1 B A P 2 = P 1 (A) (B) () Action (AB) Sep. (A), (B), () B. Schwarz 5-7

8 3. Example: State table reduction for a Moore FSM State A B E F G State Table Next State X=0 X=1 B F F E B G F E F G Output Y Partition Next States P 0 Output P 1 NS for X = 0 NS for X = 1 P 2 NS for X = 0 NS for X = 1 Partition Blocks Action (ABEFG) Sep. (AB) and (EFG) (AB) (EFG) BB FFEF FG EG Sep. (F) and (EG) (AB) (EG) (F) BB FFF E FG EG Sep. (B) and (A) P 3 NS for X = 0 NS for X = 1 (A) (B) (EG) (F) BB FFF E G F EG P 4 = P 3 (A) (B) (EG) (F) B. Schwarz 5-8

9 omments on the partitioning procedure for the 3. Example: All Moore states which generate the same output level Y are combined into separate blocks of partition P 1. Partition P 2 is obtained by examining each block of P 1. In the first block of P 1 the next states for A, B and with X = 0 and X = 1 all lie in the same block of P 1. In the second block of P 1 the next states for, E, F and G lie all in the second block of P 1 for X = 0. For X = 1 the next state of F lies in the first block of P 1 and the next states of, E and G belong to the second block. Therefore the block (EFG) contained in P 1 is split into the blocks (F) (EG) in P 2. P 2 = (AB) (EG) (F), the states within each block are 2-equivalent. Partition P 3 is obtained by examining each block of P 2. The next states of A, B and lie in different blocks of P 2 for input X = 1. Hence states A and must be separated into a different block of P 3 than state B. P 3 = (A) (B) (EG) (F), the states A and are 3-equivalent as well as states, E and G. B. Schwarz 5-9

10 5.2 FSM controller for a andy Vending Machine A andy costs 15 cents and the machine accepts nickels (5 cent) and dimes (10 cent) in an arbitrary sequence. No change at all will be returned, instead the machine expects that another candy will be bought. Input signals: ( 1dime = 10 cent are inserted), N ( 1 nickel = 5 cent are inserted). The output Y equals to '1' when a candy is released. efinition of states for a Moore FSM: S1: Initial state, no money is deposited and no candy is released. S2: 10 cents have been inserted for the first time. S3: 5 cents have been inserted the first time. S4: 10 cents and 5 cents have been deposed in a sequence. Output Y = 1. S5: Two dimes are deposited and a candy will be released. A credit of 5 cents is deposited. S6:... B. Schwarz 5-10

11 The FSM will be clocked with a high frequency. Input Signal Synchronisation The input circuit with two chained -flip-flops will insure that slow dropping coins which are sensed by the coin detector (SENSE) will generate input pulses (MONO) just for a single clock cycle. We can assume that it is physically impossible to insert two coins at the same time and therefore we cannot have N = = 1 in the same clock period. B. Schwarz 5-11

12 State iagram for the oin-operated andy Machine esign S Y N S1 0 Reset S4 1 S2 0 S3 0 S7 1 S5 1 S6 0 S8 1 S9 1 B. Schwarz 5-12

13 State Reduction by Partitioning S S1 S2 S3 S4 S5 S6 S7 S8 S9 State table S + N= Y Partition Partition Blocks Action P 1 N = 00 N = 01 N = 10 N = 11 P 2 N = 00 N = 01 N = 10 N = 11 P 3 N = 00 N = 01 N = 10 N = 11 P 4 N = 00 N = 01 N = 10 N = 11 B. Schwarz 5-13

14 Reduced State iagram for the Moore-Model S Reduced State Table S + N= Y S1 0 Reset N S1 S2 S3 S4 S5 S2 0 S5 1 S4 1 B. Schwarz 5-14

15 Reduced State iagram for the Mealy Model With each state 4 input signal combinations can generate different output signals. Therefore the number of states will be less than with the Moore FSM. S N / Y Reset S1 S3 S2 B. Schwarz 5-15

16 5.3 Implication Table Procedure The implication table is another tool that can be used to remove redundant states. The procedure is a sequence of five steps, which can be more time consuming than the partitioning approach. Step 1: Form a table by listing vertically all states in the table except the first and horizontally all states except the last. The implication table displays all possible combinations of two states and hence each cell corresponding to the intersection of a row and a column represents two states being tested for equivalence. Step 2: A cross is placed in the cells with pairs of states whose outputs are not equal for every input. (condition 1) Step 3: Into the vacant cells are placed the pairs of next states whose equivalence is "implied" by the two states whose intersection defines the cells (condition 2). If the implied pairs for any cell contain only the states that define the cell or the next states are the same for a given input, then a check mark (b) is placed in the cell. B. Schwarz 5-16

17 Step 4: Successive passes are made through the entire table to determine if any cells should be crossed off additionally. A cell has to be crossed out if it contains at least one implied pair of next states that defines a cell that has previously been crossed out. Step 5: Finally the implication table is examined column by column to see the cell which are not crossed out. The states that define these cells are equivalent and are listed as blocks of the equivalence partition. Pairs are combined by using transitivity: (S j S i) ) (S i S k ) (S j S i S k ) 1. Example: Implication table for a five-state circuit. State Table S S + /Y X=0 X=1 A B E /1 /1 /0 E/0 B/0 E/0 E/0 A/1 B E A B B. Schwarz 5-17

18 2. Example: Implication table for a six-state circuit. State Table S S + / Y V0 V1 V2 R0 R1 R2 EN, IR 0, X 1, 0 1, 1 V0 / 0 V0 / 0 V2 / 0 R0 / 0 R2 / 0 R2 / 0 V1 / 0 V2 / 0 V0 / 1 V1 / 0 V2 / 0 V0 / 1 R2 / 1 R0 / 0 R1 / 0 R2 / 1 R0 / 0 R1 / 0 V1 V2 R0 R1 R2 V0 V1 V2 R0 R1 B. Schwarz 5-18

19 5.4 State Reduction in Incompletely Specified ircuits The minimisation of state tables containing don't care entries in the next state and/or in the output column requires special consideration. Here we will work on examples which will illustrate the problem. For a systematic state reduction algorithm further reading is necessary 1. In the following 1. state table four don't-cares appear. Once these entries are specified the known state reduction techniques can be applied to determine equivalent states. Suppose we chose assignments as described by the 2. state table then we have made A equvilant to B and E equivalent to F. 1. State Table S S + /Y X=0 X=1 A B E F B/ F/0 /0 / E/0 E/ /0 A/1 / /1 2. State Table S S + /Y X=0 X=1 A B E F F/0 /0 /0 E/0 E/0 /0 A/1 /1 /1 3. State Table S S + /Y X=0 X=1 (B) A (F)E A/1 E/0 A/1 /0 E/0 /0 A/1 /1 B. Schwarz 5-19

20 The next choice of don't-care substitution is less obvious. They are specified as zeros for present states A and E and specified as ones for states B and F. As a result states A, and E are equivalent, as are states B, and F. S A B E F State Table S + /Y X=0 X=1 B/... F/0 /0 /... E/0 E/... /0 A/1 /... /1 Partition Next States P 1 NS for X = 0 NS for X = 1 P 2 NS for X = 0 NS for X = 1 P 3 NS for X = 0 Partition Blocks Reduced State Table S S + /Y X=0 X=1 S1 S2 S2/0 S2/1 S1/0 S1/0 NS for X = 1 State equivalence by partitioning B. Schwarz 5-20

21 Minimisation of an incompletely specified state table with implication table. State Table S A B E S + / Y2 Y1 Y0 I1, I0 0, 0 0, 1 1, 0 1, 1 A / 000 B / 1xx / 01x A / 000 A / 000 E / 001 / 01x / 01x X / xxx E / 001 B / 1xx B / 1xx / 000 / 000 X / xxx X / xxx X / xxx X / xxx X / xxx X / xxx B E A B 1 G. e Micheli: Synthesis and Optimization of igital ircuits. McGraw-Hill 1994 B. Schwarz 5-21