Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits

Transcription

1 Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines Timing of Sequential Logic Parallelism Chapter 3 <> Chapter 3 <2> Introduction Outputs of sequential logic depend on current and prior input values it has memory. Some definitions: State: all the information about a circuit necessary to explain its future behavior Latches and flip flops: state elements that store one bit of state Synchronous sequential circuits: combinational logic followed by a bank of flip flops Sequential Circuits Give sequence to events Have memory (short-term) Use feedback from output to input to store information Chapter 3 <3> Chapter 3 <4>

2 State Elements The state of a circuit influences its future behavior State elements store state Bistable circuit S Latch Latch Flip-flop Bistable Circuit Fundamental building block of other state elements Two outputs:, No inputs I2 I I I2 Chapter 3 <5> Chapter 3 <6> Bistable Circuit Analysis S (Set/eset) Latch Consider the two possible cases: = : then =, = (consistent) I S Latch N = : then =, = (consistent) I2 I S N2 Consider the four possible cases: Stores bit of state in the state variable, (or ) But there are no inputs to control the state I2 S =, = S =, = S =, = S =, = Chapter 3 <7> Chapter 3 <8> 2

3 S Latch Analysis S Latch Analysis S =, = : then = and = S N N2 S =, = : then = prev S prev = prev = N N2 N N2 S S =, = : then = and = S N N2 S =, = : then =, = S N N2 Chapter 3 <9> Chapter 3 <> S Latch Analysis S Latch Symbol S =, = : then = prev Memory! S =, = : then =, = Invalid State NOT S prev = prev = S N N2 N N2 Chapter 3 <> S N N2 S stands for Set/eset Latch Stores one bit of state () Control what value is being stored with S, inputs S Latch Set: Make the output Symbol (S =, =, = ) eset: Make the output (S =, =, = ) S Chapter 3 <2> 3

4 Latch Latch Internal Circuit Two inputs:, : controls when the output changes (the data input): controls what the output changes to Function When =, passes through to (transparent) When =, holds its previous value (opaque) Avoids invalid case when NOT Latch Symbol X S S S Chapter 3 <3> Chapter 3 <4> Latch Internal Circuit Flip Flop X X S S S prev prev Inputs:, Function Samples on rising edge of When rises from to, passes through to Otherwise, holds its previous value changes only on rising edge of Called edge-triggered Activated on the clock edge Flip-Flop Symbols Chapter 3 <5> Chapter 3 <6> 4

5 Flip Flop Internal Circuit Latch vs. Flip Flop Two back-to-back latches (L and L2) controlled by complementary clocks When = L is transparent L2 is opaque passes through to N N When = L2 is transparent L is opaque N passes through to L L2 Thus, on the edge of the clock (when rises from ) passes through to (latch) (flop) Chapter 3 <7> Chapter 3 <8> Latch vs. Flip Flop egisters 3: 4 4 3: (latch) 2 2 (flop) 3 3 Chapter 3 <9> Chapter 3 <2> 5

6 Enabled Flip Flops Inputs:,, EN The enable input (EN) controls when new data () is stored Function EN = : passes through to on the clock edge EN = : the flip-flop retains its previous state EN Internal Circuit Symbol EN esettable Flip Flops Inputs:,, eset Function: eset = : is forced to eset = : flip-flop behaves as ordinary flip-flop eset Symbols r Chapter 3 <2> Chapter 3 <22> esettable Flip Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when eset = Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? esettable Flip Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when eset = Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? Internal Circuit eset Chapter 3 <23> Chapter 3 <24> 6

7 Settable Flip Flops Sequential Logic Inputs:,, Set Function: Set = : is set to Set = : the flip-flop behaves as ordinary flip-flop Symbols Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z X Y Z time (ns) Set s Chapter 3 <25> Chapter 3 <26> Sequential Logic Synchronous Sequential Logic esign Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z No inputs and -3 outputs Astable circuit, oscillates Period depends on inverter delay It has a cyclic path: output fed back to input X Y Z time (ns) Breaks cyclic paths by inserting registers egisters contain state of the system State changes at clock edge: system synchronized to the clock ules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite State Machines (FSMs) Pipelines Chapter 3 <27> Chapter 3 <28> 7

8 Finite State Machine (FSM) Finite State Machines (FSMs) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs Next State Logic C L Next State Output Logic C L Next State Chapter 3 <29> S S Outputs Current State Next state determined by current state and inputs Two types of finite state machines differ in output logic: Moore FSM: outputs depend only on current state Mealy FSM: outputs depend on current state and inputs M inputs M inputs next state logic next state logic Moore FSM next k k state state Mealy FSM next k k state state output logic output logic N outputs N outputs Chapter 3 <3> FSM Example FSM Black Box Traffic light controller Traffic sensors:, (TUE when there s traffic) Lights:, Academic Labs Bravado Blvd. ining Hall Fields Ave. orms Inputs:, eset,, Outputs:, Traffic Light Controller eset Chapter 3 <3> Chapter 3 <32> 8

9 FSM State Transition iagram FSM State Transition iagram Moore FSM: outputs labeled in each state States: Circles eset Transitions: Arcs S : green Moore FSM: outputs labeled in each state States: Circles T eset A TA Transitions: Arcs S : green S : yellow S3 : yellow S2 : green Chapter 3 <33> Chapter 3 <34> FSM State Transition Table FSM State Transition Table Current State Next State Inputs S S' S X S X S X X S2 X S2 X S3 X X Current State Inputs Next State S S' S X S S X S S X X S2 S2 X S3 S2 X S2 S3 X X S Chapter 3 <35> Chapter 3 <36> 9

10 FSM Encoded State Transition Table FSM Encoded State Transition Table Current State Inputs Next State Current State Inputs Next State S S S' S' X X X X X X X X State Encoding S S S2 S3 S S S' S' X X X X X X X X State Encoding S S S2 S3 S' = S S S' = S S + S S Chapter 3 <37> Chapter 3 <38> FSM Output Table FSM Output Table Current State Outputs S S Output Encoding green yellow red Current State Outputs S S Output Encoding green yellow red = S = S S = S = S S Chapter 3 <39> Chapter 3 <4>

11 FSM Schematic: State egister FSM Schematic: Next State Logic S' S S' S S' r eset S state register S S S' r eset S inputs next state logic state register Chapter 3 <4> Chapter 3 <42> FSM Schematic: Output Logic FSM Timing iagram Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle S' S eset S' :?? S () S () S2 () S3 () S () S () S' r eset S S : : :?????? S () Green () ed () S () S2 () S3 () S () Yellow () ed () Green () Green () Yellow () ed () S S t (sec) eset TA inputs next state logic state register output logic outputs S : green S : yellow S3 : yellow S2 : green Chapter 3 <43> Chapter 3 <44>

12 FSM State Encoding Binary encoding: i.e., for four states,,,, One-hot encoding One state bit per state Only one state bit HIGH at once i.e., for 4 states,,,, equires more flip-flops Often next state and output logic is simpler Moore vs. Mealy FSM Alyssa P. Hacker has a snail that crawls down a paper tape with s and s on it. The snail smiles whenever the last two digits it has crawled over are. esign Moore and Mealy FSMs of the snail s brain. Chapter 3 <45> Chapter 3 <46> State Transition iagrams Moore FSM State Transition Table Moore FSM eset Current State Inputs Next State State Encoding S Mealy FSM eset / S S2 S S A S' S' S S S2 S / / S / Mealy FSM: arcs indicate input/output Chapter 3 <47> Chapter 3 <48> 2

13 Moore FSM State Transition Table Moore FSM Output Table Current State Inputs Next State S S A S' S' State Encoding S S S2 Current State Output S S Y Y = S S = S A S = A Chapter 3 <49> Chapter 3 <5> Moore FSM Output Table Mealy FSM State Transition & Output Table Current State Output S S Y Current State Input Next State Output S A S' Y State Encoding S S Y = S Chapter 3 <5> Chapter 3 <52> 3

14 Mealy FSM State Transition & Output Table Moore FSM Schematic Current State Input Next State Output A S A S' Y State Encoding S S' S Y S S' S r eset Chapter 3 <53> Chapter 3 <54> Mealy FSM Schematic Moore & Mealy Timing iagram A Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle Cycle eset S' S Y A Moore Machine S?? S S S2 S S2 S S S2 S Y r eset Mealy Machine S?? S S S S S S S Y Chapter 3 <55> Chapter 3 <56> 4

15 Factoring State Machines Parade FSM Break complex FSMs into smaller interacting FSMs Example: Modify traffic light controller to have Parade Mode. Two more inputs: P, When P =, enter Parade Mode & Bravado Blvd light stays green When =, leave Parade Mode Unfactored FSM Factored FSM P P Controller FSM Mode FSM M Lights FSM Controller FSM Chapter 3 <57> Chapter 3 <58> Unfactored FSM Factored FSM P eset S : green P P P S3 : yellow P P P P S : yellow P S2 : green P P S4 : green S7 : yellow S5 : yellow S6 : green eset S : green S3 : yellow TA M M + Lights FSM S : yellow S2 : green eset S M: P P Mode FSM S M: Chapter 3 <59> Chapter 3 <6> 5

16 FSM esign Procedure Identify inputs and outputs Sketch state transition diagram Write state transition table Select state encodings For Moore machine: ewrite state transition table with state encodings Write output table For a Mealy machine: ewrite combined state transition and output table with state encodings Write Boolean equations for next state and output logic Sketch the circuit schematic Chapter 3 <6> Timing Flip-flop samples at clock edge must be stable when sampled Similar to a photograph, must be stable around clock edge If not, metastability can occur Chapter 3 <62> Input Timing Constraints Output Timing Constraints Setup time: t setup = time before clock edge data must be stable (i.e. not changing) Hold time: t hold = time after clock edge data must be stable Aperture time: t a = time around clock edge data must be stable (t a = t setup + t hold ) Propagation delay: t pcq = time after clock edge that the output is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that might be unstable (i.e., start changing) t ccq t pcq t setup t hold t a Chapter 3 <63> Chapter 3 <64> 6

17 ynamic iscipline Synchronous sequential circuit inputs must be stable during aperture (setup and hold) time around clock edge Specifically, inputs must be stable at least t setup before the clock edge at least until t hold after the clock edge ynamic iscipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements (a) C L T c 2 2 Chapter 3 <65> 2 (b) Chapter 3 <66> Setup Time Constraint epends on the maximum delay from register through combinational logic to 2 The input to register 2 must be stable at least t setup before clock edge 2 C L T c t pcq t pd t setup 2 2 T c Setup Time Constraint epends on the maximum delay from register through combinational logic to 2 The input to register 2 must be stable at least t setup before clock edge 2 C L T c t pcq t pd t setup 2 2 T c t pcq + t pd + t setup t pd Chapter 3 <67> Chapter 3 <68> 7

18 Setup Time Constraint epends on the maximum delay from register through combinational logic to 2 The input to register 2 must be stable at least t setup before clock edge 2 C L T c t pcq t pd t setup 2 2 T c t pcq + t pd + t setup t pd T c (t pcq + t setup ) Chapter 3 <69> Hold Time Constraint epends on the minimum delay from register through the combinational logic to 2 The input to register 2 must be stable for at least t hold after the clock edge 2 t ccq t cd t hold C L 2 2 t hold < Chapter 3 <7> Hold Time Constraint epends on the minimum delay from register through the combinational logic to 2 The input to register 2 must be stable for at least t hold after the clock edge 2 C L 2 2 t hold < t ccq + t cd t cd > Hold Time Constraint epends on the minimum delay from register through the combinational logic to 2 The input to register 2 must be stable for at least t hold after the clock edge 2 C L 2 2 t hold < t ccq + t cd t cd > t hold - t ccq t ccq t cd t ccq t cd t hold t hold Chapter 3 <7> Chapter 3 <72> 8

19 Timing Analysis Timing Analysis A Timing Characteristics t ccq = 3 ps A Timing Characteristics t ccq = 3 ps B C X' X t pcq = 5 ps t setup = 6 ps t hold = 7 ps B C X' X t pcq = 5 ps t setup = 6 ps t hold = 7 ps t pd = Y' Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 5 ps Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = t cd = 25 ps Setup time constraint: Hold time constraint: Setup time constraint: Hold time constraint: T c t ccq + t cd > t hold? T c ( ) ps = 25 ps t ccq + t cd > t hold? f c = f c = /T c = 4.65 GHz (3 + 25) ps > 7 ps? No! Chapter 3 <73> Chapter 3 <74> Timing Analysis Timing Analysis Add buffers to the short paths: Timing Characteristics Add buffers to the short paths: Timing Characteristics A t ccq t pcq = 3 ps = 5 ps A t ccq t pcq = 3 ps = 5 ps B t setup = 6 ps B t setup = 6 ps C X' X t hold = 7 ps C X' X t hold = 7 ps t pd = Y' Y per gate t pd t cd = 35 ps = 25 ps t pd = 3 x 35 ps = 5 ps Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = t cd = 2 x 25 ps = 5 ps Setup time constraint: Hold time constraint: Setup time constraint: Hold time constraint: T c t ccq + t cd > t hold? T c ( ) ps = 25 ps t ccq + t cd > t hold? f c = f c = /T c = 4.65 GHz (3 + 5) ps > 7 ps? Yes! Chapter 3 <75> Chapter 3 <76> 9

20 Clock Skew The clock doesn t arrive at all registers at same time Skew: difference between two clock edges Perform worst case analysis to guarantee dynamic discipline is not violated for any register many registers in a system! t skew delay C L Setup Time Constraint with Skew In the worst case, 2 is earlier than C 2 L T c 2 T c 2 t pcq t pd t setup t skew Chapter 3 <77> Chapter 3 <78> Setup Time Constraint with Skew In the worst case, 2 is earlier than 2 C 2 L Setup Time Constraint with Skew In the worst case, 2 is earlier than 2 C 2 L T c 2 T c 2 2 T c t pcq + t pd + t setup + t skew t pd 2 T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) 2 2 t pcq t pd t setup t skew t pcq t pd t setup t skew Chapter 3 <79> Chapter 3 <8> 2

21 Hold Time Constraint with Skew In the worst case, 2 is later than 2 C 2 L Hold Time Constraint with Skew In the worst case, 2 is later than 2 C 2 L t ccq + t cd > 2 t ccq + t cd > t hold + t skew t cd > 2 2 t ccq t cd t ccq t cd t skew t hold t skew t hold Chapter 3 <8> Chapter 3 <82> Hold Time Constraint with Skew Violating the ynamic iscipline In the worst case, 2 is later than 2 C 2 L 2 2 t ccq + t cd > t hold + t skew Asynchronous (for example, user) inputs might violate the dynamic discipline button t setup t hold t aperture Case I 2 t cd > t hold + t skew t ccq Case II t ccq t cd t skew t hold??? Case III Chapter 3 <83> Chapter 3 <84> 2

22 Metastability Bistable devices: two stable states, and a metastable state between them Flip-flop: two stable states ( and ) and one metastable state If flip-flop lands in metastable state, could stay there for an undetermined amount of time stable metastable stable Flip Flop Internals Flip-flop has feedback: if is somewhere between and, cross-coupled gates drive output to either rail ( or ) S N N2 Metastable signal: if it hasn t resolved to or If flip-flop input changes at random time, probability that output is metastable after waiting some time, t: P(t res > t) = (T /T c ) e -t/τ t res : time to resolve to or T, τ : properties of the circuit Chapter 3 <85> Chapter 3 <86> Metastability Intuitively: T /T c : probability input changes at a bad time (during aperture) P(t res > t) = (T /T c ) e -t/τ τ: time constant for how fast flip-flop moves away from metastability P(t res > t) = (T /T c ) e -t/τ Synchronizers Asynchronous inputs are inevitable (user interfaces, systems with different clocks interacting, etc.) Synchronizer goal: make the probability of failure (the output still being metastable) low Synchronizer cannot make the probability of failure In short, if flip-flop samples metastable input, if you wait long enough (t), the output will have resolved to or with high probability. SYNC Chapter 3 <87> Chapter 3 <88> 22

23 Synchronizer Internals Synchronizer: built with two back-to-back flip-flops Suppose is transitioning when sampled by F Internal signal 2 has (T c - t setup ) time to resolve to or 2 F T c F2 Synchronizer Probability of Failure For each sample, probability of failure is: P(failure) = (T /T c ) e -(T c - t setup )/τ F 2 T c F2 2 metastable 2 metastable t res t setup t pcq Chapter 3 <89> t res t setup t pcq Chapter 3 <9> Synchronizer Mean Time Between Failures If asynchronous input changes once per second, probability of failure per second is P(failure). If input changes N times per second, probability of failure per second is: P(failure)/second = (NT /T c ) e -(T c - t setup )/τ Synchronizer fails, on average, /[P(failure)/second] Called mean time between failures, MTBF: Example Synchronizer F 2 Suppose: T c = /5 MHz = 2 ns τ = 2 ps T = 5 ps t setup = ps N = events per second What is the probability of failure? MTBF? F2 MTBF = /[P(failure)/second] = (T c /NT ) e (T c -t setup )/τ Chapter 3 <9> Chapter 3 <92> 23

24 Example Synchronizer F 2 Suppose: T c = /5 MHz = 2 ns τ = 2 ps T = 5 ps t setup = ps N = events per second What is the probability of failure? MTBF? P(failure) = (5 ps/2 ns) e-(.9 ns)/2 ps = P(failure)/second = (5.6-6 ) = / second MTBF = /[P(failure)/second] 5 hours F2 Parallelism Two types of parallelism: Spatial parallelism duplicate hardware performs multiple tasks at once Temporal parallelism task is broken into multiple stages also called pipelining for example, an assembly line Chapter 3 <93> Chapter 3 <94> Parallelism efinitions Parallelism Example Token: Group of inputs processed to produce group of outputs Latency: Time for one token to pass from start to end Throughput: Number of tokens produced per unit time Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 5 minutes to bake What is the latency and throughput without parallelism? Parallelism increases throughput Chapter 3 <95> Chapter 3 <96> 24

25 Parallelism Example Parallelism Example Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 5 minutes to bake What is the latency and throughput without parallelism? Latency = = 2 minutes = /3 hour Throughput = tray/ /3 hour = 3 trays/hour What is the latency and throughput if Ben uses parallelism? Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own oven Temporal parallelism: two stages: rolling and baking He uses two trays While first batch is baking, he rolls the second batch, etc. Chapter 3 <97> Chapter 3 <98> Spatial Parallelism Spatial Parallelism Latency: time to first tray Latency: time to first tray Spatial Parallelism Tray Tray 2 Tray 3 Tray 4 Ben Ben Alyssa Alyssa Ben 2 Ben 2 Alyssa 2 Alyssa 2 Time oll Bake Legend Spatial Parallelism Tray Tray 2 Tray 3 Tray 4 Ben Ben Alyssa Alyssa Ben 2 Ben 2 Alyssa 2 Alyssa 2 Time oll Bake Legend Latency =? Throughput =? Latency = = 2 minutes = /3 hour Throughput = 2 trays/ /3 hour = 6 trays/hour Chapter 3 <99> Chapter 3 <> 25

26 Temporal Parallelism Temporal Parallelism Latency: time to first tray Latency: time to first tray Temporal Parallelism Tray Tray 2 Tray 3 Ben Ben Ben 2 Ben 2 Ben 3 Ben 3 Time Temporal Parallelism Tray Tray 2 Tray 3 Ben Ben Ben 2 Ben 2 Ben 3 Ben 3 Time Latency =? Throughput =? Latency = = 2 minutes = /3 hour Throughput = trays/ /4 hour = 4 trays/hour Using both techniques, the throughput would be 8 trays/hour Chapter 3 <> Chapter 3 <2> 26