Overview of Chapter 4

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1 Overview of hapter 4 Types of Sequential ircuits Storage Elements Latches Flip-Flops Sequential ircuit Analysis State Tables State Diagrams Sequential ircuit Design Specification Assignment of State odes Implementation HDL Representation 1

2 Sequential ircuits A Sequential circuit contains: ombinational Logic: Inputs Storage Elements State Implements a multiple-output switching function Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State, are signals from storage elements. The remaining outputs, Next State are inputs to storage elements. Storage elements: Latches or Flip- Flops ombinational Logic Next State Outputs 2

3 Sequential ircuits ombinatorial Logic Next state function: Next State = f(inputs, State) ombinatorial Logic Outputs = g(inputs, State) Alternate output function (Moore): Outputs = h(state) Type of output function heavily influences the design 3

4 Types of Sequential ircuits Depends on time at which inputs are observed by storage elements and state of storage elements change Synchronous Behavior defined from knowledge of its signals at discrete instances of time Storage elements affected by inputs and can change state only in relation to a timing signal (clock pulses from a clock) Asynchronous Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change If clock just regarded as another input, all circuits are asynchronous! Nevertheless, the synchronous abstraction makes complex designs tractable! 4

5 Discrete Event Simulation In order to understand the time behavior of a Sequential ircuit we use discrete event simulation Rules: Gates modeled by an ideal (instantaneous) function and a fixed gate delay Any change in input values is evaluated to see if it causes a change in output value hanges in output values are scheduled for after the fixed gate delay At the time for a scheduled output change, the output value is changed along with any inputs connected to it 5

6 Simulated NAND Gate Example: A 2-Input NAND gate with a 5 ns. delay: A B F(Instantaneous) DELAY 5 ns. F Assume A and B have been 1 for a long time At time t=0, A changes to a 0 at t=8 ns, back to 1. t(ns) A B F(I) F omment A=B=1 for a long time F(I) changes to F changes to 1 after a 5 ns delay F(Instantaneous) changes to F changes to 0 after a 5 ns delay 6

7 Gate Models Suppose we represent gates with delay n ns as follows: n n n 7

8 Storing State onsider a simple 2-input multiplexer: With function: Y = A for S = 1 Y = B for S = 0 A S B Y A B S Y What would happen if we connect output signal Y to input signal A? 8

9 Storing State (ontinued) The circuit becomes: With function: Y = B for S = 1, and Y(t) dependent on Y(t 2) for S = 0 S B Y S B Y The simple combinational circuit has now become a sequential circuit because its output is a function of a time sequence of input signals! 9

10 Storing State (ontinued) Simulation example as input signals change with time. hanges occur every 100 ns, so that the 0.2 ns delays are negligible. B S Y omment Y = B when S = Now Y remembers B for S = No change in Y Y = B when S = Y remembers B Even when B changes Y represents the state of the circuit, not just an output. 10

11 Storing State (ontinued) Suppose we place an inverter in the feedback path. The following behavior results: The circuit is said to be unstable. For S = 0 it is an oscillator! S B B S Y omment Y = B when S = Now Y "remembers" B Y at 0.2 ns later Y at 0.2 ns later Y at 0.2 ns later 0 Y 11

12 Basic (NOR) S R Latch ross-coupling two NOR gates gives the S R Latch: Which has the time sequence behavior: R (reset) S (set) R S ' omment 0 0?? We don't know "Set" to Now "remembers" "Reset" to Now "remembers" Both go low 0 0?? INSTABILITY ' 12

13 Basic (NAND) S R Latch ross-oupling two NAND gates gives the S - R Latch: S (set) R (reset) Which has the time sequence behavior: R S ' omment 1 1?? We don't know "Set" to Now "remembers" "Reset" to Now "remembers" Both go high 1 1?? INSTABILITY ' 13

14 locked S - R Latch Adding two NAND gates to the basic S - R NAND Latch, we arrive at the locked S R Latch: S R This has a time sequence behavior similar to the Basic S - R Latch except that: S and R are now active high signals (i.e. -- a "1" signal on S sets to 1) and The S and R inputs are only observed when the line is high. has the meaning "lock" or "lock Pulse". ' 14

15 locked S - R Latch (ontinued) The locked S-R Latch can be described by a table: S R The table describes what happens after the clock [at time (t+1)] based on: current inputs (S,R) and current state (t). ' (t) S R (t+1) omment No change lear Set 0 1 1??? Indeterminate No change lear Set 1 1 1??? Indeterminate 15

16 haracteristic Equation for S - R Latch We can describe the behavior of output at time (t+1) (immediately after one clock pulse) using a K-Map: X S X We can see that: (t+1) = S + R' given that (both are not high at once): S R = 0 The locked S R Latch has the symbol: R S R ' 16

17 D Latch Adding an inverter to the S-R Latch, gives the D Latch: Note that there are no "Indeterminate" states! D ' D (t+1) omment No change Set lear Set The graphic symbol for a D Latch is: D ' 17

18 Latch and Flip-Flop Triggering So far, the latches we have talked about are "clocked" with an input pulse. Here are some possible wave forms: Positive lock Pulse lock Period Positive edge lock Period Negative lock Puls e w Negative Edge w Positive lock Pulse Negative lock Pulse W = Pulse Width lock Period = Time between referenced edges. Reference level is generally 50%. Rise and Fall times may be important as well. 18

19 System Level locking onsider a system comprised of ranks of latches or flip-flops connected by logic: If the lock Period is TOO SHORT, some data changes will not propagate through the network. If the lock Pulse Width is TOO LONG, some data will propagate through the second rank of latches! D D D D D LOK ' ' ' ' ' D D D D D LOK ' ' ' ' ' 19

20 Master-Slave Flip-Flop One way to solve the locking Problem is with a master-slave organization: R R R S S ' S ' ' The complement of the clock is used to change the outputs. Now outputs change on ' only. Problem: One's catching in Master. Problem: Instability in Master. Another solution: Use D-FF's or Edge Triggering 20

21 Edge Triggered Flip-Flops Edge triggered Flip-Flops are sensitive to a small window for data changes around the time of a clock edge. Setup Time: The time required for input data to be stable before the clock edge. Hold Time: The time data must remain stable after the clock edge. D D T J ' ' K ' Positive Edge Triggered FFs T J ' ' K ' Negative Edge Triggered FFs 21

22 Flip-Flop haracteristic Tables The haracteristic Tables: Show current inputs. Show current state implicitly. Predict flip-flop state AFTER LOKING. locking conditions are: Positive level triggered. Negative level triggered. Positive edge triggered. Negative edge triggered. NOTE: Proper clocking or flip-flop operation may be subject to conditions such as: Set-up and hold times are met. Simultaneous SR changes disallowed. 22

23 haracteristic Tables J K (t+1) omment 0 0 (t) No change lear Set 1 1 '(t) omplement S R (t+1) omment 0 0 (t) No change lear Set 1 1??? Indeterminate T (t+1) omment 0 (t) No change 1 '(t) omplement D (t+1) omment 0 0 lear 1 1 Set 23

24 J-K Master Slave Flip Flop Two SR Latches driven by inverted clocks form a master-slave configuration. Input logic forms the JK logic transition: Set (master) = J s' Reset (master) = K s J K P Mas te r S R Slave S R m s Master Set is possible if the slave s is currently "0" any time the clock P is high! Master Reset is possible if the slave s is currently "1" any time the clock P is high! This is referred to as One's atching. 24

25 Master Slave Symbols Master-Slave Flip Flops are denoted by a line near the outputs. This highlights the fact that the slave changes AFTER the master clocking condition is deasserted. SR JK SR JK S J S J R ' K ' R ' K ' Po s itive Puls e Trig g ere d Mas ter/slave FFs Negative Pulse Triggered Mas ter/slave FFs 25

26 Flip-Flop onventions A Bubble near a clock input denotes an active low assertion. A Triangle near the clock input denotes edge sensitive. B A K A B A L-Shaped Line near the output denotes Master/Slave. ' K 26

27 Propagation Delay Logic gate, Latch and Flip-Flop timing parameters: TPLH: Propagation time low-to-high -- the time required for an output to transition from a low logic level to a high logic level from an input event (usually clock). TPHL: Propagation time high-to-low -- the time required for an output to transition from a high logic level to a low logic level from an input event (usually clock). lock Skew: Difference in clock arrival times at different flip-flops. Tsu Set-up time: Time data must be stable at FFs before the clock. Minimum clock period is set by: MAX(TPHL,TPLH) + LogicDelay + Tsu Hold Time and lock Skew constrain the minimum logic plus flipflop delay. 27

28 alculating lock Frequency Given the network below, assume signal A is changing from "1" to "0": lock Period = t PHL (Flip-Flop) +3*t PHL (Logic) + t su (Flip-Flop) Frequency = 1/(lock Period) LOK LOK A B D D ' tphl (Logic ) A B D lock Period tphl (Flip-Flop) tphl (Log ic ) ts u (Flip-Flop) tphl (Log ic ) LOK D ' 28

29 alculating lock Frequency ontd Given the network below, assume signal A is changing from "0" to "1": D ' LOK A B D D ' LOK lock Period = t PLH (Flip-Flop) +3*t PLH (Logic) + t su (Flip-Flop Frequency = 1/(lock Period) We ususally pick MAX(t PHL, T PLH ). LOK A B D lock Period tplh (Flip-Flo p) tplh (Logic) tpl H(Logic) tplh (Logic) tsu (Flip-Flop) 29

30 Sequential ircuit Analysis General Model urrent State at time (t) is stored in an array of flip-flops. Inputs Storage Elements Next State at time (t+1) is a State LK ombinati onal Logic Next State Boolean function of current state and inputs. Outputs at time (t) are a Boolean function of current state (t) and (sometimes) current inputs (t). Outputs 30

31 Example (from Fig. 4-18) Input: x(t) Output: y(t) x D A State: A(t), B(t) ' A What is the Output Function? What is the Next State Function? P D ' B y 31

32 Example (Fig. 4-18) (ontinued) Boolean Equations for the functions: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A(t)x(t) x Next State D ' A A' y(t) = x(t)(b(t) + A(t)) D B P ' y Output 32

33 Example (Fig. 4-18) (ontinued) Where in time are inputs, outputs and states defined? Functional Simulation - Fig Mano & Kime ns 106ns 159ns 212ns 265ns 318ns 371ns 424ns l RESET... l LOK... l l l l l l X... NA... NB... A... B... Y l t t+1 t+2 t+3 33

34 State Table haracteristics State table a multiple variable function table with the following four sections: Present State the values of the state variables for each allowed state. Input the input combinations allowed. Next-state the value of the state at time (t+1) based on the present state and the input. Output the value of the output as a function of the present state and (sometimes) the input. From the viewpoint of a truth table: the inputs are Input, Present State and the outputs are Output, Next State 34

35 Example: State Table (Fig. 4-18) The STATE TABLE can be filled in using the next state and output equations: A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A (t)x(t) y(t) = x (t)(b(t) + A(t)) Present State Input Next State Output A(t) B(t) x(t) A(t+1) B(t+1) y(t)

36 Alternate State Table 2-dimensional table that matches well to a K-map. Present state rows and input columns in Gray code order. A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A (t)x(t) y(t) = x (t)(b(t) + A(t)) Present State Next State x(t)=0 x(t)=1 Output x(t)=0 x(t)=1 A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)

37 State Diagram haracteristics The Boolean state variables are a vector of n bits. Not all 2 n states are necessarily used! Similarly not all input and output combinations are used. The state variables may need to be initialize to a valid, appropriate initial state. Examples: A system with 10 states requires a minimum of 4 bits (3 bits gives only 8 symbols). BD coded inputs can have 16 combinations, only 10 of which have meaning. 37

38 State Diagrams The sequential circuit function can be represented in graphical form as a state diagram with the following components: A circle with the state name in it for each state A directed arc from the Present State to the Next State for each state transition A label on each directed arc with the Input value which causes the state transition, and A label: On each circle with the output value produced, or On each directed arc with the output value produced. 38

39 State Diagrams Label form: On circle with output included: state/output Moore type output depends only on state On directed arc with the output included: input/output Mealy type output depends on state and input 39

40 State Diagram Example Which type? Gets confusing as circuit grows in size. For small circuits, usually easier to understand than the state table. x=0/y=0 x=1/y=0 A B 0 0 x=0/y=1 x=0/y=1 x=0/y= x=1/y=0 Try drawing state diagram for mod 4 counter and toggle (T) flip-flop 1 0 x=1/y=0 x=1/y=0 40

41 Flip-Flop Input Functions The D-Flip-Flop easy to analyze since it has only one input. Other FFs such as the JK and SR have two inputs. onvention used in text: First Letters designate the FF input function. Second Letters (or subscript) designate the state variable. Example with Two JKFFs: J A = B K A = B x J B = x K B = A x + A x Example 4-18 with Two DFFs: D A = A x + B x D B = A x y = (A + B) x 41

42 Analysis with Other Flip-Flops With a D Flip-Flop: Next state obtained directly from the flip-flop input equation for D i With a JK, T or SR Flip-Flop: Obtain the values for each flip-flop input in terms of present state and input values Use the corresponding flip-flop characteristic table from Table 4-1 to determine the next state value of the flip-flop 42

43 haracteristic Tables J K (t+1) omment 0 0 (t) No change lear Set 1 1 (t) omplement S R (t+1) omment 0 0 (t) No change lear Set 1 1? Indeterminate T (t+1) omment 0 (t) No change 1 (t) omplement D (t+1) omment 0 0 lear 1 1 Set 43

44 JK Flip-Flop ircuit Analysis Step 1: Write the Boolean expression for each flip-flop input. For flip-flop A: J A = K A = For flip-flop B: J B = K B = x P J A K A J B K B J K J K ' ' A B 44

45 JK Flip-Flop Analysis (ont.) Step 2: Using the diagram or equations, fill in the flip-flop inputs. J A = B x K A = B J B = x K B = A x x JA KA JB P KB J K J K ' ' A B Present State Input Next State Flip-Flop Inputs A B x A B J A K A J B K B

46 JK Flip-Flop Analysis (ont.) Step 3: By using JK haracteristic Table, the J and K inputs and the present state from the table, fill in the next state in the table for each flip flop. A (t) = 0; J A =0; K A = 0; Implies A (t+1) = 0 (No hange) B (t) = 0; J B =1; K B = 0; Implies B (t+1) = 1 (Set ) J K (t+1) omment 0 0 (t) No change lear Set 1 1 (t) omp. Present State Input Next State Flip-Flop Inputs A B x A B J A K A J B K B

47 JK Flip-Flop Analysis (ont.) The result of completion of Step 3: Present State Input Next State Flip-Flop Inputs A B x A B J A K A J B K B For convenience, discard the flip-flop input columns What is the output function? 47

48 JK Flip-Flop Analysis (ont.) Step 4: From the diagrams or equations, place the output values in the table: Present State Input Next State A B x A B Output A B

49 Additional oncepts haracteristic Equations Moore and Mealy Models Diagram Examples Table Examples 49

50 haracteristic Equations an be used instead of characteristic tables for transforming flip-flop inputs to next state information J K (t+1) omment 0 0 (t) No change lear Set 1 1 (t) omplement (t+1) = J (t) + K(t) T (t+1) omment 0 (t) No change 1 (t) omplement S R (t+1) omment 0 0 (t) No change lear Set 1 1? Indeterminate (t+1) = S + R (t) D (t+1) omment 0 0 lear 1 1 Set (t+1) = T (t) (t+1) = D 50

51 Moore and Mealy Models Sequential ircuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function ONLY of states Usually specified on the states. Mealy Model Named after G. Mealy Outputs are a function of inputs AND states Usually specified on the state transition arcs. 51

52 Moore and Mealy Example Diagrams Mealy Model State Diagram maps inputs and state to outputs x=0/y=0 x=1/y=0 0 1 Moore Model State Diagram maps states to outputs x=0 x=0/y=0 x=1/y=1 0/0 x=0 x=1 x=0 x=1 1/0 x=1 2/1 52

53 Moore and Mealy Example Tables Mealy Model State Table maps inputs and state to outputs Present State Next State x=0 x=1 Output x=0 x= Moore Model State Table maps state to outputs Present State Next State x=0 x= Output 53

Chapter 4 Part 2 Sequential Circuits

University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 4 Part 2 Sequential Circuits Originals by: Charles R. Kime and Tom Kamisnski