EEE2135 Digital Logic Design

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1 EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과

2 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the current inputs and present state determined by the past input history b. State register required to record the past inputs 2) Sequential Circuit Structure a. Moore Model - POs independent of PIs, depend on PS b. Mealy Model - POs depend on PIs and PS 3) State Behavior a. State (Transition) Table I. Behavioral description of a sequential circuit requires to list all possible input/output sequences (tt impractical) II. State table to represent the behavior of a sequential circuit ex. State table of a serial adder b. State (Transition) Diagram I. Representation of a state table in graphical form Vertex : state, Arc : state transition, Label : x/z (inputs/outputs) II. Reset signal to represent the initial state

4 2. Analysis of a Sequential Circuit 1) Analysis Procedure a. Derive Boolean equations from logics at each input of FFs b. Construct transition table c. State table can be obtained by replacing the bit patterns by symbols d. Circuit behavior can be known 2) Behavior Extraction a. Combinational function identification b. State/State transition identification c. Formal behavioral specification

5 3. Timing control and clock 1) Clocks a. Inputs/outputs can change at any time w/o clocking I. to determine precisely when states change and II. to minimize sensitivities to glitches b. to control the overall operations 2) Delays in sequential circuits a. Propagation delay b. Longest path constraint c. Shortest path constraint - logic signals travel too fast around main feedback loop d. Clock signal design 3) Clock skew a. Clock signal spreads over system different delays for different clock signals applied to f/f s b. Max. allowed clock skew max. time difference which can occur between almost simultaneous click transitions which f/f s will treat as being simultaneous

6 F/F Timing t SU t SU t h Clk t ff t CC D Inputs to f/f stabilized f/f outputs stabilized t P, clk > t SU + t ff + t CC + margin (15~25%) f clk < 1/(t SU + t ff + t CC + margin (15~25%)) 5

7 4. Sequential Circuit Synthesis 1) Design Process a. State behavior specification I. Construct state diagram which precisely captures i/o behavior II. Internal states and transitions are identified b. State assignment : NP, heuristic algorithms required ex. NOVA (UCBerkeley), Albatross c. Construct transition table and excitation table d. Derive NS equations and output equations e. Logic design for each FF Input 2) Detailed Design Process a. Problem specification : sometimes informal b. Defining state behavior & improving it c. State assignment d. Combinational function spec. & circuit design e. Design verification - Simulation is essential for verifying the correctness of designs

10 3) Example Design a. A sequential circuit State diagram of a simple sequential circuit State-assigned table w = Reset A z = w = 1 w = C z = 1 w = 1 B z = w = w = 1 Next state Present state w = w = 1 Output y 1 Y 2 Y 1 Y 2 Y 1 z A 1 B 1 1 C dd dd d

11 y y 2 1 w d 1 1 d Ignoring don't cares Y = wy 1 1 Using don't cares Y = wy 1 1 y 1 w d 1 d 1 Y = wy wy 1 Y = wy + w 1 2 = w ( y + y ) 1 2 y d z = y 1 z = Logic expressions

12 Final implementation Y 2 D z w Y 1 D y 1 Clock Resetn

13 Clock w y 1 z t t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1

14 b. Counter Design Examples I. Modulo-6 counter using JK F/Fs State Transition Table State Assignment Logic Derivation II. Modulo-4 up/down counter, upcount when x=1, and downcount when x=

15 5. Moore and Mealy Models 1) FSM a. Sequential Machines are also called Finite State Machines (FSMs). b. Two formal models exist: Moore Model Named after E.F. Moore. Outputs are a function only of states Outputs usually specified on the states Mealy Model Named after G. Mealy Outputs are a function of inputs and states Outputs usually specified on the state transition arcs c. In contemporary design, models are sometimes mixed Moore and Mealy

16 Moore and Mealy Models 2) Moore Circuits a. Less sensitive to input glitches, and output responses are delayed by up to a clock period b. Mealy machine Moore machine I. Split each state into two (actuall m, where m :#outputs), and associate a fixed value of z with each split state II. Each node has the corresponding output value written inside the node

17 Moore and Mealy Models 3) Comparisons a. Mealy Model State Diagram - maps inputs and state to outputs x=/y=s x=1/y= S1 b. Moore Model State Diagram - maps states to outputs x= x=/y= x=1/y=1 x=1 S/ x= x=1 x= S1/ S2/1 x=1

18 The general form of a sequential circuit Mealy model/machine W Combinational Circuit F/Fs Combinational Circuit Z Clock

19 A general sequential circuit with two state flip-flops Moore model/machine w Combinational Circuit Y 1 y 1 Combinational Circuit z Y 2 Clock

20 4) State diagram for the Moore-type serial adder FSM reset G s = 11 H s = G 1 s = 1 H 1 s = 1 11

21 5) Circuit for the Moore-type serial adder FSM a b Full adder Sum bit Carry-out Y 1 D y 1 s Y 2 D Clock Reset

22 5) Circuit for the Moore-type serial adder FSM a b Full adder Sum bit Carry-out Y 1 D y 1 s Y 2 D Clock Reset

23 5) Circuit for the Moore-type serial adder FSM a b Full adder Sum bit Carry-out Y 1 D y 1 s Y 2 D Clock Reset

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007 EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler