Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90

Size: px
Start display at page:

Download "Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90"

Transcription

1 Final Exam ECE 25, Spring 2008 Thursday, June 12, 2008 Name: PID: Problem Points Score Total 90 1) Number representation (10 pts) a) For each binary vector below, what does it represent as an Octal number and a Hexadecimal number? Binary Octal Hexadecimal b) Given X and Y below that are 4-bit numbers in 2 s complement form, fill in the table of what S should be bit-vector form, whether or not there is an overflow, andwhats is as a number. (First row provides an example.) X Y S = X Y S as a x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 s 3 s 2 s 1 s 0 Overflow? number No

2 2) Two-level logic minimization (10 pts) Consider the logic diagram shown below. X A Y B OR F C D a) The second block F (A, B, C, D) is a function of A, B, C, andd. Please fill out the following K-map by taking into consideration combinations of A and B that cannot occur as don t cares because A and B are themselves functions of X and Y. AB CD 00 F b) For the K-map derived in part (a) for F, specify all the primes and essential primes. Prime Essential c) Find the minimum two-level logic implementation for F. F = 2

3 3) Finite state machines (10 pts) Consider the following Mealy state machine with A as the initial state. 1/0 0/1 A 0/1 1/1 0/0 B 1/0 C Figure 1: Mealy machine. If the input sequence is 011, then the corresponding output sequence, A 0/1 B 1/0 C 1/1 A, would be 101. a) What would be output sequence if the input sequence is 100? b) What would be output sequence if the input sequence is 001? c) Consider the following Mealy state machine with R as the initial state. 0/1 R 1/0 0/1 1/1 S 1/0 T Figure 2: Mealy machine. Part 1) If the input is fixed to a constant 1 for all cycles, then will the Mealy machine shown in Fig. 2 produce the same output as the Mealy machine in shown Fig. 1 starting from their respective initial states? Part 2) If the input is fixed to a constant 0 for all cycles, then will the two Mealy machines produce the same outputs? You have to get both parts correct to get points so that you can t just guess the answer. 3

4 4) Multi-level logic minimization (10 pts) Given following logic equations, minimize the number of literals, e.g. by using common subexpressions, Boolean rules, etc. You can introduce new immediate equations for common sub-expressions if it helps to reduce the number of literals. Put a box around your final answer, and indicate the number of literals in your final answer. H = Ā B C + Ā BC + A B C + A BC + AB C + ABC J = A + B K = ĀBE(ĀBE + CDE) L = AD + Ā BD + Ā BCD 4

5 5) Sequential logic implementation (10 pts) Consider the following Moore machine with initial state A. S + 2 S S 2 I =0 I =1 Z A B C 0 B F A 1 C B C 0 D E C 1 E F D 0 F F A 1 G A F 0 Assume the following state encoding. State S 2 A 000 B 001 C 100 D 101 E 011 F 111 G 010 Derive the minimum two-level logic for the output Z by taking into consideration what states are reachable from the initial state A. Z = 5

6 6) Reverse engineer sequential circuit to finite state machine (10 pts) + D-FF F I + D-FF a) Fill out the following functions (OK to use in functions). F = + = + = b) Assume initial state is 00, fill in the following state table. If a state is not reacheable, indicate the appropriate don t cares (use * to indicate don t cares). S I =0 I =1 F c) With initial state = 00, what states, if any, are not reacheable? 6

7 7) ALU design (10 pts) Consider the following diagram with two sets of data inputs A 3 A 2 A 1 A 0 and B 3 B 2 B 1 B 0, two selection bits and, and one set of outputs F 3 F 2 F 1 F 0. A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 your logic your logic your logic your logic X 3 Y 3 X 2 Y 2 X 1 Y 1 X 0 Y 0 overflow C 4 full C 3 full C 2 full C 1 adder adder adder full adder C 0 F 3 F 2 F 1 F 0 Consider the following four ALU operations: ALU operation 0 0 A (two s complement of A) 0 1 B (two s complement of B) 1 0 A B 1 1 A + B Specify the minimized logic equations for X i and Y i of the your function box shown in the diagram. (X i and Y i are both functions of A i, B i,,.) X i = Y i = 7

8 8) Timing analysis (10 pts) Consider the following sequential logic diagram. Assume the gate delay is 1 ns for both 2- and 2-OR. Assume the gate delay is 3 ns for 2-. Assume the positive edge-trigged flip-flop delay is T delayf F = 1 ns, and Assume the positive edge-trigged flip-flop setup time is also T setupf F = 1 ns. a) Fill out the rest of the timing diagram for A, B, C, D, and E. B A OR D D-FF E C A B C D E CLK b) The clock period shown in the diagram is 6ns. The clock can safely run faster. How fast can we run the clock (what is the shortest feasible clock period)? 8

9 9) Delay analysis (10 pts) Consider the following 32-bit priority encoder with inputs R 31 R 30 R 1 R 0 ( requests ) and outputs G 31 G 30 G 1 G 0 ( grants ). When both R i =1,and thereisnor j =1suchthatj>i, then G i =1;otherwise,G i = 0. The logic in Fig. 3 is designed so that at most one G i is equal to 1, corresponding to the highest R i = 1 request. The output status = 1 indicates that there was agrant.assume1ns gate delay for all gates (i.e., 2-, 2-OR, and INV). R i R 31 R 30 R 1 R 0 D i OR D i-1 D 31 = 0 D 30 D 29 D 1 D 0 status G 31 G 30 G 1 G 0 G i Figure 3: Priority encoder. Figure 4: Logic for rectangle box. a) What is the longest delay in Fig. 3 (in ns)? b) Which output in Fig. 3 determines the longest delay? Now consider the following modified diagram (same gate delays and same Fig. 4 rectangle box). R 31 R 30 R 1 R 0 D 31 = 0 D 30 D 29 D 1 D 0 S G 31 G 30 G 1 G 0 E 31 = 0 E 30 E 29 E 1 E 0 T H 31 H 30 H 1 H 0 Figure 5: Modified design. c) What is the longest delay in Fig. 5 (in ns)? d) Which output in Fig. 5 determines the longest delay? 9

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

Total time is: 1 setup, 2 AND, 3 XOR, 1 delay = (1*1) + (2*2) + (3*3) + (1*1) = 15ns

Total time is: 1 setup, 2 AND, 3 XOR, 1 delay = (1*1) + (2*2) + (3*3) + (1*1) = 15ns Clock Period/ Delay Analysis: Find longest possible path (time-wise) between two flip-flops. If 2ns for AND and 3ns for XOR, with T delayff = 1ns and T setupff = 1 ns. So the total time is: 1 setupff +

More information

For smaller NRE cost For faster time to market For smaller high-volume manufacturing cost For higher performance

For smaller NRE cost For faster time to market For smaller high-volume manufacturing cost For higher performance University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]

More information

Computer Science Final Examination Friday December 14 th 2001

Computer Science Final Examination Friday December 14 th 2001 Computer Science 03 60 265 Final Examination Friday December 14 th 2001 Dr. Robert D. Kent and Dr. Alioune Ngom Last Name: First Name: Student Number: INSTRUCTIONS EXAM DURATION IS 3 HOURs. CALCULATORS,

More information

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)

More information

Lecture 10: Synchronous Sequential Circuits Design

Lecture 10: Synchronous Sequential Circuits Design Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple

More information

CPE100: Digital Logic Design I

CPE100: Digital Logic Design I Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour

More information

Different encodings generate different circuits

Different encodings generate different circuits FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,

More information

COMBINATIONAL LOGIC FUNCTIONS

COMBINATIONAL LOGIC FUNCTIONS COMBINATIONAL LOGIC FUNCTIONS Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends only on the present

More information

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 Name of the person on your left : Name of the person on your right: 1. 20 points 2. 20 points 3. 20 points 4. 15 points 5. 15 points 6. 10

More information

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process Parity Checker Example A string of bits has even parity if the number of 1 s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5: Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed

More information

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering Sp 6 Reg. No. Question Paper Code : 27156 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2015. Second Semester Computer Science and Engineering CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common

More information

Practice Final Exam Solutions

Practice Final Exam Solutions The University of Michigan Department of Electrical Engineering and Computer Science EECS 270 Fall 2003 Practice Final Exam Solutions Name: UM ID: For all questions, show all work that leads to your answer.

More information

04. What is the Mod number of the counter circuit shown below? Assume initially reset.

04. What is the Mod number of the counter circuit shown below? Assume initially reset. . Which of the following is the state diagram for the Meale machine shown below. 4. What is the Mod number of the counter circuit shown below? Assume initiall reset. input CLK D output D D a. b. / / /

More information

Finite State Machine (FSM)

Finite State Machine (FSM) Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State

More information

L10 State Machine Design Topics

L10 State Machine Design Topics L State Machine Design Topics States Machine Design Other topics on state machine design Equivalent sequential machines Incompletely specified machines One Hot State Machines Ref: text Unit 15.4, 15.5,

More information

The University of Michigan Department of Electrical Engineering and Computer Science. EECS 270 Fall Practice Final Exam.

The University of Michigan Department of Electrical Engineering and Computer Science. EECS 270 Fall Practice Final Exam. The University of Michigan Department of Electrical Engineering and Computer Science EECS 270 Fall 2003 Practice Final Exam Name: UM ID: For all questions, show all work that leads to your answer. Problem

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, Second Semester: 2015/2016 Dept. of Computer Engineering Course Title: Logic Circuits Date: 08/06/2016

More information

Problem Set 9 Solutions

Problem Set 9 Solutions CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You

More information

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008

CSE 140 Midterm 2 Tajana Simunic Rosing. Spring 2008 CSE 14 Midterm 2 Tajana Simunic Rosing Spring 28 Do not start the exam until you are told to. Turn off any cell phones or pagers. Write your name and PID at the top of every page. Do not separate the pages.

More information

Logic. Combinational. inputs. outputs. the result. system can

Logic. Combinational. inputs. outputs. the result. system can Digital Electronics Combinational Logic Functions Digital logic circuits can be classified as either combinational or sequential circuits. A combinational circuit is one where the output at any time depends

More information

The Design Procedure. Output Equation Determination - Derive output equations from the state table

The Design Procedure. Output Equation Determination - Derive output equations from the state table The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types

More information

Synchronous Sequential Circuit Design. Digital Computer Design

Synchronous Sequential Circuit Design. Digital Computer Design Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always

More information

EEE2135 Digital Logic Design

EEE2135 Digital Logic Design EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the

More information

vidyarthiplus.com vidyarthiplus.com vidyarthiplus.com ANNA UNIVERSITY- COMBATORE B.E./ B.TECH. DEGREE EXAMINATION - JUNE 2009. ELECTRICAL & ELECTONICS ENGG. - FOURTH SEMESTER DIGITAL LOGIC CIRCUITS PART-A

More information

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Review: cache hit rate - Project3 - Digital Logic: - truth table => SOP - simplification: Boolean

More information

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18 University of Waterloo Department of Electrical & Computer Engineering E&CE 223 Digital Circuits and Systems Midterm Examination Instructor: M. Sachdev October 23rd, 2007 Total Time = 90 Minutes, Total

More information

Cs302 Quiz for MID TERM Exam Solved

Cs302 Quiz for MID TERM Exam Solved Question # 1 of 10 ( Start time: 01:30:33 PM ) Total Marks: 1 Caveman used a number system that has distinct shapes: 4 5 6 7 Question # 2 of 10 ( Start time: 01:31:25 PM ) Total Marks: 1 TTL based devices

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture 6 - Combinational Logic Introduction A combinational circuit consists of input variables, logic gates, and output variables. The logic gates accept

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final

More information

EECS150 - Digital Design Lecture 23 - FSMs & Counters

EECS150 - Digital Design Lecture 23 - FSMs & Counters EECS150 - Digital Design Lecture 23 - FSMs & Counters April 8, 2010 John Wawrzynek Spring 2010 EECS150 - Lec22-counters Page 1 One-hot encoding of states. One FF per state. State Encoding Why one-hot encoding?

More information

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

More information

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay ENGG 23 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR Parity checking (for interest) Parity bit Parity checking Error detection, eg. Data can be Corrupted Even parity total number of s is even Odd parity

More information

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100

More information

Lecture 8: Sequential Networks and Finite State Machines

Lecture 8: Sequential Networks and Finite State Machines Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

Quiz 2 Solutions Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins)

Quiz 2 Solutions Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins) UNIVERSITY OF CALIFORNIA AT BERKELEY ERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer Sciences Quiz 2 Solutions

More information

DIGITAL LOGIC CIRCUITS

DIGITAL LOGIC CIRCUITS DIGITAL LOGIC CIRCUITS Digital logic circuits BINARY NUMBER SYSTEM electronic circuits that handle information encoded in binary form (deal with signals that have only two values, and ) Digital. computers,

More information

EE 209 Logic Cumulative Exam Name:

EE 209 Logic Cumulative Exam Name: EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be

More information

EECS 270 Midterm Exam 2 Fall 2009

EECS 270 Midterm Exam 2 Fall 2009 EECS 270 Midterm Exam 2 Fall 2009 Name: unique name: UMID: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1&2

More information

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic ENGG 1203 Tutorial_9 - Review Boolean Algebra 1. Combinational & Sequential Logic 2. Computer Systems 3. Electronic Circuits 4. Signals, Systems, and Control Remark : Multiple Choice Questions : ** Check

More information

FSM model for sequential circuits

FSM model for sequential circuits 1 FSM model for sequential circuits The mathematical model of a sequential circuit is called finite-state machine. FSM is fully characterized by: S Finite set of states ( state ~ contents of FFs) I Finite

More information

PAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS:

PAST EXAM PAPER & MEMO N3 ABOUT THE QUESTION PAPERS: EKURHULENI TECH COLLEGE. No. 3 Mogale Square, Krugersdorp. Website: www. ekurhulenitech.co.za Email: info@ekurhulenitech.co.za TEL: 011 040 7343 CELL: 073 770 3028/060 715 4529 PAST EXAM PAPER & MEMO N3

More information

UNIVERSITI TENAGA NASIONAL. College of Information Technology

UNIVERSITI TENAGA NASIONAL. College of Information Technology UNIVERSITI TENAGA NASIONAL College of Information Technology BACHELOR OF COMPUTER SCIENCE (HONS.) FINAL EXAMINATION SEMESTER 2 2012/2013 DIGITAL SYSTEMS DESIGN (CSNB163) January 2013 Time allowed: 3 hours

More information

ENEL Digital Circuits Final Examination

ENEL Digital Circuits Final Examination Name: I#: Lecture Section: ENEL 353 - igital Circuits Final Examination Lecture sections : N. R. Bartley, MWF : :5, ENC 24 2: S. A. Norman, MWF : :5, ST 45 Wednesday, ecember 7, 24 Time: 7: PM : PM Locations:

More information

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Sequential Synchronous Circuit Analysis

Sequential Synchronous Circuit Analysis Sequential Synchronous Circuit Analysis General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES

ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN VALUES EC 216(R-15) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER- 2016 First Semester ELECTRONICS & COMMUNICATION ENGINEERING PROFESSIONAL ETHICS AND HUMAN

More information

Sequential Logic Worksheet

Sequential Logic Worksheet Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet

More information

Lecture 3 Review on Digital Logic (Part 2)

Lecture 3 Review on Digital Logic (Part 2) Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal

More information

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata Simplification of Boolean Functions Dept. of CSE, IEM, Kolkata 1 Simplification of Boolean Functions: An implementation of a Boolean Function requires the use of logic gates. A smaller number of gates,

More information

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics) Task 1. Exercises: Logical Design of Digital Systems Seite: 1 Self Study (Boolean Algebra, combinational circuits) 1.1 Minimize the function f 1 a ab ab by the help of Boolean algebra and give an implementation

More information

Sequential Circuit Design

Sequential Circuit Design Sequential Circuit esign esign Procedure. Specification 2. Formulation Obtain a state diagram or state table 3. State Assignment Assign binary codes to the states 4. Flip-Flop Input Equation etermination

More information

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007 EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler

More information

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation

More information

Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33]

Chapter 4: Combinational Logic Solutions to Problems: [1, 5, 9, 12, 19, 23, 30, 33] Chapter 4: Combinational Logic Solutions to Problems: [, 5, 9, 2, 9, 23, 3, 33] Problem: 4- Consider the combinational circuit shown in Fig. P4-. (a) Derive the Boolean expressions for T through T 4. Evaluate

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

Fundamentals of Computer Systems

Fundamentals of Computer Systems Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided

More information

Time Allowed 3:00 hrs. April, pages

Time Allowed 3:00 hrs. April, pages IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using

More information

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.4-7.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html

More information

DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates.

DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS. To design and implement encoders and decoders using logic gates. DESIGN AND IMPLEMENTATION OF ENCODERS AND DECODERS AIM To design and implement encoders and decoders using logic gates. COMPONENTS REQUIRED S.No Components Specification Quantity 1. Digital IC Trainer

More information

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits Objectives Analysis of Clocked Sequential Circuits The objectives of this lesson are as follows: Analysis of clocked sequential circuits with an example State Reduction with an example State assignment

More information

Simplify the following Boolean expressions and minimize the number of literals:

Simplify the following Boolean expressions and minimize the number of literals: Boolean Algebra Task 1 Simplify the following Boolean expressions and minimize the number of literals: 1.1 1.2 1.3 Task 2 Convert the following expressions into sum of products and product of sums: 2.1

More information

Sequential Circuit Analysis

Sequential Circuit Analysis Sequential Circuit Analysis Last time we started talking about latches and flip-flops, which are basic one-bit memory units. Today we ll talk about sequential circuit analysis and design. First, we ll

More information

Sequential logic and design

Sequential logic and design Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by

More information

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3 Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 02-2 Truth Table The most basic representation of a logic function Lists the output for all possible

More information

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University

COEN 312 DIGITAL SYSTEMS DESIGN - LECTURE NOTES Concordia University 1 OEN 312 DIGIAL SYSEMS DESIGN - LEURE NOES oncordia University hapter 6: Registers and ounters NOE: For more examples and detailed description of the material in the lecture notes, please refer to the

More information

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents B-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix B: Reduction of Digital Logic B-2 Chapter Contents B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction

More information

University of Minnesota Department of Electrical and Computer Engineering

University of Minnesota Department of Electrical and Computer Engineering University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID

More information

UNIT 5 KARNAUGH MAPS Spring 2011

UNIT 5 KARNAUGH MAPS Spring 2011 UNIT 5 KRNUGH MPS Spring 2 Karnaugh Maps 2 Contents Minimum forms of switching functions Two- and three-variable Four-variable Determination of minimum expressions using essential prime implicants Five-variable

More information

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic

CPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational

More information

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1 Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential

More information

Logical design of digital systems

Logical design of digital systems 21062017 lectures Summer Semester 2017 Table of content 1 Combinational circuit design 2 Elementary combinatorial circuits for data transmission 3 Memory structures 4 Programmable logic devices 5 Algorithmic

More information

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions? Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits Other operations NAND A NAND B = NOT ( A ANDB) = AB NOR A NOR B = NOT ( A ORB) = A + B Truth tables What is the result of the operation

More information

DE58/DC58 LOGIC DESIGN DEC 2014

DE58/DC58 LOGIC DESIGN DEC 2014 Q.2 a. In a base-5 number system, 3 digit representations is used. Find out (i) Number of distinct quantities that can be represented.(ii) Representation of highest decimal number in base-5. Since, r=5

More information

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page of COE 22: Digital Logic Design (3--3) Term (Fall 22) Final Exam Sunday January

More information

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date.

Schedule. ECEN 301 Discussion #25 Final Review 1. Date Day Class No. 1 Dec Mon 25 Final Review. Title Chapters HW Due date. Lab Due date. Schedule Date Day Class No. Dec Mon 25 Final Review 2 Dec Tue 3 Dec Wed 26 Final Review Title Chapters HW Due date Lab Due date LAB 8 Exam 4 Dec Thu 5 Dec Fri Recitation HW 6 Dec Sat 7 Dec Sun 8 Dec Mon

More information

Chapter 7 Logic Circuits

Chapter 7 Logic Circuits Chapter 7 Logic Circuits Goal. Advantages of digital technology compared to analog technology. 2. Terminology of Digital Circuits. 3. Convert Numbers between Decimal, Binary and Other forms. 5. Binary

More information

ELE2120 Digital Circuits and Systems. Tutorial Note 9

ELE2120 Digital Circuits and Systems. Tutorial Note 9 ELE2120 Digital Circuits and Systems Tutorial Note 9 Outline 1. Exercise(1) Sequential Circuit Analysis 2. Exercise (2) Sequential Circuit Analysis 3. Exercise (3) Sequential Circuit Analysis 4. Ref. Construction

More information

Digital Electronics Final Examination. Part A

Digital Electronics Final Examination. Part A Digital Electronics Final Examination Part A Spring 2009 Student Name: Date: Class Period: Total Points: /50 Converted Score: /40 Page 1 of 13 Directions: This is a CLOSED BOOK/CLOSED NOTES exam. Select

More information

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of 27 WORKBOOK Detailed Eplanations of Try Yourself Questions Electrical Engineering Digital Electronics Number Systems and Codes T : Solution Converting into decimal number system 2 + 3 + 5 + 8 2 + 4 8 +

More information

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary Number System Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary BOOLEAN ALGEBRA BOOLEAN LOGIC OPERATIONS Logical AND Logical OR Logical COMPLEMENTATION

More information

Digital Logic Appendix A

Digital Logic Appendix A Digital Logic Appendix A Boolean Algebra Gates Combinatorial Circuits Sequential Circuits 1 Boolean Algebra George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 Describe digital circuitry

More information

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE Estd-1984 KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE 641 006 QUESTION BANK UNIT I PART A ISO 9001:2000 Certified 1. Convert (100001110.010) 2 to a decimal number. 2. Find the canonical SOP for the function

More information

Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER

Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER Synchronous Sequential Logic Part I BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Sequential Logic Digital circuits we have learned, so far, have been combinational no memory,

More information

Models for representing sequential circuits

Models for representing sequential circuits Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams

More information

Written exam for IE1204/5 Digital Design with solutions Thursday 29/

Written exam for IE1204/5 Digital Design with solutions Thursday 29/ Written exam for IE4/5 Digital Design with solutions Thursday 9/ 5 9.-. General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 8-794487 Exam text does not have to be returned when

More information

Lecture (08) Synchronous Sequential Logic

Lecture (08) Synchronous Sequential Logic Lecture (08) Synchronous Sequential Logic By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II Analysis of Clocked Sequential Circuits The behavior of a clocked sequential

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2017/2018 Dept. of Computer Engineering Course Title: Logic Circuits Date: 29/01/2018

More information

Karnaugh Maps Objectives

Karnaugh Maps Objectives Karnaugh Maps Objectives For Karnaugh Maps of up to 5 variables Plot a function from algebraic, minterm or maxterm form Obtain minimum Sum of Products and Product of Sums Understand the relationship between

More information

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra Digital Logic Appendix A Gates Combinatorial Circuits Sequential Circuits George Boole ideas 1854 Claude Shannon, apply to circuit design, 1938 (piirisuunnittelu) Describe digital circuitry function programming

More information

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C. Numbers & Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Chapter 2.4-2.6, 3.2, C.5 C.6 Example: Big Picture Computer System Organization and Programming

More information

CSC9R6 Computer Design. Practical Digital Logic

CSC9R6 Computer Design. Practical Digital Logic CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/

More information

Numbers and Arithmetic

Numbers and Arithmetic Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu

More information

Quiz 2 Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins)

Quiz 2 Room 10 Evans Hall, 2:10pm Tuesday April 2 (Open Katz only, Calculators OK, 1hr 20mins) Your Name: NIVERSITY OF CALIFORNIA AT BERKELEY RKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS 150

More information