EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization
|
|
- Brittany Carter
- 5 years ago
- Views:
Transcription
1 EECS 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Discrete Systems Lecture: Automata, State machines, Circuits Stavros Tripakis University of California, Berkeley Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 1 / 36
2 Discrete Systems Automata, state machines, transition systems,... States Transitions: discrete moves from state to state Logical time: order of transitions As opposed to quantitative, real-time models that we will see later Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 2 / 36
3 AUTOMATA, STATE MACHINES, DIGITAL CIRCUITS Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 3 / 36
4 Deterministic Finite Automata A DFA is a tuple (Σ, S, s 0, δ, F ) Σ: finite set of symbols, letters (the alphabet) S: finite set of states s 0 S: (unique) initial state δ: transition function (usually total but could also be partial) δ : S Σ S F S: set of final/accepting states Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 4 / 36
5 Example: Automaton a s 0 b s 1 c s 2 a Define the tuple: (Σ, S, s 0, δ, F ) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 5 / 36
6 DFA as Systems DFA states = system states DFA transitions = system dynamics What about inputs and outputs? Viewing the DFA as an acceptor: Σ = set of inputs. Viewing the DFA as a generator: Σ = set of outputs. Accepting states can be seen as a boolean output: 0 if the current state s F ; 1 otherwise. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 6 / 36
7 DFA as Language Acceptors Theory of formal languages and grammars Major contributions by linguists Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 7 / 36
8 DFA as Language Acceptors Theory of formal languages and grammars Major contributions by linguists Since then, innumerable applications. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 7 / 36
9 Important application: verification Source Design Monitor Source: an automaton, viewed as generator. Generates all possible valid input sequences. Monitor: an automaton, viewed as an acceptor. Models the property we want to check. E.g., property holds iff there is no accepting behavior. Design: the system we want to verify. It has inputs and outputs, usually captured as state machine. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 8 / 36
10 Important application: verification Environment Design Monitor Environment: a state machine. There is often feedback between the system and its environment. I.e., the values that the environment provides to the system depend on what it receives from the system. Monitor: an automaton, viewed as an acceptor. Models the property we want to check. E.g., property holds iff there is no accepting behavior. Design: the system we want to verify. It has inputs and outputs, usually captured as state machine. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 9 / 36
11 Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: If the FSM is of type Mealy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36
12 Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: λ : S O If the FSM is of type Mealy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36
13 Finite State Machines An FSM is a tuple (I, O, S, s 0, δ, λ) I: set of inputs O: set of outputs S: set of states s 0 S: initial state δ : S I S: transition function λ: output function If the FSM is of type Moore: λ : S O If the FSM is of type Mealy: λ : S I O Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 10 / 36
14 Example: Moore Machine structure: tick (implicit) counter modulo 4 MSB {0, 1} LSB {0, 1} behavior: s 0 00 s 1 01 s 2 10 s 3 11 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 11 / 36
15 Example: Mealy Machine structure: in1 {0, 1} in2 {0, 1} arbiter out {0, 1, 2} behavior: 01/1 00/0 00/0 11/1 01/1 10/2 11/2 10/2 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 12 / 36
16 Example: Mealy Machine original: in1 {0, 1} in2 {0, 1} arbiter out {0, 1, 2} 01/1 10/2 00/0 00/0 11/1 01/1 11/2 10/2 alternative drawing: out := case in1 in2 00 : 0; 01 : 1; 10 : 2; 11 : 1; end out := case in1 in2 00 : 0; 01 : 1; 10 : 2; 11 : 2; end Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 13 / 36
17 Synchronous Circuits Generic structural view: Combinational logic part: a network of logical gates (AND, OR, NOT, XOR,...). Memory/state of the circuit: some type of digital memory element (e.g., D-type flip-flop). Synchronous: clock arriving conceptually synchronously (simultaneously) at all flip-flops. Circuit: a network of connected gates and flip-flops ( netlist ). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 14 / 36
18 Memory element: D flip-flop D (input) clock output Behavior (simplified): 1 Clock input defines a set of times t 1, t 2, t 3,... (e.g., up-edges of a periodic pulse). The value of output remains constant during the interval [t k, t k+1 ) and equal to the value of the input D at t k. Door-window metaphor (on white board). 1 More accurate description of timing behavior in timing analysis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 15 / 36
19 Memory element: D flip-flop D (input) clock output Behavior (simplified): 1 Clock input defines a set of times t 1, t 2, t 3,... (e.g., up-edges of a periodic pulse). The value of output remains constant during the interval [t k, t k+1 ) and equal to the value of the input D at t k. Door-window metaphor (on white board). Memory elements often have more inputs (e.g., resets to initialize state). 1 More accurate description of timing behavior in timing analysis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 15 / 36
20 Combinational logic gates Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 16 / 36
21 Digital Circuits: Networks of Flip-Flops and Logic Gates For now, we consider acyclic circuits: any feedback loops are broken by flip-flops: Dynamics determined by the sequence of clock pulses. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 17 / 36
22 From Circuits to State Machines Is this a state machine? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 18 / 36
23 From Circuits to State Machines Is this a state machine? Is it a Mealy or Moore machine? How are (I, O, S, s 0, δ, λ) defined? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 19 / 36
24 From Circuits to State Machines Is this a state machine? Is it a Mealy or Moore machine? How are (I, O, S, s 0, δ, λ) defined? What would a Moore Machine look like? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 19 / 36
25 State Machines and Synchronous Circuits Why this is not a good drawing: 01/1 00/0 00/0 11/1 01/1 10/2 11/2 10/2 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 20 / 36
26 From FSMs to Circuits Brute-force implementation: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36
27 From FSMs to Circuits Brute-force implementation: log n flip-flops, where n = S = number of states of the FSM. log k input wires, where k = I = number of input symbols. log m output wires, where m = O = number of output symbols. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36
28 From FSMs to Circuits Brute-force implementation: log n flip-flops, where n = S = number of states of the FSM. log k input wires, where k = I = number of input symbols. log m output wires, where m = O = number of output symbols. Multiplexers to implement transition and output functions. More efficient implementations: logic synthesis lecture. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 21 / 36
29 An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36
30 An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? E 0 = false E k+1 = X k+1 X k Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36
31 An Elegant Notation for State Machines: Lustre A program in the synchronous language Lustre [Halbwachs et al., 1991]: node Edge (X : bool) returns (E : bool); let E = false -> X and not pre X ; tel Can you guess its meaning? E 0 = false E k+1 = X k+1 X k Quiz: write a counter in Lustre. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 22 / 36
32 Non-Deterministic Finite Automata An NFA is a tuple (Σ, S, S 0,, F ) Σ: alphabet S: finite set of states S 0 S: set of initial states : transition relation S Σ S or S Σ {ɛ} S F S: set of final/accepting states Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 23 / 36
33 Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36
34 Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Can DFA always be viewed as deterministic? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36
35 Non-Determinism: Why? Uncertainty, e.g.: user input unknown weather patterns unknown... Abstraction: don t want to model some details (e.g., how message corruption occurs) Can DFA always be viewed as deterministic? What if they are generators? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 24 / 36
36 (Linear) Runs, Behaviors,... A run of a NFA (Σ, S, S 0,, F ) is a (finite or infinite) sequence of states and transitions: a s 1 a 0 2 a s1 3 s2 such that s 0 S 0 i : (s i, a i+1, s i+1 ) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 25 / 36
37 (Linear) Runs, Behaviors,... A run of a NFA (Σ, S, S 0,, F ) is a (finite or infinite) sequence of states and transitions: a s 1 a 0 2 a s1 3 s2 such that s 0 S 0 i : (s i, a i+1, s i+1 ) A behavior is the corresponding sequence of labels: a 1 a 2 a 3 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 25 / 36
38 (Linear) Runs, Behaviors,... A run of a NFA (Σ, S, S 0,, F ) is a (finite or infinite) sequence of states and transitions: a s 1 a 0 2 a s1 3 s2 such that s 0 S 0 i : (s i, a i+1, s i+1 ) A behavior is the corresponding sequence of labels: a 1 a 2 a 3 Accepting run (and corresponding accepted behaviors): if run is finite: ending in a state in F. if run is infinite: infinitely often visiting a state in F (Büchi condition), or other conditions (Rabin, Street,...). Language: set of behaviors accepted by the automaton. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 25 / 36
39 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
40 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
41 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
42 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
43 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton or a network of actors... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
44 (Linear) Runs, Behaviors,... = Semantics! Syntax vs. Semantics: Syntax: the program, the automaton, the model,... Semantics: the set of runs/behaviors of the program, automaton, model,... What is this? a b c A graph (syntax). What is its semantics? It could be an automaton or a network of actors or a dependency relation or... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 26 / 36
45 Syntax vs. Semantics Different models could have the same semantics, e.g.: different automata may accept the same language. 0, NFA: s 1 0 s 1 DFA: q 0 q 1 0 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 27 / 36
46 Syntax vs. Semantics Different models could have the same semantics, e.g.: different automata may accept the same language. 0,1 s 1 NFA: 0 s DFA: q 0 q 1 different models that mean the same thing, e.g., FSM vs. Lustre program. 1 0 Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 27 / 36
47 Syntax vs. Semantics Different models could have the same semantics, e.g.: different automata may accept the same language. 0,1 s 1 NFA: 0 s DFA: q 0 q 1 different models that mean the same thing, e.g., FSM vs. Lustre program. A single model may be assigned many different semantics, e.g.: linear vs. branching-time semantics (we will look at these later) operational vs. denotational semantics Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 27 / 36
48 Operational and Denotational Semantics for FSMs A run of a Mealy machine (I, O, S, s 0, δ, λ) is a (finite or infinite) sequence of states / transitions: such that i : x i I, y i O i : s i+1 = δ(s i, x i ) i : y i = λ(s i, x i ) x 0/y 0 x 1/y 1 x 2/y 2 s 0 s1 s2 The observable I/O behavior corresponding to the above run is (x 0, y 0 ) (x 1, y 1 ) (x 2, y 2 ) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 28 / 36
49 Operational and Denotational Semantics for FSMs A run of a Mealy machine (I, O, S, s 0, δ, λ) is a (finite or infinite) sequence of states / transitions: such that i : x i I, y i O i : s i+1 = δ(s i, x i ) i : y i = λ(s i, x i ) x 0/y 0 x 1/y 1 x 2/y 2 s 0 s1 s2 The observable I/O behavior corresponding to the above run is (x 0, y 0 ) (x 1, y 1 ) (x 2, y 2 ) I can also look at a Mealy machine as a function M : I ω O ω which to every infinite input sequence x 0 x 1 assigns an infinite output sequence y 0 y 1 = M(x 0 x 1 ) defined as above. Quiz: why is this a function? is it a total function? Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 28 / 36
50 Types of semantics operational runs, trees, transition systems,... denotational sets (e.g., of behaviors), functions (on values, streams, signals,...), relations,... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 29 / 36
51 Expressiveness How powerful is a modeling language? What kind of systems can it express? Mathematically: which types of sets, functions,... can it express? Can we compare modeling languages? When are two systems similar? equivalent? When are two formalisms equivalent? i.e., for any system expressed in formalism A, there exists an equivalent/similar system expressed in formalism B. Many notions of equivalence different notions of expressiveness: language containement, language equivalence, simulations, bisimulations,... Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 30 / 36
52 Expressiveness E.g., Chomsky hierarchy: Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36
53 Expressiveness E.g., Chomsky hierarchy: Not much work in comparing heterogeneous modeling languages (e.g., discrete, continuous, dataflow,...). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36
54 Expressiveness E.g., Chomsky hierarchy: Not much work in comparing heterogeneous modeling languages (e.g., discrete, continuous, dataflow,...). Homework: are Moore and Mealy machines equivalent? almost equivalent? In what sense? (be precise) Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 31 / 36
55 Input-completeness Input-completeness (also called input-enabledness): system is able to accept any input at any given time. Formally: transition / output functions of automata/fsms are total. Together with non-determinism, interesting generic propery of systems, with different meanings and usages. Example: a s b 0 s c 1 s 2 This DFA has a partial transition function δ. Can it be made total? a Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 32 / 36
56 Input-completeness This DFA has a partial transition function δ. Can it be made total? a s 0 b s 1 c s 2 a Answer: it depends. If the automaton is to be used as an acceptor, yes. How? If the automaton is to be used as a generator, probably not useful. 2 Why? 2 The term input-complete is not very appropriate here, since generators have only outputs. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 33 / 36
57 Input-completeness Different meanings and usages of partial inputs: Requirements: I require that the environment never provides this input (at that time). This can be useful for contract-based design. More about this when we talk about composition. Example: read() init() write() Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 34 / 36
58 Input-completeness Different meanings and usages of partial inputs: Requirements: I require that the environment never provides this input (at that time). This can be useful for contract-based design. More about this when we talk about composition. Example: read() init() write() Assumptions: I know that the environment will never provide this input (at that time). Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 34 / 36
59 Don t cares In the assumptions case, missing inputs can be interpreted as don t cares. They can be used for instance to optimize implementations. Example: Two boolean inputs, x, y. One output z: must be 0 if x = y, 1 otherwise. Assumption: x and y cannot be both 1. Suppose our library only has OR, NOT gates. Given the assumption, I only need an OR gate. Ignoring the assumption, I would have to implement a XOR. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 35 / 36
60 Don t cares In the assumptions case, missing inputs can be interpreted as don t cares. They can be used for instance to optimize implementations. Example: Two boolean inputs, x, y. One output z: must be 0 if x = y, 1 otherwise. Assumption: x and y cannot be both 1. Suppose our library only has OR, NOT gates. Given the assumption, I only need an OR gate. Ignoring the assumption, I would have to implement a XOR. More on this on logic synthesis. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 35 / 36
61 Bibliography Halbwachs, N., Caspi, P., Raymond, P., and Pilaud, D. (1991). The synchronous dataflow programming language Lustre. Proceedings of the IEEE, 79(9): Hopcroft, J. E. and Ullman, J. D. (1990). Introduction To Automata Theory, Languages, And Computation. Addison-Wesley. Kohavi, Z. (1978). Switching and finite automata theory, 2nd ed. McGraw-Hill. Stavros Tripakis: EECS 144/244 Discrete Systems Automata, state machines, circuits 36 / 36
EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007
EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler
More informationTemporal Logic. Stavros Tripakis University of California, Berkeley. We have designed a system. We want to check that it is correct.
EE 244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 Temporal logic Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE 244, Fall 2016
More information3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value
EGC22 Digital Logic Fundamental Additional Practice Problems. Complete the following table of equivalent values. Binary. Octal 35.77 33.23.875 29.99 27 9 64 Hexadecimal B.3 D.FD B.4C 2. Calculate the following
More informationThe Design Procedure. Output Equation Determination - Derive output equations from the state table
The Design Procedure Specification Formulation - Obtain a state diagram or state table State Assignment - Assign binary codes to the states Flip-Flop Input Equation Determination - Select flipflop types
More informationEEE2135 Digital Logic Design
EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,
More informationLecture 8: Sequential Networks and Finite State Machines
Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University
More informationLecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
More informationDeterministic Finite Automata (DFAs)
Algorithms & Models of Computation CS/ECE 374, Fall 27 Deterministic Finite Automata (DFAs) Lecture 3 Tuesday, September 5, 27 Sariel Har-Peled (UIUC) CS374 Fall 27 / 36 Part I DFA Introduction Sariel
More informationCMP 309: Automata Theory, Computability and Formal Languages. Adapted from the work of Andrej Bogdanov
CMP 309: Automata Theory, Computability and Formal Languages Adapted from the work of Andrej Bogdanov Course outline Introduction to Automata Theory Finite Automata Deterministic Finite state automata
More informationCSE 135: Introduction to Theory of Computation Nondeterministic Finite Automata (cont )
CSE 135: Introduction to Theory of Computation Nondeterministic Finite Automata (cont ) Sungjin Im University of California, Merced 2-3-214 Example II A ɛ B ɛ D F C E Example II A ɛ B ɛ D F C E NFA accepting
More informationDeterministic Finite Automata (DFAs)
CS/ECE 374: Algorithms & Models of Computation, Fall 28 Deterministic Finite Automata (DFAs) Lecture 3 September 4, 28 Chandra Chekuri (UIUC) CS/ECE 374 Fall 28 / 33 Part I DFA Introduction Chandra Chekuri
More informationSri vidya college of engineering and technology
Unit I FINITE AUTOMATA 1. Define hypothesis. The formal proof can be using deductive proof and inductive proof. The deductive proof consists of sequence of statements given with logical reasoning in order
More informationFinite-state machines (FSMs)
Finite-state machines (FSMs) Dr. C. Constantinides Department of Computer Science and Software Engineering Concordia University Montreal, Canada January 10, 2017 1/19 Finite-state machines (FSMs) and state
More informationClasses and conversions
Classes and conversions Regular expressions Syntax: r = ε a r r r + r r Semantics: The language L r of a regular expression r is inductively defined as follows: L =, L ε = {ε}, L a = a L r r = L r L r
More informationFinite State Machines 2
Finite State Machines 2 Joseph Spring School of Computer Science 1COM0044 Foundations of Computation 1 Discussion Points In the last lecture we looked at: 1. Abstract Machines 2. Finite State Machines
More informationMealy & Moore Machines
Mealy & Moore Machines Moore Machine is a finite-state machine whose output values are determined solely by its current state and can be defined as six elements (S, S 0, Σ, Λ, T, G), consisting of the
More informationIntroduction to Computers & Programming
16.070 Introduction to Computers & Programming Theory of computation: What is a computer? FSM, Automata Prof. Kristina Lundqvist Dept. of Aero/Astro, MIT Models of Computation What is a computer? If you
More informationParity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process
Parity Checker Example A string of bits has even parity if the number of 1 s in the string is even. Design a circuit that accepts a bit-serial stream of bits and outputs a 0 if the parity thus far is even
More informationEE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016
EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2016 Discrete Event Simulation Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley)
More informationINF Introduction and Regular Languages. Daniel Lupp. 18th January University of Oslo. Department of Informatics. Universitetet i Oslo
INF28 1. Introduction and Regular Languages Daniel Lupp Universitetet i Oslo 18th January 218 Department of Informatics University of Oslo INF28 Lecture :: 18th January 1 / 33 Details on the Course consists
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page of COE 22: Digital Logic Design (3--3) Term (Fall 22) Final Exam Sunday January
More informationFinite-State Machines (Automata) lecture 12
Finite-State Machines (Automata) lecture 12 cl a simple form of computation used widely one way to find patterns 1 A current D B A B C D B C D A C next 2 Application Fields Industry real-time control,
More informationDigital Control of Electric Drives
Digital Control of Electric Drives Logic Circuits - equential Description Form, Finite tate Machine (FM) Czech Technical University in Prague Faculty of Electrical Engineering Ver.. J. Zdenek 27 Logic
More informationDeterministic Finite Automata (DFAs)
Algorithms & Models of Computation CS/ECE 374, Spring 29 Deterministic Finite Automata (DFAs) Lecture 3 Tuesday, January 22, 29 L A TEXed: December 27, 28 8:25 Chan, Har-Peled, Hassanieh (UIUC) CS374 Spring
More informationFinite Automata. Mahesh Viswanathan
Finite Automata Mahesh Viswanathan In this lecture, we will consider different models of finite state machines and study their relative power. These notes assume that the reader is familiar with DFAs,
More informationUnit 8: Sequ. ential Circuits
CPSC 121: Models of Computation Unit 8: Sequ ential Circuits Based on slides by Patrice Be lleville and Steve Wolfman Pre-Class Learning Goals By the start of class, you s hould be able to Trace the operation
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More information2. Elements of the Theory of Computation, Lewis and Papadimitrou,
Introduction Finite Automata DFA, regular languages Nondeterminism, NFA, subset construction Regular Epressions Synta, Semantics Relationship to regular languages Properties of regular languages Pumping
More informationCSE 135: Introduction to Theory of Computation Nondeterministic Finite Automata
CSE 135: Introduction to Theory of Computation Nondeterministic Finite Automata Sungjin Im University of California, Merced 1-27-215 Nondeterminism Michael Rabin and Dana Scott (1959) Michael Rabin Dana
More informationA Logic Primer. Stavros Tripakis University of California, Berkeley. Stavros Tripakis (UC Berkeley) EE 144/244, Fall 2014 A Logic Primer 1 / 35
EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 A Logic Primer Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE 144/244,
More informationCOM364 Automata Theory Lecture Note 2 - Nondeterminism
COM364 Automata Theory Lecture Note 2 - Nondeterminism Kurtuluş Küllü March 2018 The FA we saw until now were deterministic FA (DFA) in the sense that for each state and input symbol there was exactly
More informationEmbedded Systems Development
Embedded Systems Development Lecture 2 Finite Automata & SyncCharts Daniel Kästner AbsInt Angewandte Informatik GmbH kaestner@absint.com Some things I forgot to mention 2 Remember the HISPOS registration
More informationLogic Model Checking
Logic Model Checking Lecture Notes 10:18 Caltech 101b.2 January-March 2004 Course Text: The Spin Model Checker: Primer and Reference Manual Addison-Wesley 2003, ISBN 0-321-22862-6, 608 pgs. the assignment
More informationCourse 4 Finite Automata/Finite State Machines
Course 4 Finite Automata/Finite State Machines The structure and the content of the lecture is based on (1) http://www.eecs.wsu.edu/~ananth/cpts317/lectures/index.htm, (2) W. Schreiner Computability and
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationLet us first give some intuitive idea about a state of a system and state transitions before describing finite automata.
Finite Automata Automata (singular: automation) are a particularly simple, but useful, model of computation. They were initially proposed as a simple model for the behavior of neurons. The concept of a
More informationA Logic Primer. Stavros Tripakis University of California, Berkeley
EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2015 A Logic Primer Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE 144/244,
More informationBridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI
Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Stavros Tripakis Aalto University and University of California, Berkeley Abstract FMI (Functional Mockup Interface) is a standard
More informationTheory of Computation Lecture 1. Dr. Nahla Belal
Theory of Computation Lecture 1 Dr. Nahla Belal Book The primary textbook is: Introduction to the Theory of Computation by Michael Sipser. Grading 10%: Weekly Homework. 30%: Two quizzes and one exam. 20%:
More informationAlan Bundy. Automated Reasoning LTL Model Checking
Automated Reasoning LTL Model Checking Alan Bundy Lecture 9, page 1 Introduction So far we have looked at theorem proving Powerful, especially where good sets of rewrite rules or decision procedures have
More informationSanjit A. Seshia EECS, UC Berkeley
EECS 219C: Computer-Aided Verification Explicit-State Model Checking: Additional Material Sanjit A. Seshia EECS, UC Berkeley Acknowledgments: G. Holzmann Checking if M satisfies : Steps 1. Compute Buchi
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationfor System Modeling, Analysis, and Optimization
Fundamental Algorithms for System Modeling, Analysis, and Optimization Stavros Tripakis UC Berkeley EECS 144/244 Fall 2013 Copyright 2013, E. A. Lee, J. Roydhowdhury, S. A. Seshia, S. Tripakis All rights
More informationComputational Models - Lecture 1 1
Computational Models - Lecture 1 1 Handout Mode Ronitt Rubinfeld and Iftach Haitner. Tel Aviv University. February 29/ March 02, 2016 1 Based on frames by Benny Chor, Tel Aviv University, modifying frames
More informationDesign of Sequential Circuits
Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable
More informationSequential logic and design
Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by
More informationPeter Wood. Department of Computer Science and Information Systems Birkbeck, University of London Automata and Formal Languages
and and Department of Computer Science and Information Systems Birkbeck, University of London ptw@dcs.bbk.ac.uk Outline and Doing and analysing problems/languages computability/solvability/decidability
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationFSM model for sequential circuits
1 FSM model for sequential circuits The mathematical model of a sequential circuit is called finite-state machine. FSM is fully characterized by: S Finite set of states ( state ~ contents of FFs) I Finite
More informationAuthor: Vivek Kulkarni ( )
Author: Vivek Kulkarni ( vivek_kulkarni@yahoo.com ) Chapter-2: Finite State Machines Solutions for Review Questions @ Oxford University Press 2013. All rights reserved. 1 Q.1 Construct Mealy and Moore
More informationSynchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationDeterministic Finite Automata (DFAs)
Algorithms & Models of Computation CS/ECE 374, Fall 27 Deterministic Finite Automata (DFAs) Lecture 3 Tuesday, September 5, 27 Part I DFA Introduction Sariel Har-Peled (UIUC) CS374 Fall 27 / 36 Sariel
More informationBüchi Automata and Their Determinization
Büchi Automata and Their Determinization Edinburgh, October 215 Plan of the Day 1. Büchi automata and their determinization 2. Infinite games 3. Rabin s Tree Theorem 4. Decidability of monadic theories
More informationDesign of Embedded Systems: Models, Validation and Synthesis (EE 249) Lecture 9
Design of Embedded Systems: Models, Validation and Synthesis (EE 249) Lecture 9 Prof. Dr. Reinhard von Hanxleden Christian-Albrechts Universität Kiel Department of Computer Science Real-Time Systems and
More informationFormal Models in NLP
Formal Models in NLP Finite-State Automata Nina Seemann Universität Stuttgart Institut für Maschinelle Sprachverarbeitung Pfaffenwaldring 5b 70569 Stuttgart May 15, 2012 Nina Seemann (IMS) Formal Models
More informationBridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI
Bridging the Semantic Gap Between Heterogeneous Modeling Formalisms and FMI Stavros Tripakis David Broman Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationState-Space Exploration. Stavros Tripakis University of California, Berkeley
EE 144/244: Fundamental Algorithms for System Modeling, Analysis, and Optimization Fall 2014 State-Space Exploration Stavros Tripakis University of California, Berkeley Stavros Tripakis (UC Berkeley) EE
More informationFinite Automata. Finite Automata
Finite Automata Finite Automata Formal Specification of Languages Generators Grammars Context-free Regular Regular Expressions Recognizers Parsers, Push-down Automata Context Free Grammar Finite State
More informationState and Finite State Machines
State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register
More informationCS 154, Lecture 2: Finite Automata, Closure Properties Nondeterminism,
CS 54, Lecture 2: Finite Automata, Closure Properties Nondeterminism, Why so Many Models? Streaming Algorithms 0 42 Deterministic Finite Automata Anatomy of Deterministic Finite Automata transition: for
More informationPeled, Vardi, & Yannakakis: Black Box Checking
Peled, Vardi, & Yannakakis: Black Box Checking Martin Leucker leucker@it.uu.se Department of Computer Systems,, Sweden Plan Preliminaries State identification and verification Conformance Testing Extended
More informationClocked Synchronous State-machine Analysis
Clocked Synchronous State-machine Analysis Given the circuit diagram of a state machine: Analyze the combinational logic to determine flip-flop input (excitation) equations: D i = F i (Q, inputs) The input
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationSimplify the following Boolean expressions and minimize the number of literals:
Boolean Algebra Task 1 Simplify the following Boolean expressions and minimize the number of literals: 1.1 1.2 1.3 Task 2 Convert the following expressions into sum of products and product of sums: 2.1
More informationIntroduction to Turing Machines. Reading: Chapters 8 & 9
Introduction to Turing Machines Reading: Chapters 8 & 9 1 Turing Machines (TM) Generalize the class of CFLs: Recursively Enumerable Languages Recursive Languages Context-Free Languages Regular Languages
More informationFinite State Machine (1A) Young Won Lim 6/9/18
Finite State Machine (A) 6/9/8 Copyright (c) 23-28 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version.2 or
More informationBridging the Gap between Reactive Synthesis and Supervisory Control
Bridging the Gap between Reactive Synthesis and Supervisory Control Stavros Tripakis University of California, Berkeley Joint work with Ruediger Ehlers (Berkeley, Cornell), Stéphane Lafortune (Michigan)
More informationCSC9R6 Computer Design. Practical Digital Logic
CSC9R6 Computer Design Practical Digital Logic 1 References (for this part of CSC9R6) Hamacher et al: Computer Organization App A. In library Floyd: Digital Fundamentals Ch 1, 3-6, 8-10 web page: www.prenhall.com/floyd/
More informationComputational Models - Lecture 4
Computational Models - Lecture 4 Regular languages: The Myhill-Nerode Theorem Context-free Grammars Chomsky Normal Form Pumping Lemma for context free languages Non context-free languages: Examples Push
More informationComputational Models - Lecture 5 1
Computational Models - Lecture 5 1 Handout Mode Iftach Haitner and Yishay Mansour. Tel Aviv University. April 10/22, 2013 1 Based on frames by Benny Chor, Tel Aviv University, modifying frames by Maurice
More informationLogical design of digital systems
21062017 lectures Summer Semester 2017 Table of content 1 Combinational circuit design 2 Elementary combinatorial circuits for data transmission 3 Memory structures 4 Programmable logic devices 5 Algorithmic
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationIntroduction to the Theory of Computation. Automata 1VO + 1PS. Lecturer: Dr. Ana Sokolova.
Introduction to the Theory of Computation Automata 1VO + 1PS Lecturer: Dr. Ana Sokolova http://cs.uni-salzburg.at/~anas/ Setup and Dates Lectures and Instructions 23.10. 3.11. 17.11. 24.11. 1.12. 11.12.
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationSeptember 11, Second Part of Regular Expressions Equivalence with Finite Aut
Second Part of Regular Expressions Equivalence with Finite Automata September 11, 2013 Lemma 1.60 If a language is regular then it is specified by a regular expression Proof idea: For a given regular language
More informationEmbedded systems specification and design
Embedded systems specification and design David Kendall David Kendall Embedded systems specification and design 1 / 21 Introduction Finite state machines (FSM) FSMs and Labelled Transition Systems FSMs
More informationEE 209 Logic Cumulative Exam Name:
EE 209 Logic Cumulative Exam Name: 1.) Answer the following questions as True or False a.) A 4-to-1 multiplexer requires at least 4 select lines: true / false b.) An 8-to-1 mux and no other logi can be
More informationECE380 Digital Logic. Synchronous sequential circuits
ECE38 Digital Logic Synchronous Sequential Circuits: State Diagrams, State Tables Dr. D. J. Jackson Lecture 27- Synchronous sequential circuits Circuits here a clock signal is used to control operation
More informationAutomata, Logic and Games: Theory and Application
Automata, Logic and Games: Theory and Application 1. Büchi Automata and S1S Luke Ong University of Oxford TACL Summer School University of Salerno, 14-19 June 2015 Luke Ong Büchi Automata & S1S 14-19 June
More informationIntroduction to the Theory of Computation. Automata 1VO + 1PS. Lecturer: Dr. Ana Sokolova.
Introduction to the Theory of Computation Automata 1VO + 1PS Lecturer: Dr. Ana Sokolova http://cs.uni-salzburg.at/~anas/ Setup and Dates Lectures Tuesday 10:45 pm - 12:15 pm Instructions Tuesday 12:30
More informationDepartment of Electrical & Electronics EE-333 DIGITAL SYSTEMS
Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100
More informationCS 154, Lecture 3: DFA NFA, Regular Expressions
CS 154, Lecture 3: DFA NFA, Regular Expressions Homework 1 is coming out Deterministic Finite Automata Computation with finite memory Non-Deterministic Finite Automata Computation with finite memory and
More information14:332:231 DIGITAL LOGIC DESIGN
14:332:231 IGITL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering all 2013 Lecture #17: locked Synchronous -Machine nalysis locked Synchronous Sequential ircuits lso known as
More informationDeterministic finite Automata
Deterministic finite Automata Informatics 2A: Lecture 3 Alex Simpson School of Informatics University of Edinburgh als@inf.ed.ac.uk 21 September, 212 1 / 29 1 Languages and Finite State Machines What is
More informationCSE 311 Lecture 23: Finite State Machines. Emina Torlak and Kevin Zatloukal
CSE 3 Lecture 3: Finite State Machines Emina Torlak and Kevin Zatloukal Topics Finite state machines (FSMs) Definition and examples. Finite state machines with output Definition and examples. Finite state
More informationBasic Problems in Multi-View Modeling
Basic Problems in Multi-View Modeling Jan Reineke Stavros Tripakis Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2014-4 http://www.eecs.berkeley.edu/pubs/techrpts/2014/eecs-2014-4.html
More informationAutomata Theory for Presburger Arithmetic Logic
Automata Theory for Presburger Arithmetic Logic References from Introduction to Automata Theory, Languages & Computation and Constraints in Computational Logic Theory & Application Presented by Masood
More informationSequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More informationChapter 3: Linear temporal logic
INFOF412 Formal verification of computer systems Chapter 3: Linear temporal logic Mickael Randour Formal Methods and Verification group Computer Science Department, ULB March 2017 1 LTL: a specification
More informationDigital Circuits and Systems
EE201: Digital Circuits and Systems 4 Sequential Circuits page 1 of 11 EE201: Digital Circuits and Systems Section 4 Sequential Circuits 4.1 Overview of Sequential Circuits: Definition The circuit whose
More informationChapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Sequential circuit: A circuit that includes memory elements. In this case the output depends not only on the current input but also on the past inputs. Memory A synchronous
More informationChapter 5. Finite Automata
Chapter 5 Finite Automata 5.1 Finite State Automata Capable of recognizing numerous symbol patterns, the class of regular languages Suitable for pattern-recognition type applications, such as the lexical
More informationPart I: Definitions and Properties
Turing Machines Part I: Definitions and Properties Finite State Automata Deterministic Automata (DFSA) M = {Q, Σ, δ, q 0, F} -- Σ = Symbols -- Q = States -- q 0 = Initial State -- F = Accepting States
More informationModels for representing sequential circuits
Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams
More informationCSE 311: Foundations of Computing. Lecture 23: Finite State Machine Minimization & NFAs
CSE : Foundations of Computing Lecture : Finite State Machine Minimization & NFAs State Minimization Many different FSMs (DFAs) for the same problem Take a given FSM and try to reduce its state set by
More informationComputational Models #1
Computational Models #1 Handout Mode Nachum Dershowitz & Yishay Mansour March 13-15, 2017 Nachum Dershowitz & Yishay Mansour Computational Models #1 March 13-15, 2017 1 / 41 Lecture Outline I Motivation
More informationPreparation of Examination Questions and Exercises: Solutions
Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),
More informationC2.1 Regular Grammars
Theory of Computer Science March 22, 27 C2. Regular Languages: Finite Automata Theory of Computer Science C2. Regular Languages: Finite Automata Malte Helmert University of Basel March 22, 27 C2. Regular
More information