Finite State Machine (1A) Young Won Lim 6/9/18

Transcription

1 Finite State Machine (A) 6/9/8

2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free ocumentation License, Version.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free ocumentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using LibreOffice and Octave. 6/9/8

3 FSM and igital Logic Circuits Latch FlipFlop Registers Timing Mealy machine Moore machine Traffic Lights Examples FSM Overview (A) 3 6/9/8

4 NOR-based SR Latch SET / RESET SET S= = RESET S= = R= = R= = FSM Overview (A) 4 6/9/8

5 NOR-based SR Latch HOL HOL S= =old HOL S= =old R= =old R= =old FSM Overview (A) 5 6/9/8

6 NOR-based SR Latch SET begins RST begins SET begins RST begins S R SET S= = S= R= S= R= S= R= S= R= S= R= S= S= R= R= S= R= R= = RESET S= = R= = Hold begins Hold begins Hold begins Hold begins HOL S= R= =old =old FSM Overview (A) 6 6/9/8

7 NOR-based SR Latch States HOL RESET SET NOR based SR Latch S R S= R= S= R= S= R= S= R= S= R= SET S= R= = = = = = = RESET S= R= = = S= R= HOL S= R= =old =old FSM Overview (A) 7 6/9/8

8 SR Latch States HOL, RESET SET HOL, SET SET S= R= = = RESET S= R= = = RESET HOL S= R= =old =old FSM Overview (A) 8 6/9/8

9 NOR-based Latch SET / RESET = C= SET S= = R= = C R S = C= RESET S= = R= = C R S FSM Overview (A) 9 6/9/8

10 NOR-based Latch HOL C R =X C= HOL S= R= =old =old S C R =X C= HOL S= R= =old =old S FSM Overview (A) 6/9/8

11 NOR-based Latch Set / Reset / Hold SET begins RST begins SET begins RST begins C C transparent opaque transparent opaque Hold begins Hold begins FSM Overview (A) 6/9/8

12 NOR-based Latch transparent / opaque C C= C= C= transparent opaque transparent transparent C opaque C input output input output FSM Overview (A) 2 6/9/8

13 NOR-based Latch States HOL RESET SET NOR based Latch C C C= =X C= = C= = C= =X C= = = = C= = = = FSM Overview (A) 3 6/9/8

14 Latch States C Opaque, Opaque, Transparent Transparent Transparent Trans C= = = = Trans C= = = = Transparent Opaque C= =old =X =old FSM Overview (A) 4 6/9/8

15 Master-Slave FlipFlops Y C C C Y FSM Overview (A) 5 6/9/8

16 Master-Slave FlipFlop Master Latch Y Y Slave Latch Y Master-Slave F/F FSM Overview (A) 6 the hold output of the master is transparently reaches the output of the slave this value is held for another half period 6/9/8

17 Master Slave FlipFlop transparent / opaque transparent falling edge transparent falling edge transparent C opaque opaque opaque opaque else input output input output FSM Overview (A) 7 6/9/8

18 Master-Slave FlipFlop Falling Edge Master Latch Y CK CK C CK C Y CK CK Slave Latch FSM Overview (A) 8 6/9/8

19 Latch & FlipFlop Level Sensitive Latch CK= transparent CK= opaque CK C Edge Sensitive FlipFlop CK= transparent else opaque CK FSM Overview (A) 9 6/9/8

20 FlipFlop with Enable () EN= Regular Flip Flop Sampling posedge of CK EN CK EN= Holding Flip Flop Sampling posedge of CK EN CK FSM Overview (A) 2 6/9/8

21 FlipFlop with Enable (2) EN CK EN CK EN EN CK FSM Overview (A) 2 6/9/8

22 Registers Inputs to FFs 2 2 Outputs of FFs 2 Register 2 CLK FSM Overview (A) 22 6/9/8

23 FF Timing (Ideal) Inputs to FFs 3: Register Outputs of FFs 3: FSM Overview (A) 23 6/9/8

24 States State (t) th edge (t+) th edge (t+2) th edge (t+3) th edge (t+4) th edge (t+5) th edge Inputs Outputs Register 3: 3: (t) (t+) (t+2) (t+3) (t+4) (t+5) FSM Overview (A) 24 6/9/8

25 Sequence of States (t) th edge (t+) th edge (t+2) th edge (t+3) th edge (t+4) th edge (t+5) th edge Inputs State Outputs :?????? Register 3: (t) (t+) (t+2) (t+3) (t+4) (t+5) Find inputs to FFs which will make outputs in this sequence FSM Overview (A) 25 6/9/8

26 How to change current state Next State Current State NextSt gate delay Compute NextSt from CurrSt, Ta, Tb 3 3 CurrSt comb 2 Register 2 This NextSt becomes a new CurrSt Compute NextSt Current State input Next State CurrSt <= NextSt FSM Overview (A) 26 6/9/8

27 Finding FF Inputs Next State Current State uring the t th clock edge period, Comb Next State Logic Compute the next state (t+) using the current state (t) and other external inputs Place it to FF inputs After the next clock edge, (t+) th, the computed next state (t+) becomes the current state FSM inputs FSM Overview (A) 27 6/9/8

28 Method of Finding FF Inputs 3: 3: (t+) (t+2) (t+3) (t+4) (t+5) (t+6) (t) (t+) (t+2) (t+3) (t+4) (t+5) Find the boolean functions 3, 2,, in terms of 3, 2,,, and external FSM inputs for all possible cases. FSM Inputs (t+) (t) + Inputs Current State (t) input Next State (t+) FSM Overview (A) 28 6/9/8

29 State Transition 3: 3: (t+) (t) (t+) Compute the next state using the current state and external inputs in the current clock cycle (t+) comb Register (t) Inputs FSM Inputs Next State Current State FSM Overview (A) 29 After the next clock edge, the computed next state (FF Inputs) becomes the current state (FF Outputs) 6/9/8

30 Traffic Lights Example FSM Overview (A) 3 6/9/8

31 FSM Inputs and Outputs L B Traffic Lights - Outputs L A L B T B Sensor - Inputs L A T A T A L A T A T B T B L B FSM Overview (A) 3 6/9/8

32 Four States T A = L B L B L A L A T A = L A L A L B L B GR YR T B = L B L B L A L A T B = L A L A L B L B RY RG FSM Overview (A) 32 6/9/8

33 State Transition iagrams and Tables GR T A = T A = YR S S T A T B S' S' X X X X X X X X S S 2 L A L A L B L B RY T B = RG G Y R R R R G Y T B = G: Y: R: FSM Overview (A) 33 6/9/8

34 Next State Functions S and S 2 S S T A T B S' S' S S T A T B S' X X X X X X X X S S S S T B S S T B X X X X X X X X S' = S S + S S = S + S S S T A T B S' S' = S + S S' = S S T A + S S T B S S T A S S T B X X X X X X X X S' = S S T A + S S T B FSM Overview (A) 34 6/9/8

35 Output Functions : L A, L A, L B, L B S S 2 L A L A L B L B S S 2 L A S S 2 L A L A =S L A =S S L A =S L A =S S L B =S L B =S S S S 2 L B S S 2 L B L B =S L B =S S FSM Overview (A) 35 6/9/8

36 Moore FSM inputs T A NextSt gate delay Compute NextSt from CurrSt, Ta, Tb T B Next State S' Current State S CurrSt This NextSt becomes a new CurrSt clk S' states : S : S : S2 : S3 S S S outputs L A L A L B L B outputs (LA/LB) : Green : Yellow : Red : X Compute NextSt CurrSt <= NextSt FSM Overview (A) 36 6/9/8

37 Moore FSM Implementation inputs T A Inputs T A T B T B Current State S S Next State S' Current State S' S S' = S + S Next States clk states : S : S : S2 : S3 S S S S' = S S T A + S S T B L A =S L A =S S L B =S L B =S S outputs S' = S + S S' = S S T A + S S T B Current State S S L A L A L Outputs B L L A =S L B B=S L A =S S L B =S S outputs (LA/LB) : Green : Yellow : Red : X FSM Overview (A) 37 6/9/8

38 Next State Functions S and S 2 S S T A T B S' S' X X X X X Current State FSM Inputs Next State (S S ) (T A T B ) (S S ) X X X {,,,} {,,,} {,,,} S' = S + S S' = S S T A + S S T B FSM Overview (A) 38 6/9/8

39 Cartesian Product S S T A T B S' S' X X X X X X X X Current State FSM Inputs Next State (S S ) (T A T B ) (S S ) {,,,} {,,,} {,,,} S S T A T B S' S' FSM Overview (A) 39 6/9/8

40 Output Functions : L A, L A, L B, L B S S 2 L A L A L B L B Current State (S S ) FSM Output (L A, L A, L B, L B ) G : Y : R : {,,, } {,,,} L A =S L A =S S L B =S L B =S S FSM Overview (A) 4 6/9/8

41 Moore FSM FSM Inputs Next State Current State FSM Outputs Next State Combinational Logic State Register Output Combinational Logic clock FSM Overview (A) 4 6/9/8

42 Mealy FSM FSM Inputs Next State Current State FSM Outputs Next State Combinational Logic State Register Output Combinational Logic clock FSM Overview (A) 42 6/9/8

43 State iagram ST2 ST ST time E: Entry Action active output moore X: Exit Action active output moore I: Input Action active output mealy state output FSM Overview (A) 43 6/9/8

44 Acceptors Acceptor FSM: parsing the string "nice" FSM Overview (A) 44 6/9/8

45 Recognizers Representation of a finite-state machine; determines whether a binary number has an even number of s, where S is an accepting state. FSM Overview (A) 45 6/9/8

46 Classifiers A classifier is a generalization of a finite state machine that, similar to an acceptor, produces a single output on termination but has more than two terminal states FSM Overview (A) 46 6/9/8

47 Transducers Transducers generate output based on a given input and/or a state using actions. They are used for control applications and in the field of computational linguistics. FSM Overview (A) 47 6/9/8

48 Acceptors, Recognizers, Transducers acceptors: either accept the input or not recognizers: either recognize the input transducers: generate output from given input FSM Overview (A) 48 6/9/8

49 General Transducers Transducers are used in electronic communications systems to convert signals of various physical forms to electronic signals, and vice versa. In this example, the first transducer could be a microphone, and the second transducer could be a speaker. FSM Overview (A) 49 6/9/8

50 Transducers : Moore and Mealy Machines Fig. 7 Transducer FSM: Mealy model example There are two input actions (I:): "start motor to close the door if command_close arrives" Fig. 6 Transducer FSM: Moore model example "start motor in the other direction to open the door if command_open arrives". FSM Overview (A) 5 6/9/8

51 Moore machine example output does not depend on inputs FSM Overview (A) 5 6/9/8

52 Mealy machine input / output output does depend on inputs FSM Overview (A) 52 6/9/8

53 Mathematical Model transducers () A finite-state transducer is a sextuple (Σ, Γ, S, s, δ, ω), where: Σ is the input alphabet (a finite non-empty set of symbols). Γ is the output alphabet (a finite, non-empty set of symbols). S is a finite, non-empty set of states. s is the initial state, an element of S. δ is the state-transition function: δ : S Σ S ω is the output function. Moore machine : ω : S Γ Mealy machine : ω : S Σ Γ (Σ, Γ, S, s, δ, ω) (I, O, S, f, g, σ) FSM Overview (A) 53 6/9/8

54 Mathematical Model transducers (2) If the output function is a function of a state and input alphabet (ω : S Σ Γ) that definition corresponds to the Mealy model, and can be modelled as a Mealy machine. If the output function depends only on a state (ω : S Γ) that definition corresponds to the Moore model, and can be modelled as a Moore machine. A finite-state machine with no output function at all is known as a semiautomaton or transition system. FSM Overview (A) 54 6/9/8

55 Mathematical Models acceptors A deterministic finite state machine or acceptor deterministic finite state machine is a quintuple (Σ, S, s, δ, F), where: output set {, } Σ is the input alphabet (a finite, non-empty set of symbols). S is a finite, non-empty set of states. s is an initial state, an element of S. δ is the state-transition function: δ : S Σ S F is the set of final states, a (possibly empty) subset of S. output function ω A set of accepted states FSM Overview (A) 55 6/9/8

56 Finite State Tranducers and Acceptors limited finite state machine (Σ, S, δ) finite state acceptor (Σ, S, s, δ, F) finite-state transducer (Σ, Γ, S, s, δ, ω) Finite State Automaton (FSA) Finite State Machine (FSM) Σ is the input alphabet (a finite non-empty set of symbols). S is a finite, non-empty set of states. δ is the state-transition function: δ : S Σ S s is the initial state, an element of S. F is the set of final states, a (possibly empty) subset of S. Γ is the output alphabet (a finite, non-empty set of symbols). ω is the output function. FSM Overview (A) 56 6/9/8

57 References [] [2] 6/9/8