Chapter 3. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 3 <1>
|
|
- Thomasine Butler
- 5 years ago
- Views:
Transcription
1 Chapter 3 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 3 <1>
2 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic Design Finite State Machines Timing of Sequential Logic Parallelism Chapter 3 <2>
3 Introduction Outputs of sequential logic depend on current and prior input values it has memory. Some definitions: State: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state Synchronous sequential circuits: combinational logic followed by a bank of flip-flops Chapter 3 <3>
4 Sequential Circuits Give sequence to events Have memory (short-term) Use feedback from output to input to store information Chapter 3 <4>
5 State Elements The state of a circuit influences its future behavior State elements store state Bistable circuit SR Latch D Latch D Flip-flop Chapter 3 <5>
6 Bistable Circuit Fundamental building block of other state elements Two outputs:, No inputs I2 I1 I1 I2 Chapter 3 <6>
7 Bistable Circuit Analysis Consider the two possible cases: = 0: then = 1, = 0 (consistent) 1 I1 0 0 I2 1 = 1: then = 0, = 1 (consistent) 0 I1 1 1 I2 0 Stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state Chapter 3 <7>
8 SR (Set/Reset) Latch SR Latch R N1 S N2 Consider the four possible cases: S = 1, R = 0 S = 0, R = 1 S = 0, R = 0 S = 1, R = 1 Chapter 3 <8>
9 SR Latch Analysis S = 1, R = 0: then = 1 and = 0 R 0 0 N1 1 S 0 1 N2 0 S = 0, R = 1: then = 1 and = 0 R 1 1 N1 0 S 0 0 N2 1 Chapter 3 <9>
10 SR Latch Analysis S = 1, R = 0: then = 1 and = 0 R 0 0 N1 1 Set the output S 0 1 N2 0 S = 0, R = 1: then = 1 and = 0 Reset the output R S N1 N2 0 1 Chapter 3 <10>
11 SR Latch Analysis S = 0, R = 0: prev = 0 prev = 1 then = prev R 0 N1 0 R 0 N1 1 S 0 N2 S 0 N2 S = 1, R = 1: then = 0, = 0 R S N1 N2 0 0 Chapter 3 <11>
12 SR Latch Analysis S = 0, R = 0: prev = 0 prev = 1 then = prev Memory! R 0 N1 0 R 0 N1 S 0 N2 S 0 N2 S = 1, R = 1: then = 0, = 0 Invalid State NOT R S N1 N2 0 0 Chapter 3 <12>
13 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R = 0, = 1) Reset: Make the output 0 (S = 0, R = 1, = 0) SR Latch Symbol R S Chapter 3 <13>
14 D Latch Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (transparent) When = 0, holds its previous value (opaque) Avoids invalid case when NOT Chapter 3 <14> D Latch Symbol D
15 D Latch Internal Circuit D R R D S S D D 0 X D S R Chapter 3 <15>
16 D Latch Internal Circuit D R R D S S D D 0 X D X 1 0 S R 0 0 prev prev Chapter 3 <16>
17 D Flip-Flop Inputs:, D Function Samples D on rising edge of When rises from 0 to 1, D passes through to Otherwise, holds its previous value changes only on rising edge of Called edge-triggered Activated on the clock edge D D Flip-Flop Symbols Chapter 3 <17>
18 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = 0 L1 is transparent L2 is opaque D passes through to N1 When = 1 L2 is transparent L1 is opaque N1 passes through to D D L1 N1 D L2 Thus, on the edge of the clock (when rises from 0 1) D passes through to Chapter 3 <18>
19 D Latch vs. D Flip-Flop D D D (latch) (flop) Chapter 3 <19>
20 D Latch vs. D Flip-Flop D D D (latch) (flop) Chapter 3 <20>
21 Registers D 0 D 0 D 1 D 1 D 3: :0 D 2 D 2 D 3 D 3 Chapter 3 <21>
22 Enabled Flip-Flops Inputs:, D, EN The enable input (EN) controls when new data (D) is stored Function EN = 1: D passes through to on the clock edge EN = 0: the flip-flop retains its previous state EN Internal Circuit Symbol D 0 1 D D EN Chapter 3 <22>
23 Resettable Flip-Flops Inputs:, D, Reset Function: Reset = 1: is forced to 0 Reset = 0: flip-flop behaves as ordinary D flip-flop Symbols D Reset r Chapter 3 <23>
24 Resettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when Reset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? Chapter 3 <24>
25 Resettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when Reset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop Synchronously resettable flip-flop? Internal Circuit D Reset D Chapter 3 <25>
26 Settable Flip-Flops Inputs:, D, Set Function: Set = 1: is set to 1 Set = 0: the flip-flop behaves as ordinary D flip-flop Symbols D Set s Chapter 3 <26>
27 Sequential Logic Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z X Y Z time (ns) Chapter 3 <27>
28 Sequential Logic Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z X Y Z time (ns) No inputs and 1-3 outputs Astable circuit, oscillates Period depends on inverter delay It has a cyclic path: output fed back to input Chapter 3 <28>
29 Synchronous Sequential Logic Design Breaks cyclic paths by inserting registers Registers contain state of the system State changes at clock edge: system synchronized to the clock Rules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite State Machines (FSMs) Pipelines Chapter 3 <29>
30 Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State Current State Next State Logic Output Logic C L Next State C L Outputs Chapter 3 <30>
31 Finite State Machines (FSMs) Next state determined by current state and inputs Two types of finite state machines differ in output logic: Moore FSM: outputs depend only on current state Mealy FSM: outputs depend on current state and inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM inputs M next state logic k next state k state output logic N outputs Chapter 3 <31>
32 FSM Black Box Inputs:, Reset, T A, T B Outputs: L A, L B T A T B Traffic Light Controller L A L B Reset Chapter 3 <33>
33 FSM Example Traffic light controller Traffic sensors: T A, T B (TRUE when there s traffic) Lights: L A, L B Academic Labs L A T A Bravado Blvd. T B T B Dining Hall L B L A T A L B Fields Ave. Dorms Chapter 3 <32>
34 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs Reset S0 L A : green L B : red Chapter 3 <34>
35 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs Reset S0 L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow T B S2 L A : red L B : green T B Chapter 3 <35>
36 FSM State Transition Table Current State Inputs Next State S T A T B S' S0 0 X S0 1 X S1 X X S2 X 0 S2 X 1 S3 X X Chapter 3 <36>
37 FSM State Transition Table Current State Inputs Next State S T A T B S' S0 0 X S1 S0 1 X S0 S1 X X S2 S2 X 0 S3 S2 X 1 S2 S3 X X S0 Chapter 3 <37>
38 FSM Encoded State Transition Table Current State Inputs Next State S 1 S 0 T A T B S' 1 S' X X 0 1 X X 1 0 X X X X State Encoding S0 00 S1 01 S2 10 S3 11 Chapter 3 <38>
39 FSM Encoded State Transition Table Current State Inputs Next State S 1 S 0 T A T B S' 1 S' X X X X X X X X 0 0 State Encoding S0 00 S1 01 S2 10 S3 11 S' 1 = S 1 Å S 0 S' 0 = S 1 S 0 T A + S 1 S 0 T B Chapter 3 <39>
40 FSM Output Table Current State Outputs S 1 S 0 L A1 L A0 L B1 L B Output Encoding green 00 yellow 01 red 10 Chapter 3 <40>
41 FSM Output Table Current State Outputs S 1 S 0 L A1 L A0 L B1 L B Output Encoding green 00 yellow 01 red 10 L A1 = S 1 L A0 = S 1 S 0 L B1 = S 1 L B0 = S 1 S 0 Chapter 3 <41>
42 FSM Schematic: State Register S' 1 S 1 S' 0 r Reset S 0 state register Chapter 3 <42>
43 FSM Schematic: Next State Logic S' 1 S 1 T A T B S' 0 r Reset S 0 S 1 S 0 inputs next state logic state register Chapter 3 <43>
44 FSM Schematic: Output Logic L A1 S' 1 S 1 L A0 T A S' 0 r S 0 L B1 T B Reset S 1 S 0 L B0 inputs next state logic state register output logic outputs Chapter 3 <44>
45 FSM Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Reset T A T B S' 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01) S 1:0?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) L A1:0?? Green (00) Yellow (01) Red (10) Green (00) L B1:0?? Red (10) Green (00) Yellow (01) Red (10) t (sec) Reset S0 L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow T B T B S2 L A : red L B : green Chapter 3 <45>
46 FSM State Encoding Binary encoding: i.e., for four states, 00, 01, 10, 11 One-hot encoding One state bit per state Only one state bit HIGH at once i.e., for 4 states, 0001, 0010, 0100, 1000 Requires more flip-flops Often next state and output logic is simpler Chapter 3 <46>
47 Moore vs. Mealy FSM Alyssa P. Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it. The snail smiles whenever the last two digits it has crawled over are 01. Design Moore and Mealy FSMs of the snail s brain. Chapter 3 <47>
48 State Transition Diagrams Moore FSM Reset 0 1 S S S2 1 Mealy FSM Reset 0/0 S0 1/0 0/0 S1 1/1 Mealy FSM: arcs indicate input/output Chapter 3 <48>
49 Moore FSM State Transition Table Current State Inputs Next State State Encoding S 1 S 0 A S' 1 S' S0 00 S1 01 S Chapter 3 <49>
50 Moore FSM State Transition Table Current State Inputs Next State State Encoding S 1 S 0 A S' 1 S' S0 00 S1 01 S S 1 = S 0 A S 0 = A Chapter 3 <50>
51 Moore FSM Output Table Current State Output S 1 S 0 Y Chapter 3 <51>
52 Moore FSM Output Table Current State Output S 1 S 0 Y Y = S 1 Chapter 3 <52>
53 Mealy FSM State Transition & Output Table Current State Input Next State Output S 0 A S' 0 Y State Encoding S0 00 S1 01 Chapter 3 <53>
54 Mealy FSM State Transition & Output Table Current State Input Next State Output S 0 A S' 0 Y State Encoding S0 00 S1 01 Chapter 3 <54>
55 Moore FSM Schematic A S' 1 S 1 Y S' 0 S 0 r Reset Chapter 3 <55>
56 Mealy FSM Schematic A S' 0 S 0 Y r Reset Chapter 3 <56>
57 Moore & Mealy Timing Diagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 Reset A S Y S Moore Machine?? S0 S1 S2 S1 S2 S0 S1 S2 S0 Mealy Machine?? S0 S1 S0 S1 S0 S1 S0 Y Chapter 3 <57>
58 Factoring State Machines Break complex FSMs into smaller interacting FSMs Example: Modify traffic light controller to have Parade Mode. Two more inputs: P, R When P = 1, enter Parade Mode & Bravado Blvd light stays green When R = 1, leave Parade Mode Chapter 3 <58>
59 Parade FSM Unfactored FSM P R T A T B Controller FSM L A L B Factored FSM P R Mode FSM M T A T B Lights FSM L A L B Controller FSM Chapter 3 <59>
60 Unfactored FSM PT A Reset S0 L A : green L B : red P P S3 L A : red L B : yellow T A P PT A P P T B T A P T B S1 L A : yellow L B : red P S2 L A : red L B : green P RT A RT A R S4 L A : green L B : red R S7 L A : red L B : yellow R T A R T A R S5 L A : yellow L B : red R S6 L A : red L B : green P R RT B RT B Chapter 3 <60>
61 Factored FSM Reset S0 L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow MT B S2 L A : red L B : green Reset S0 M: 0 P P R S1 M: 1 M + T B R Lights FSM Mode FSM Chapter 3 <61>
62 FSM Design Procedure 1. Identify inputs and outputs 2. Sketch state transition diagram 3. Write state transition table 4. Select state encodings 5. For Moore machine: 1. Rewrite state transition table with state encodings 2. Write output table 6. For a Mealy machine: 1. Rewrite combined state transition and output table with state encodings 7. Write Boolean equations for next state and output logic 8. Sketch the circuit schematic Chapter 3 <62>
63 Timing Flip-flop samples D at clock edge D must be stable when sampled Similar to a photograph, D must be stable around clock edge If not, metastability can occur Chapter 3 <63>
64 Input Timing Constraints Setup time: t setup = time before clock edge data must be stable (i.e. not changing) Hold time: t hold = time after clock edge data must be stable Aperture time: t a = time around clock edge data must be stable (t a = t setup + t hold ) D t setup t hold t a Chapter 3 <64>
65 Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that might be unstable (i.e., start changing) t ccq t pcq Chapter 3 <65>
66 Dynamic Discipline Synchronous sequential circuit inputs must be stable during aperture (setup and hold) time around clock edge Specifically, inputs must be stable at least t setup before the clock edge at least until t hold after the clock edge Chapter 3 <66>
67 Dynamic Discipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements 1 C L D2 (a) R1 R2 T c 1 D2 (b) Chapter 3 <67>
68 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge 1 C L D2 T c R1 R2 T c 1 D2 t pcq t pd t setup Chapter 3 <68>
69 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge R1 1 C L T c D2 R2 T c t pcq + t pd + t setup t pd 1 D2 t pcq t pd t setup Chapter 3 <69>
70 Setup Time Constraint Depends on the maximum delay from register R1 through combinational logic to R2 The input to register R2 must be stable at least t setup before clock edge R1 1 C L T c D2 R2 T c t pcq + t pd + t setup t pd T c (t pcq + t setup ) 1 D2 (t pcq + t setup ): sequencing overhead t pcq t pd t setup Chapter 3 <70>
71 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge R1 1 C L D2 R2 t hold < 1 D2 t ccq t cd t hold Chapter 3 <71>
72 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge R1 1 C L D2 R2 t hold < t ccq + t cd t cd > 1 D2 t ccq t cd t hold Chapter 3 <72>
73 Hold Time Constraint Depends on the minimum delay from register R1 through the combinational logic to R2 The input to register R2 must be stable for at least t hold after the clock edge 1 D2 R1 1 C L D2 R2 t hold < t ccq + t cd t cd > t hold - t ccq t ccq t cd t hold Chapter 3 <73>
74 Timing Analysis A Timing Characteristics t ccq = 30 ps B C X' X t pcq = 50 ps t setup = 60 ps t hold = 70 ps D t pd = t cd = Setup time constraint: T c f c = Y' Y per gate t pd t cd Hold time constraint: t ccq + t cd > t hold? = 35 ps = 25 ps Chapter 3 <74>
75 Timing Analysis A Timing Characteristics t ccq = 30 ps B C X' X t pcq = 50 ps t setup = 60 ps t hold = 70 ps D t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y' Y per gate t pd t cd = 35 ps = 25 ps Hold time constraint: t ccq + t cd > t hold? ( ) ps > 70 ps? No! Chapter 3 <75>
76 Timing Analysis Add buffers to the short paths: A Timing Characteristics t ccq t pcq = 30 ps = 50 ps B t setup = 60 ps C X' X t hold = 70 ps D t pd = Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = Setup time constraint: Hold time constraint: T c t ccq + t cd > t hold? f c = Chapter 3 <76>
77 Timing Analysis Add buffers to the short paths: A Timing Characteristics t ccq t pcq = 30 ps = 50 ps B t setup = 60 ps C X' X t hold = 70 ps D t pd = 3 x 35 ps = 105 ps Y' Y per gate t pd t cd = 35 ps = 25 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: Hold time constraint: T c ( ) ps = 215 ps t ccq + t cd > t hold? f c = 1/T c = 4.65 GHz ( ) ps > 70 ps? Yes! Chapter 3 <77>
78 Clock Skew The clock doesn t arrive at all registers at same time Skew: difference between two clock edges Perform worst case analysis to guarantee dynamic discipline is not violated for any register many registers in a system! delay 1 R1 1 C L D2 R2 2 t skew 1 2 Chapter 3 <78>
79 Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 1 C L T c D2 2 R2 1 2 T c 1 D2 t pcq t pd t setup t skew Chapter 3 <79>
80 Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 1 C L T c D2 2 R T c t pcq + t pd + t setup + t skew t pd D2 t pcq t pd t setup t skew Chapter 3 <80>
81 Setup Time Constraint with Skew In the worst case, 2 is earlier than 1 1 R1 1 C L T c D2 2 R T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) D2 t pcq t pd t setup t skew Chapter 3 <81>
82 Hold Time Constraint with Skew In the worst case, 2 is later than C D2 L R1 R2 1 2 t ccq + t cd > 1 D2 t ccq t cd t skew t hold Chapter 3 <82>
83 Hold Time Constraint with Skew In the worst case, 2 is later than C D2 L R1 R t ccq + t cd > t hold + t skew t cd > D2 t ccq t cd t skew t hold Chapter 3 <83>
84 Hold Time Constraint with Skew In the worst case, 2 is later than C D2 L R1 R t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq D2 t ccq t cd t skew t hold Chapter 3 <84>
85 Violating the Dynamic Discipline Asynchronous (for example, user) inputs might violate the dynamic discipline button D D t setup t hold t aperture Case I D Case II D??? Case III Chapter 3 <85>
86 Metastability Bistable devices: two stable states, and a metastable state between them Flip-flop: two stable states (1 and 0) and one metastable state If flip-flop lands in metastable state, could stay there for an undetermined amount of time metastable stable stable Chapter 3 <86>
87 Flip-Flop Internals Flip-flop has feedback: if is somewhere between 1 and 0, cross-coupled gates drive output to either rail (1 or 0) R N1 S N2 Metastable signal: if it hasn t resolved to 1 or 0 If flip-flop input changes at random time, probability that output is metastable after waiting some time, t: P(t res > t) = (T 0 /T c ) e -t/τ t res : time to resolve to 1 or 0 T 0, τ : properties of the circuit Chapter 3 <87>
88 Metastability Intuitively: T 0 /T c : probability input changes at a bad time (during aperture) P(t res > t) = (T 0 /T c ) e -t/τ τ: time constant for how fast flip-flop moves away from metastability P(t res > t) = (T 0 /T c ) e -t/τ In short, if flip-flop samples metastable input, if you wait long enough (t), the output will have resolved to 1 or 0 with high probability. Chapter 3 <88>
89 Synchronizers Asynchronous inputs are inevitable (user interfaces, systems with different clocks interacting, etc.) Synchronizer goal: make the probability of failure (the output still being metastable) low Synchronizer cannot make the probability of failure 0 D SYNC Chapter 3 <89>
90 Synchronizer Internals Synchronizer: built with two back-to-back flip-flops Suppose D is transitioning when sampled by F1 Internal signal D2 has (T c - t setup ) time to resolve to 1 or 0 D2 D F1 F2 T c D2 metastable t res t setup t pcq Chapter 3 <90>
91 Synchronizer Probability of Failure For each sample, probability of failure is: P(failure) = (T 0 /T c ) e -(T c - t setup )/τ D F1 D2 T c F2 D2 metastable t res t setup t pcq Chapter 3 <91>
92 Synchronizer Mean Time Between Failures If asynchronous input changes once per second, probability of failure per second is P(failure). If input changes N times per second, probability of failure per second is: P(failure)/second = (NT 0 /T c ) e -(T c - t setup )/τ Synchronizer fails, on average, 1/[P(failure)/second] Called mean time between failures, MTBF: MTBF = 1/[P(failure)/second] = (T c /NT 0 ) e (T c - t setup )/τ Chapter 3 <92>
93 Example Synchronizer D D2 F1 F2 Suppose: T c = 1/500 MHz = 2 ns τ = 200 ps T 0 = 150 ps t setup = 100 ps N = 10 events per second What is the probability of failure? MTBF? Chapter 3 <93>
94 Example Synchronizer D D2 F1 F2 Suppose: T c = 1/500 MHz = 2 ns τ = 200 ps T 0 = 150 ps t setup = 100 ps N = 10 events per second What is the probability of failure? MTBF? P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps = P(failure)/second = 10 ( ) MTBF = / second = 1/[P(failure)/second] 5 hours Chapter 3 <94>
95 Parallelism Two types of parallelism: Spatial parallelism duplicate hardware performs multiple tasks at once Temporal parallelism task is broken into multiple stages also called pipelining for example, an assembly line Chapter 3 <95>
96 Parallelism Definitions Token: Group of inputs processed to produce group of outputs Latency: Time for one token to pass from start to end Throughput: Number of tokens produced per unit time Parallelism increases throughput Chapter 3 <96>
97 Parallelism Example Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 15 minutes to bake What is the latency and throughput without parallelism? Chapter 3 <97>
98 Parallelism Example Ben Bitdiddle bakes cookies to celebrate traffic light controller installation 5 minutes to roll cookies 15 minutes to bake What is the latency and throughput without parallelism? Latency = = 20 minutes = 1/3 hour Throughput = 1 tray/ 1/3 hour = 3 trays/hour Chapter 3 <98>
99 Parallelism Example What is the latency and throughput if Ben uses parallelism? Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own oven Temporal parallelism: two stages: rolling and baking He uses two trays While first batch is baking, he rolls the second batch, etc. Chapter 3 <99>
100 Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Roll Bake Legend Time Latency =? Throughput =? Chapter 3 <100>
101 Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Roll Bake Legend Time Latency = = 20 minutes = 1/3 hour Throughput = 2 trays/ 1/3 hour = 6 trays/hour Chapter 3 <101>
102 Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency =? Throughput =? Chapter 3 <102>
103 Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency = = 20 minutes = 1/3 hour Throughput = 1 trays/ 1/4 hour = 4 trays/hour Using both techniques, the throughput would be 8 trays/hour Chapter 3 <103>
Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits
Chapter 3 Chapter 3 :: Topics igital esign and Computer Architecture, 2 nd Edition avid Money Harris and Sarah L. Harris Introduction Latches and Flip Flops Synchronous Logic esign Finite State Machines
More informationCPE100: Digital Logic Design I
Chapter 3 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe1/ CPE1: Digital Logic Design I Section 14: Dr. Morris Sequential Logic Design Chapter 3 Chapter
More informationFinite State Machine (FSM)
Finite State Machine (FSM) Consists of: State register Stores current state Loads next state at clock edge Combinational logic Computes the next state Computes the outputs S S Next State CLK Current State
More informationSynchronous Sequential Circuit Design. Digital Computer Design
Synchronous Sequential Circuit Design Digital Computer Design Races and Instability Combinational logic has no cyclic paths and no races If inputs are applied to combinational logic, the outputs will always
More informationDifferent encodings generate different circuits
FSM State Encoding Different encodings generate different circuits no easy way to find best encoding with fewest logic gates or shortest propagation delay. Binary encoding: K states need log 2 K bits i.e.,
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Final Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Tuesday Dec 12 th 13:00-15:00 (1-3pm) 2 hour
More informationALU, Latches and Flip-Flops
CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades
More informationTiming Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid
Timing Constraints in Sequential esigns 63 Sources: TSR, Katz, Boriello & Vahid Where we are now. What we covered last time: FSMs What we ll do next: Timing constraints Upcoming deadlines: ZyBook today:
More informationLecture 10: Sequential Networks: Timing and Retiming
Lecture 10: Sequential Networks: Timing and Retiming CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego
More informationSequential Logic. Handouts: Lecture Slides Spring /27/01. L06 Sequential Logic 1
Sequential Logic Handouts: Lecture Slides 6.4 - Spring 2 2/27/ L6 Sequential Logic Roadmap so far Fets & voltages Logic gates Combinational logic circuits Sequential Logic Voltage-based encoding V OL,
More informationCSE140: Design of Sequential Logic
CSE4: Design of Sequential Logic Instructor: Mohsen Imani Flip Flops 2 Counter 3 Up counter 4 Up counter 5 FSM with JK-Flip Flop 6 State Table 7 State Table 8 Circuit Minimization 9 Circuit Timing Constraints
More informationCPE100: Digital Logic Design I
Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu CPE100: Digital Logic Design I Midterm02 Review http://www.ee.unlv.edu/~b1morris/cpe100/ 2 Logistics Thursday Nov. 16 th In normal lecture (13:00-14:15)
More informationProblem Set 9 Solutions
CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits - A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationSequential Logic. Road Traveled So Far
Comp 2 Spring 25 2/ Lecture page Sequential Logic These must be the slings and arrows of outrageous fortune ) Synchronous as an implementation of Sequential 2) Synchronous Timing Analysis 3) Single synchronous
More informationJin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan
Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University it Jungli, Taiwan Outline Latches & Registers Sequencing Timing
More informationDesigning Sequential Logic Circuits
igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was
More information6. Finite State Machines
6. Finite State Machines 6.4x Computation Structures Part Digital Circuits Copyright 25 MIT EECS 6.4 Computation Structures L6: Finite State Machines, Slide # Our New Machine Clock State Registers k Current
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance
More informationLecture 7: Sequential Networks
CSE 140: Components and Design Techniques for Digital Systems Lecture 7: Sequential Networks CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1 Part II: Sequential
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationChapter 7 Sequential Logic
Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics
More informationAdders, subtractors comparators, multipliers and other ALU elements
CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing
More information5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were
More informationCh 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1
Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationLatches. October 13, 2003 Latches 1
Latches The second part of CS231 focuses on sequential circuits, where we add memory to the hardware that we ve already seen. Our schedule will be very similar to before: We first show how primitive memory
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br
More informationEECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007
EECS 150 - Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler
More informationSequential Logic Design: Controllers
Sequential Logic Design: Controllers Controller Design, Flip Flop Timing Copyright (c) 2012 Sean Key Standard Controller Architecture Controller A circuit that implements a FSM is referred to as a controller
More informationHomework #4. CSE 140 Summer Session Instructor: Mohsen Imani. Only a subset of questions will be graded
Homework #4 CSE 140 Summer Session 2 2017 Instructor: Mohsen Imani Only a subset of questions will be graded 1) For the circuit shown below, do the following: a. Write a logic equation for the output P
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More informationLecture 10: Synchronous Sequential Circuits Design
Lecture 0: Synchronous Sequential Circuits Design. General Form Input Combinational Flip-flops Combinational Output Circuit Circuit Clock.. Moore type has outputs dependent only on the state, e.g. ripple
More informationMemory Elements I. CS31 Pascal Van Hentenryck. CS031 Lecture 6 Page 1
Memory Elements I CS31 Pascal Van Hentenryck CS031 Lecture 6 Page 1 Memory Elements (I) Combinational devices are good for computing Boolean functions pocket calculator Computers also need to remember
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Final Stephen A. Edwards Columbia University Summer 25 The Final 2 hours 8 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationDigital Design. Sequential Logic
Principles Of igital esign Chapter 6 Sequential Logic Chapter preview Boolean algebra 3 Logic gates and flip-flops 3 Finite-state machine 6 Logic design techniques 4 Sequential design techniques 6 Binary
More informationEXPERIMENT Traffic Light Controller
11.1 Objectives EXPERIMENT 11 11. Traffic Light Controller Practice on the design of clocked sequential circuits. Applications of sequential circuits. 11.2 Overview In this lab you are going to develop
More informationSequential Circuits. Circuits with state. Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. L06-1
Sequential Circuits Circuits with state Silvina Hanono Wachman Computer Science & Artificial Intelligence Lab M.I.T. L06-1 Combinational circuits A 0 A 1 A n-1. Sel lg(n) O Mux A B Comparator Result: LT,
More informationSynchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1
Synchronous Sequential Circuit Design Dr. Ehab A. H. AL-Hialy Page Motivation Analysis of a few simple circuits Generalizes to Synchronous Sequential Circuits (SSC) Outputs are Function of State (and Inputs)
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Review for the Midterm Stephen A. Edwards Columbia University Spring 22 The Midterm 75 minutes 4 5 problems Closed book Simple calculators are OK, but unnecessary One double-sided
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University
More informationSequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
More informationTopic 8: Sequential Circuits
Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the
More informationSequential logic and design
Principles Of Digital Design Sequential logic and design Analysis State-based (Moore) Input-based (Mealy) FSM definition Synthesis State minimization Encoding Optimization and timing Copyright 20-20by
More informationKing Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department
King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department Page 1 of 13 COE 202: Digital Logic Design (3-0-3) Term 112 (Spring 2012) Final
More informationState and Finite State Machines
State and Finite State Machines See P&H Appendix C.7. C.8, C.10, C.11 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)
ELEC 2200-002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationCSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013
CSE 140 Midterm 2 - Solutions Prof. Tajana Simunic Rosing Spring 2013 Do not start the exam until you are told. Write your name and PID at the top of every page. Do not separate the pages. Turn off and
More informationSequential Logic Worksheet
Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet
More informationModels for representing sequential circuits
Sequential Circuits Models for representing sequential circuits Finite-state machines (Moore and Mealy) Representation of memory (states) Changes in state (transitions) Design procedure State diagrams
More informationBER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO
UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a
More informationState & Finite State Machines
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Stateful Components Until now is combinatorial logic Output
More informationENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF
ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter Timing diagram of a DFF Lab 3 Gate Timing difference timing for difference kind of gate, cost dependence (1) Setup Time = t2-t1 (2) Propagation
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationDigital Design 2010 DE2 1
1 Underviser: D. M. Akbar Hussain Litteratur: Digital Design Principles & Practices 4 th Edition by yj John F. Wakerly 2 DE2 1 3 4 DE2 2 To enable students to apply analysis, synthesis and implementation
More informationState & Finite State Machines
State & Finite State Machines Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See P&H Appendix C.7. C.8, C.10, C.11 Big Picture: Building a Processor memory inst register file
More informationLecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
More informationIntroduction to Digital Logic
Introduction to Digital Logic Lecture 17: Latches Flip-Flops Problem w/ Bistables Output should have been at end of sequence Problem: Glitch was remembered Need some way to ignore inputs until they are
More informationY. Tsiatouhas. VLSI Systems and Computer Architecture Lab
CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Memory Elements and other Circuits ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview.
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson
More informationALU A functional unit
ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1
More informationMetastability. Introduction. Metastability. in Altera Devices
in Altera Devices May 1999, ver. 4 Application Note 42 Introduction The output of an edge-triggered flipflop has two valid states: high and low. To ensure reliable operation, designs must meet the flipflop
More informationChapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
More informationAppendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs
Appendix B Review of Digital Logic Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Elect. & Comp. Eng. 2 DeMorgan Symbols NAND (A.B) = A +B NOR (A+B) = A.B AND A.B = A.B = (A +B ) OR
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines 1 Clocks A microprocessor is composed of many different circuits that are operating simultaneously if each
More informationSynchronous Sequential Circuit
Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait
More informationI. Motivation & Examples
I. Motivation & Examples Output depends on current input and past history of inputs. State embodies all the information about the past needed to predict current output based on current input. State variables,
More informationEET 310 Flip-Flops 11/17/2011 1
EET 310 Flip-Flops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationLecture 9: Sequential Logic Circuits. Reading: CH 7
Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finite-state machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms
More informationENEL Digital Circuits Final Examination
Name: I#: Lecture Section: ENEL 353 - igital Circuits Final Examination Lecture sections : N. R. Bartley, MWF : :5, ENC 24 2: S. A. Norman, MWF : :5, ST 45 Wednesday, ecember 7, 24 Time: 7: PM : PM Locations:
More informationFundamentals of Digital Design
Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric
More informationUniversity of Minnesota Department of Electrical and Computer Engineering
University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Final Eam (Closed Book) Solutions Please enter your name, ID
More informationSequential Circuits Sequential circuits combinational circuits state gate delay
Sequential Circuits Sequential circuits are those with memory, also called feedback. In this, they differ from combinational circuits, which have no memory. The stable output of a combinational circuit
More information14.1. Unit 14. State Machine Design
4. Unit 4 State Machine Design 4.2 Outcomes I can create a state diagram to solve a sequential problem I can implement a working state machine given a state diagram STATE MACHINES OVERVIEW 4.3 4.4 Review
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationSynchronous Logic. These must be the slings and arrows of outrageous fortune. Comp 411 Fall /18/06. L14 Synchronous Logic 1
Synchronous Logic 1) Sequential Logic 2) Synchronous Design 3) Synchronous Timing Analysis 4) Single Clock Design 5) Finite State Machines 6) Turing Machines 7) What it means to be Computable These must
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and
More informationDigital Electronics Sequential Logic
/5/27 igital Electronics Sequential Logic r. I. J. Wassell Sequential Logic The logic circuits discussed previously are known as combinational, in that the output depends only on the condition of the latest
More informationCMPEN 411. Spring Lecture 18: Static Sequential Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationAppendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring
- Principles of Computer rchitecture Miles Murdocca and Vincent Heuring 999 M. Murdocca and V. Heuring -2 Chapter Contents. Introduction.2 Combinational Logic.3 Truth Tables.4 Logic Gates.5 Properties
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Synchronous Sequential Circuits Basic Design Steps CprE 281: Digital Logic Iowa State University, Ames,
More informationEEE2135 Digital Logic Design
EEE2135 Digital Logic Design Chapter 7. Sequential Circuits Design 서강대학교 전자공학과 1. Model of Sequential Circuits 1) Sequential vs. Combinational Circuits a. Sequential circuits: Outputs depend on both the
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationDigital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..
Indian Institute of Technology Jodhpur, Year 2017-2018 Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd.. Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationDesign of Datapath Controllers
Design of Datapath Controllers Speaker: 俞子豪 Adviser: Prof. An-Yeu Wu ACCESS IC LAB Outline vsequential Circuit Model vfinite State Machines vuseful Modeling Techniques P. 2 Model of Sequential Circuits
More informationLaboratory Exercise #8 Introduction to Sequential Logic
Laboratory Exercise #8 Introduction to Sequential Logic ECEN 248: Introduction to Digital Design Department of Electrical and Computer Engineering Texas A&M University 2 Laboratory Exercise #8 1 Introduction
More informationStop Watch (System Controller Approach)
Stop Watch (System Controller Approach) Problem Design a stop watch that can measure times taken for two events Inputs CLK = 6 Hz RESET: Asynchronously reset everything X: comes from push button First
More informationPreparation of Examination Questions and Exercises: Solutions
Questions Preparation of Examination Questions and Exercises: Solutions. -bit Subtraction: DIF = B - BI B BI BO DIF 2 DIF: B BI 4 6 BI 5 BO: BI BI 4 5 7 3 2 6 7 3 B B B B B DIF = B BI ; B = ( B) BI ( B),
More informationCPE/EE 422/522. Chapter 1 - Review of Logic Design Fundamentals. Dr. Rhonda Kay Gaede UAH. 1.1 Combinational Logic
CPE/EE 422/522 Chapter - Review of Logic Design Fundamentals Dr. Rhonda Kay Gaede UAH UAH Chapter CPE/EE 422/522. Combinational Logic Combinational Logic has no control inputs. When the inputs to a combinational
More informationAdders allow computers to add numbers 2-bit ripple-carry adder
Lecture 12 Logistics HW was due yesterday HW5 was out yesterday (due next Wednesday) Feedback: thank you! Things to work on: ig picture, ook chapters, Exam comments Last lecture dders Today Clarification
More informationChapter 14 Sequential logic, Latches and Flip-Flops
Chapter 14 Sequential logic, Latches and Flip-Flops Flops Lesson 4 JK Flip Flop Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 JK Flip-Flop ve edge triggered Output Q and
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationComputers also need devices capable of Storing data and information Performing mathematical operations on such data
Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable
More informationLecture 13: Sequential Circuits, FSM
Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,
More informationSequential Synchronous Circuit Analysis
Sequential Synchronous Circuit Analysis General Model Current State at time (t) is stored in an array of flip-flops. Next State at time (t+1) is a Boolean function of State and Inputs. Outputs at time
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More information