Digital Design 2010 DE2 1
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1 1 Underviser: D. M. Akbar Hussain Litteratur: Digital Design Principles & Practices 4 th Edition by yj John F. Wakerly 2 DE2 1
2 3 4 DE2 2
3 To enable students to apply analysis, synthesis and implementation of basic digital circuits. 5 Students can make analysis and should be able to design digital circuits which is a central feature of data or electrical engineering. 6 DE2 3
4 Multi-vibrators & Sequential circuits. Bi-stable Circuits, Structure of Mono-stable and A-stable circuits. Modeling, Analysis and Synthesizing of circuits. Mealy and Moore State Machines there analysis, design and realization. Counters and Shift Registers. 7 Modul 1 8 DE2 4
5 A circuit which is used to build most common two state systems, for example Oscillator, Timers and flip-flops. Astable: Circuit is not stable in either state and continuously oscillates from one state to the other and it does not require any input, for example clock etc. Monostable: Obviously as the name says it can have one stable state and one unstable state and it can flip into the unstable state for a determined period, but will eventually return to the stable state. Such a circuit is useful for creating a timing period of fixed duration in response to some external event. This circuit is also known as a one shot. Bistable: In such a circuit it will remain in one of the two states indefinitely. The circuit can be flipped from one state to the other by an external event or trigger. This type circuit is the fundamental building block of a register or memory device. This circuit is also known as a latch or a flip-flop DE2 5
6 Depend upon current input values as well as past sequence applied. A circuit with n binary state variables can have 2 n possible states. Always Finite Never Infinite 11 What is a FSM It is a quintuple (Σ, S, A, δ, F), where: Σ input alphabet (a finite set of symbols) S finite set of states A an initial state, an element of S δ the state transition function: δ: S x Σ S F set of final states, a subset of S. 12 DE2 6
7 13 Mealy & Moore Models Input Actions (State & Inputs) Entry Actions (State) 14 DE2 7
8 Clocked Synchronous State Machine (Mealy Machine) Next State = F (current state, input) Output = G (current state, input) 15 Clocked Synchronous State Machine (Moore Machine) Output = G (current state) 16 DE2 8
9 Mealy Machine with Pipelined Outputs DE2 9
10 Micro-Architecture Pipeline Stages Intel P5 (Pentium) 5 Intel P6 (Pentium Pro) 14 Intel P6 (Pentium III) 10 IBM PowerPC 7 17 IBM Xenon 19 AMD Athlon 10 AMD Athlon XP 11 AMD Athlon64 12 AMD Phenom 12 AMD Opteron Describing the function of a circuit: 20 DE2 10
11 Definition of a state machine: Next state = F (current state, input) Output = G (current state, input) 21 D0 = Q0 EN + Q0 EN D1 = Q1 EN + Q1 Q0 EN + Q1 Q0 EN 22 DE2 11
12 23 24 DE2 12
13 25 26 DE2 13
14 27 1. Determine the excitation equations for the flip-flops. flops. 2. Substitute them into the characteristics equations to get the transition equations. 3. Use the transition equations to construct a transition table. 4. Determine the output equations. 5. Create a transition/output table. 6. Name the states. 7. Draw a state diagram. 28 DE2 14
15 29 30 DE2 15
16 31 1. Construct a state / Output table. 2. If possible minimise the number of states. 3. Choose a set of state variable for state assignments. 4. Create a transition/output table by substituting state variable combinations into state/output table. 5. Select / Choose a flip flop, almost always it is D type flip flop. 6. Construct an excitation table, which shows the excitation values required to get to the next desired state for all possible state/input combinations. 7. Derive excitation equations from excitation table. 8. Derive output equations from the transition table. 9. Draw a logic diagram. 32 DE2 16
17 33 1. From this verbal description create/construct a state / Output table. 2. Minimise the number of states. The basic idea is that two or more states are equivalent if it is impossibleibl to distinguishi i by observing the current and future output of the machine. Typically, these techniques are rarely used, because some time increasing the number of states simplifies the design, most engineers simplify the machine during state assignment (next step). A B Q1Q2Q Z A B B C C 0 B D D C C 0 C B B E E 0 D D D E C 1 E B D E E 1 34 DE2 17
18 35 Minimal Risk Minimal Cost 36 DE2 18
19 37 Transition & Output Table 38 DE2 19
20 Excitation & Output Table 39 D1 = Q2. Q3 + Q1 D2 = Q1. Q3. A + Q1. Q3. A + Q1. Q2. B D3 = Q1. A + Q2. Q3. A Z = Q1. Q2. Q3 + Q1 Q2 Q3 Z = Q1. Q2 40 DE2 20
21 Design aclocked synchronous state machine with 2inputs X, Y and output Z. The output should be 1if the number of inputs on Xand Ysince reset is a multiple of 4and 0 otherwise DE2 21
22 D1 = Q2. X. Y + Q1. X. Y + Q1. X. Y + Q2. X. Y D2 = Q1. X. Y + Q1. X. Y + Q2. X. Y + Q2. X. Y Z = Q1. Q DE2 22
23 45 D1 = Q1. Q2. X + Q1. Q2. Q3 + Q1. Q2. Q3 D2 = Q2. Q3. X + Q2. Q3. X D3 = Q1. Q2. Q3 + Q1. Q3. X + Q2. X. + Q3. Q1. X + Q2. Q3. X 46 DE2 23
24 UNLK = Q1. Q2. Q3. X HINT = Q1. Q2. Q3. X + Q1. Q2. X + Q2. Q3. X + Q2. Q3. X + Q2. Q3. X DE2 24
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