Digital Control of Electric Drives

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1 Digital Control of Electric Drives Logic Circuits - equential Description Form, Finite tate Machine (FM) Czech Technical University in Prague Faculty of Electrical Engineering Ver.. J. Zdenek 27

2 Logic equential Circuit Logic sequential circuit (LC) is described with state diagram, logic equations, transition and output tables, HDL language Input, output and inner (q i ) variables take only ar values Input tate I O Output tate x y q x n q k y m Inner tate At every time instant values of all output variables are defined by values of input variables at the same time instant and by values of inner variables (stored variables) (The LC has memory, i.e. the LC does remember its past states) BEM4DEP Digital Control of Electric Drives - 4 2

3 Finite tate Machine, Transition and Output Functions Logic sequential circuit abstract model Finite tate Machine (FM) or another name Finite tate Automaton (FA) Finite state machine finite number of input, output and inner states Let us define a given combination of input, inner and output variables as input, inner and output states I,, O i k j Transition function f: = f (, I t+ t t ) t t +,, I t inner next, inner and input current states Output function g: t O = g( t, I t ) t t O,, I t output, inner and input current states BEM4DEP Digital Control of Electric Drives - 4 3

4 Logic equential Circuit Generic Model (Huffmann) LC - Logic equential Circuit t O = g( t, I t ) I x,,x i Logic Combinational Circuit O y,,y j t+ t Memory = f (, I t (torage ) q,,q k Elements) BEM4DEP Digital Control of Electric Drives - 4 4

5 LC Categories Aspect input variables change time response Asynchronous LC state changes immediatelly after input variables change (or with small time delay due to inner LC circuits behaviour) ynchronous LC state change is synchronized with external synchronizing pulses (so-called clock ). The LC are designed mostly as synchronous better inner LC states tracking and supervision. Aspect calculation method of transition and output function LCC Mealy FM model Moore FM model Autonomous FM (e.g. counters, ) = f (, I t+ t t = f (, I t+ t t = f ( t+ t ) ) ) t O = g( O t = g( t O t = g( t t, I ) ) t ) BEM4DEP Digital Control of Electric Drives - 4 5

6 ynchronous FM Mealy Model = f (, I t+ t t ) t O = g( t, I t ) BEM4DEP Digital Control of Electric Drives - 4 6

7 ynchronous FM Moore Model = f (, I t+ t t ) O t = g( t ) BEM4DEP Digital Control of Electric Drives - 4 7

8 ynchronous FM Autonomous = f ( t+ t ) O t = g( t ) BEM4DEP Digital Control of Electric Drives - 4 8

9 Finite tate Machine (FM) Description Forms tate diagram directed graph form Equation system Transition and output tables HDL language (Hardware Description Language) A programming language pecification of all possible sequences of inputs and outputs - NO be not using - impractical input sequence may be of infinite length BEM4DEP Digital Control of Electric Drives - 4 9

10 FM Description Mealy Model Transition I / = / tate tate Diagram I / = / Input I / = / I / = / I / = / I / = / Output (located next to edge) Transition and Output Function Current state and input tate transition at time t to t+ Immediate output generation α I i α j k I α I α I α I 2 α 2 I 2 α 2 I α I : i α I j α : O k : O : O α I α I : O α I : O α I 2 : O α I 2 : O BEM4DEP Digital Control of Electric Drives - 4

11 FM Description Mealy Model tate Diagram Transition and Output Table Transition I / = / I / = / I / = / I / = / Transition Table i I I I / = / Output Table tate Input I / = / Output (located next to edge) i I I O O O O O O BEM4DEP Digital Control of Electric Drives - 4

12 FM Description Moore Model tate tate Diagram Input Output (located next to node) Transition and Output Function Current state and input tate transition at time t to t+ Immediate output generation α I i j k α I α I α I α I 2 2 α I 2 2 α I 3 3 α I 3 α I i : O k : O : O : O 3 : O α : BEM4DEP Digital Control of Electric Drives - 4 2

13 FM Description Moore Model tate Diagram Transition and Output Table Transition Table i I I 3 3 Output Table i O i tate Input Output (located next to node) O O O 3 O BEM4DEP Digital Control of Electric Drives - 4 3

14 Logic equential Circuit Design Process (schema) Design at gate level using schema: Requirement tatement verbal description tate diagram (directed graph of transitions and outputs) Transition and output tables Inner state and output coding Encoded transition and output tables Next-state and output logic function Minimization of next-state and output functions (K maps) Implementation at gate level schema (CAD tool, graphic editor) ynthesis from FPGA resources (CAD tool) Logic simulation (CAD tool) Timing simulation (post-route) (CAD Tool) Generating of FPGA configuration file (CAD tool) Calculation and verification of maximum clock frequency (next lecture) Verification in application (evaluation board) BEM4DEP Digital Control of Electric Drives - 4 4

15 Logic equential Circuit Design Process (HDL) Design at gate level using Hardware Description Language (VHDL, Verilog): Requirement tatement verbal description tate diagram (directed graph of transitions and outputs) Inscription in HDL (Hardware Description Language) (CAD tool) ynthesis from FPGA resources (HDL program compilation) (CAD tool) Logic simulation (CAD tool) Timing simulation (post-route) (CAD Tool) Generating of FPGA configuration file (CAD tool) Calculation and verification of maximum clock frequency (next lecture) Verification in application (evaluation board) BEM4DEP Digital Control of Electric Drives - 4 5

16 BEM4DEP Digital Control of Electric Drives Basic torage Element R- Latch R Q Q Q Q R!!! R Latch (NAND) i R i i Q i Q +!!! R Latch (NOR) i R i i Q i Q +!!! Prohibited tate

17 Clocked R- Latch Q R Clk Q R Latch (Clock enable) i R i Clk i Q + Q i X don t care X X!!! i Q!!! Prohibited tate BEM4DEP Digital Control of Electric Drives - 4 7

18 Clocked D Latch D Q ymbol Q Clk D Latch (Clock enable) i Clk i D Q + X i Q X don t care BEM4DEP Digital Control of Electric Drives - 4 8

19 D Flip-Flop ymbol Q Q D Clk D value storage controlled with rising edge of clock (Clk) D Flip-Flop Clk i D X X i Q + i Q i Q BEM4DEP Digital Control of Electric Drives - 4 9

20 D Flip-Flop (with asynchronous set-reset) ymbol Q Q D Clk R D value storage controlled with rising edge of clock (Clk) asynchronous set/reset D Flip-Flop Reset et i D X X X X Clk X X i Q + i Q i Q BEM4DEP Digital Control of Electric Drives - 4 2

21 2bit ynchronous Binary Counter Design synchronous finite state machine (FM) of counter type. Counter is two bit and it counts in binary code. Design FM with asynchronous reset. BEM4DEP Digital Control of Electric Drives - 4 2

22 2bit ynchronous Binary Counter What ought to be designed? BEM4DEP Digital Control of Electric Drives

23 2bit ynchronous Binary Counter tate Diagram I Inputs (autonomous FM no inputs) O Outputs i i-th state Transition Table i i+ 3 3 Output Table i O i O O O 2 3 O 3 BEM4DEP Digital Control of Electric Drives

24 2bit ynchronous Binary Counter Transition Table i i+ 3 3 tate Coding i i+ i q q d d i+ 3 3 BEM4DEP Digital Control of Electric Drives

25 2bit ynchronous Binary Counter Output Table i O I O O O 2 3 O 3 i Output Coding O i i q q y y O i O O O 2 3 O 3 i = O i BEM4DEP Digital Control of Electric Drives

26 2bit ynchronous Binary Counter Minimization d q 2 3 d = q q + q q = XOR q d q 2 3 d = q q y = q y = q BEM4DEP Digital Control of Electric Drives

27 2bit ynchronous Binary Counter Implementation BEM4DEP Digital Control of Electric Drives

28 2bit ynchronous Binary Counter What was designed? BEM4DEP Digital Control of Electric Drives

29 What was designed? 2bit ynchronous Binary Counter Next-state Function tate Register Output Function LCC LCC2 BEM4DEP Digital Control of Electric Drives

30 Detector of bit equence (FM Moore Model) Design synchronous finite state machine (FM) (Moore model) which detects sequence in input bit flow. FM will output impulse when each such sequence will be detected. Design FM with asynchronous reset. (Moore) BEM4DEP Digital Control of Electric Drives - 4 3

31 Detector of bit equence (FM Moore Model) What ought to be designed? BEM4DEP Digital Control of Electric Drives - 4 3

32 Detector of bit equence (FM Moore Model) tate Diagram I Inputs O Outputs i i-th state Transition Table i I I 3 3 Output Table i O i O O O 3 O BEM4DEP Digital Control of Electric Drives

33 Detector of bit equence (FM Moore Model) Transition Table i I I 3 3 tate Coding i q i I i+ q x d d i+ x Next-state Function tate Register q q clock d D Q q d D Q q 3 3 Feedback BEM4DEP Digital Control of Electric Drives

34 Detector of bit equence (FM Moore Model) Output Table i O I O O O 3 O Output Coding i y 3 BEM4DEP Digital Control of Electric Drives

35 BEM4DEP Digital Control of Electric Drives Detector of bit equence (FM Moore Model) d x q q d x q q x q q q q d + = y = q q x q q q q q q x x q q x q q x q q d ) ( + + = = + + = Minimization

36 Detector of bit equence (FM Moore Model) Implementation BEM4DEP Digital Control of Electric Drives

37 Detector of bit equence (FM Moore Model) What was designed? BEM4DEP Digital Control of Electric Drives

38 Detector of bit equence (FM Moore Model) What was designed? Next-state Function tate Register Output Function LCC LCC2 BEM4DEP Digital Control of Electric Drives

39 Detector of bit equence (FM Moore Model) int cbittream3decoder(int x_in, int reset){ // Moore type FA, // Inputs: x_in, reset, Outputs: y_out enum {s,s,s2,s3}; static int statereg=s, nexttate=s, y_out; if(reset == TRUE){ statereg = s; nexttate = s; x_in = ; } y_out = ; statereg = nexttate; switch(statereg){ case s: if(x_in == ); if(x_in == ) nexttate = s; break; case s: if(x_in == ) nexttate = s; if(x_in == ) nexttate = s2; break; case s2: if(x_in == ) nexttate = s3; if(x_in == ); break; case s3: y_out = ; if(x_in == ) nexttate = s; if(x_in == ) nexttate = s; break; default: // Error section y_out = ; nexttate = s; }// switch() END return(y_out); }// cbittream3decoder() END C BEM4DEP Digital Control of Electric Drives

40 Detector of bit equence (FM Moore Model) class JBittream3Decoder { final int s =, s =, s2 = 2, s3 = 3; int statereg = s, nexttate = s; int yout = ; public JBittream3Decoder() {// Constructor // empty } void setfsareset (boolean reset){ statereg = s; nexttate = s; yout = ; } int jbittream3decoder(int xin) { // Moore type FA // Inputs: xin, reset, Outputs: y_out yout = ; statereg = nexttate; switch (statereg) { case s: if (xin == ); if (xin == ) nexttate = s; break; case s: if (xin == ) nexttate = s; if (xin == ) nexttate = s2; break; case s2: if (xin == ) nexttate = s3; if (xin == ); break; case s3: yout = ; if (xin == ) nexttate = s; if (xin == ) nexttate = s; break; default: // Error section yout = ; nexttate = s; }// switch() END return (yout); }// jbittream3decoder() END }// JBittream3Decoder class END Java BEM4DEP Digital Control of Electric Drives - 4 4

41 Detector of bit equence (FM Moore Model) entity vbittream3decoder is Port ( clk : in TD_LOGIC; x_in : in TD_LOGIC; y_out : out TD_LOGIC; reset : in TD_LOGIC; q : out std_logic_vector( downto ) ); end vbittream3decoder; architecture Behavioral of vbittream3decoder is type states is (s,s2,s3,s4); signal statereg, nexttate: states:= s; begin -- FA - Finite tate Machine process(clk, reset) begin if reset = '' then statereg <= s; elsif clk'event and clk = '' then statereg <= nexttate; end if; end process; process(statereg, x_in) -- tate diagram definition begin nexttate <= statereg; case statereg is when s => if x_in = '' then nexttate <= s2; end if; when s2 => if x_in = '' then nexttate <= s; elsif x_in = '' then nexttate <= s3; end if; when s3 => if x_in = '' then nexttate <= s3; elsif x_in = '' then nexttate <= s4; end if; when s4 => if x_in = '' then nexttate <= s2; elsif x_in = '' then nexttate <= s; end if; VHDL when others => nexttate <= statereg; end case; end process; process(statereg) -- Output function begin case statereg is when s => y_out <= ''; when s2 => y_out <= ''; when s3 => y_out <= ''; when s4 => y_out <= ''; when others => null; end case; end process; end Behavioral; BEM4DEP Digital Control of Electric Drives - 4 4

42 Detector of bit equence (FM Mealy Model) Design synchronous finite state machine (FM) (Mealy model) which detects sequence in input bit flow. FM will output impulse when each such sequence will be detected. Design FM with asynchronous reset. (Mealy) clk x y BEM4DEP Digital Control of Electric Drives

43 Detector of bit equence (FM Mealy Model) What ought to be designed? FM Mealy Compare vs FM Moore BEM4DEP Digital Control of Electric Drives

44 Detector of bit equence (FM Mealy Model) tate Diagram I / = / I Inputs O Outputs i i-th state I / = / I / = / I / = / I / = / Transition Table i I I I / = / Output Table i I I O O O O O O BEM4DEP Digital Control of Electric Drives

45 Detector of bit equence (FM Mealy Model) Transition Table i I I tate Coding i I i+ i q q x d d i+ x q q Next-state Function clock d tate Register d D Q q D Q q Feedback BEM4DEP Digital Control of Electric Drives

46 Detector of bit equence (FM Mealy Model) Output Table i I I O O O O O O i I O Output Coding i q q x y BEM4DEP Digital Control of Electric Drives

47 Detector of bit equence (FM Mealy Model) d x d x q q q q d = qx + qx d = q q x Minimization y q q x y = q q x BEM4DEP Digital Control of Electric Drives

48 Detector of bit equence (FM Mealy Model) Implementation BEM4DEP Digital Control of Electric Drives

49 Detector of bit equence (FM Mealy Model) What was designed? BEM4DEP Digital Control of Electric Drives

50 Detector of bit equence (FM Mealy Model) What was designed? Next-state Function tate Register Output Function LCC LCC2 BEM4DEP Digital Control of Electric Drives - 4 5

51 Digital Control of Electric Drives Logic Circuits - equential Description Form, Finite tate Machine (FM) END Czech Technical University in Prague Faculty of Electrical Engineering

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017 UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 2-2016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002