14:332:231 DIGITAL LOGIC DESIGN

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1 14:332:231 IGITL LOGI ESIGN Ivan Marsic, Rutgers University Electrical & omputer Engineering all 2013 Lecture #17: locked Synchronous -Machine nalysis locked Synchronous Sequential ircuits lso known as finite state machines inite refers to the fact that the number of states the circuit can assume is finite Use edge-triggered flip-flops locked = all storage elements use a (i.e. all storage elements are flip-flops) Synchronous = all flip-flops use the same signal ll flip-flops are triggered from the same master signal, and therefore all change their state together 2of 30 1

2 locked Synchronous SM Structure : determined by possible values in sequential storage elements Transition: change of state lock: controls when state can change by controlling storage elements Inputs ombinational Outputs urrent or Storage Elements Next lock 3of 30 -machine Structure (Mealy) Mealy machine put depends on state and current : Next state = (, ) Output = G (, ) storage = set of n flip-flops that store the state of the machine (2 n states) s Next-state Memory Output puts G signal ombinational logic storage: typically edge-triggered flip-flops ombinational logic 4of 30 2

3 -machine Structure (Moore) Moore machine put depends only on : Output = G () s Next-state Memory Output puts G signal ombinational logic storage: typically edge-triggered flip-flops ombinational logic 5of 30 omparison of Mealy & Moore SM Moore: to next state Mealy machines usually have less states put puts are shown on transitions (n n) rather than in states (n) Mealy: Moore machines are safer to use puts change at edge (always one cycle later) in Mealy machines, change can cause put change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback may occur if one isn t careful Mealy machines react faster to s react in the same cycle don't need to wait for puts may be considerably shorter than the cycle but, asynchronous puts and asynchronous are hazardous in Moore machines, more logic may be necessary to decode state into puts there may be more gate delays after edge (put) to next state 6of 30 3

4 Mealy and Moore Example Mealy or Moore? 7of 30 Mealy and Moore Example Mealy or Moore? Not a state machine 8of 30 4

5 Mealy and Moore Example Mealy or Moore? Not a state machine Moore: put = Γ(state) [no directly feeding to put logic] 9of 30 Mealy and Moore Example Mealy or Moore? Not a state machine Moore: put = Γ(state) [no directly feeding to put logic] Moore: put = Λ(state) [no directly feeding to put logic] of 30 5

6 Mealy Machine with Pipelined Outputs Outputs of a Mealy machine can be kept constant within a period by using put flip-flops Often used in programmable logic device (PL) based state machines Output taken directly from flip-flops, valid sooner after edge ut the put logic must determine put value one tick sooner ( pipelined ) rawback: put changes are delayed by as much as one cycle s Next-state Memory Output G Output Pipeline Memory pipelined puts signal of 30 Notation, haracteristic Equations means the next value of ( next state ) Excitation is the applied to a device that determines the next state haracteristic equation specifies the next state of a device as a function of its (s) evice Type S-R latch latch Edge-triggered flip-flop Edge-triggered J-K flip-flop T flip-flop T flip-flop with enable haracteristic Equation = S + R = = = J + K = = = + 12 of 30 6

7 locked Synchronous Machine nalysis locked synchronous state machines can be described in many ways: circuit schematic state and state/put tables transition and transition/put tables state diagrams (flowcharts) SM (algorithmic state machine) charts HL (hardware description languages) programming languages description that can be given to a system for simulation and synthesis is preferred. Usually these are text descriptions, but drawing tools exist 13 of 30 Example Sequential ircuit nalysis Is this a Moore or Mealy machine? What does it do? How do the puts change when an arrives? x y put 14 of 30 7

8 Example Sequential ircuit nalysis Input: x(t) Output: y(t) : (0(t), 1(t)) Example: (0 1)= (01), () Next : (0(t), 1(t)) = (0(t+1), 1(t+1)) x Next-state logic 0 1 Next state storage 0 1 urrent state y s Next-state Memory Output puts G Output logic signal 15 of 30 -Machine nalysis Steps ssumption: Starting point is a logic diagram 1. etermine next-state function ( ) and put function G( ) 2a. onstruct state table or each state/ combination, determine the value Using the characteristic equation, determine the corresponding next-state values (trivial with flip-flops) 2b. onstruct put table or each state/ combination, determine the put value (can be combined with state table) 3. raw the state diagram (optional) 16 of 30 8

9 Some efinitions Excitation = signals for flip-flops at each tick Excitation equation = next-state logic ( ) of the state machine haracteristic equation = specifies the flip-flop s next state as a function(current-state, s) Transition equation = specifies the state machine s next state as a function(current-state, s); essentially same as ( ) Transition table = created by evaluating the transition equations for very /state combination Output equation = put behavior G( ) of the state machine 17 of 30 Example Machine locked synchronous state machine example Using positive-edge triggered flip-flops Next-state Memory Output G put 0 0 MX 0 0 Output equation: MX = signal 18 of 30 9

10 it is a Mealy Machine The flip-flops are positive-edge-triggered flipflops -to-state transitions occur when the state memory (flip-flops) is loaded with new next-state values state-to-state transitions can only occur on the edge The flowchart for the analysis: equation characteristic equation transition equation transition table put equation state/put table state diagram 19 of 30 Transition Equations Excitation equations: 0 = = haracteristic equations: 0 = 0 1 = 1 Substitute equations into characteristic equations to obtain transition equations: 0 = = signal put MXS 20 of 30

11 Transition and Tables Transition equations: 0 = = Output equation: MX = S 0 1 S S 0 1, 0, 0, 0, 0, 0, 0, 0, 1 S, MX transition table state table state/put table = 00 = 01 unction of the example machine = 2-bit binary counter with enable : = When =0, maintains current count When =1, the count advances by 1 at each tick; rolling over to 00 after 21 of 30 iagram Graphical representation of the state/put table Ovals for states rrows for transitions (annotated by the put) = 0 = 0 (MX = 0) = 1 (MX = 0) (MX = 0) = 1 (MX = 1) = 1 (MX = 0) = 0 = 1 (MX = 0) = 0 (MX = 0) (MX = 0) 22 of 30

12 Redrawing of the Example Synchronous Machine Excitation equations and the state variables are placed slightly differently (also N is used) but it is the same state machine put just not drawn as conceptual Mealy model MXS 0 0 i.e., we don t need to draw it as in the model signal MX of 30 Modified Machine Moore machine, the put depends only on the state put 0 0 MXS MXS = signal 24 of 30 12

13 Modified Machine Moore state diagram and state/put table Moore type put depends only on state Mealy type put depends on state and = 0 current state put MXS=0 = 1 MXS=0 = 1 = 1 = 0 S 0 1 S MXS = 0 MXS=1 = 1 MXS=0 = 0 25 of 30 iagram onvention Moore Machine: - put depends only on state Mealy Machine: - put depends on state and put to next state (put) to next state Example: MXS=0 to state =1 Example: = 1 (MX = 0) to state 26 of 30 13

14 Timing iagram for Machine(s) Timing diagram shows example behavior, starting with a given initial state of 00 () NOT a complete description of machine behavior because it neglects timing constraints state s: = 00 = 01 = = The counter counts only if =1 at the rising edge of LOK 27 of 30 nother Example Machine ed synchronous state machine with three flip-flops and eight states 28 of 30 14

15 Example Machine nalysis Excitation equations: 0 = 1 X+ 0 X = 2 0 X+ 1 X Transition equations: 0 = 1 X+ 0 X = 2 0 X+ 1 X = X Y Output equations: Z1 = Z2 = X Y Z1 Z2 00 S E G H 00 H X Y 01 E G H H S H Z1 Z2 00 Moore machine transition/put table state/put table 29 of 30 iagram of the Example Machine Transition expression = a transition is taken for s for which the transition expression is 1 Transition expressions on arcs leaving a state must be mutually exclusive and allinclusive Transitions labeled 1 are always taken The sum of the leaving transition expressions must be one or a given (current-state, next-state) a transition expression can be written as a sum of minterms for the combinations that cause that transition X Y Z1 Z2 = X Z1 Z2 = X X Y E Z1 Z2 = 1 Z1 Z2 = 1 X X G Z1 Z2 = 1 H Z1 Z2 = X Y 1 X Y Z1 Z2 = X Z1 Z2 = 00 X 30 of 30 15

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1 Ch 7. Finite State Machines VII - Finite State Machines Contemporary Logic esign 1 Finite State Machines Sequential circuits primitive sequential elements combinational logic Models for representing sequential