CARLETON UNIVERSITY Final EXAMINATION April 16, 2003

Size: px

Start display at page:

Download "CARLETON UNIVERSITY Final EXAMINATION April 16, 2003"

Sabrina Ward
6 years ago
Views:

1 LTN UNIVSIT Final MINTIN pril 6, 23 Name: Number: Signature: UTIN: HUS No. of Student: epartment Name & ourse Number: ourse Instructor(s) UTHI MMN 3 4 lectronic ngineering L267, and Profs. N. Tait and J. Knight ny notes or books, any non-communicating calculator. Students MUST count the number of pages in this eamination question paper before beginning to write, and report any discrepancy immediately to a proctor. This question paper has 8 pages. This eamination paper May Not be taken from the eamination room. In addition to this question paper, students require: an eamination booklet yes no may request a Scantron sheet yes no Please answer on the eamination paper. The correct answers should easily fit in the space given. ou may ask for a booklet if you need it. heck on the right if your answer is in the booklet. 2% oolean lgebra a) Find the dual of the function F = ( + ) + F = [ ( + [ ])] + [ ] Many people forgot the [..] brackets F dual = [+( [+])] [+] Too many called the dual F. F dual = [ + [+]] [+] function is not equal to it s dual. a) vg 63.% 2% 7% b) valuate the inverse of the function = + as a Σ of Π epression = ( [ ]) + Partial step dual =(+[+]) = (+[+]) = (+ ) Not adding brackets around N terms caused much grief. lternately, using a map = ( [+]) + = + +, plot this = +, circle zeros Many people did not use the eneralized emorgan Theorem 2 Karnaugh Maps a) etermine the Σ of Π function f(,,,,) which gives the minimum number of letters d d f(,,,,) = d d 8 letters f = Maps for f ommon errors: Not sharing the term between and thus getting a term, Some people did not even share, using Not minimizing on one map by using instead of d d 8 letters. f = ne could reduce the letter count slightly by factoring out and, but this would no longer be Σ of Π. b) vg 69.7% 2 a) vg 84.2% page Profs. N. Tait and J. Knight page of 8

2 arleton University lectronic ngineering L267 Name 6% 2 Karnaugh Maps (continued) b) Find the simplest (minimum number of letters) implementation for the function g(,,,) defined by the Σ of Π map below. However the sum of products may not be the the best answer. Map for g Long Hard Solution g = =( + ) + ( + ) g(,,,) = =( + )( + ) + ( + )( + ) Swap =( + )[( +) + ( + )] =( + )[( + ) + ][( + ) + ( + )] 2 Map for g = ( + ) [( + )( + + )][( + + )( )] 2 Simple Solution ircle zeros g = + + using eneralized emorgan (+)(+)(++) 7 letters = ( + )( + )( + + )( + + ) = ( + )( + )( + + ) onsensus 2 a) vg 79.% 3 Programmable Logic 8% a) The functions defined by the maps are to be inplemented by a 3-output PL. PLs can share N plane (product) terms so the object here is to use the minimum number of N plane terms in the PL. ircle the maps to minimize these terms. List these product terms. 3 a) vg 79.% PL F d d d d F ll of these reduce sharing and marks Total number of different product terms st product = 5th product = 2nd product = 6th product = 3rd product = 7th product = 4th product = 8th product = 9th product = th product = th product = 2th product = Minimizing the maps individually is a very poor method and would give 2 products. F d PL d d d F Total number of different product terms_8 st product = 5th product = 9th product = 2nd product = 6th product = th product = 3rd product = 7th product = th product = 4th product = 8th product = 2th product = lternately the 6th and 7th products could be ( or ) and ( or ) Profs. N. Tait and J. Knight 9/4/9 page 2, of 8

3 arleton University lectronic ngineering L267 Name 3% 3 Programmable Logic (ontinued) b) rite the oolean epression represented by the PL shown below. F Permanent connection Programmable connection 3 a) vg 99.% F = + + = + + 4% c) rite an alternate epression for F and, from 3b) above, which could be realized using the minimum number of product lines in a PL. F = + + = + + educed number of products F = + = + Sharing the line does no good, in fact it is not possible with the PL which has fied plane logic. 3 c) vg 53.5% 4 Synchronous ircuits: a) For the state graph shown 7% 4 a) vg i) onstruct the state table. ii) raw the circuit using minimal logic. 74.2% ommon errors Shifting order of and columns between table and maps. Not making table in K-map order. Not transfering net state columns to maps properly Taking the net state as the output thus making Mealy outputs. Note the output is the same as the state. Interchanging map titles so = + instead of +. Not drawing a correct circuit from the equations. Trying to combine both outputs into one variable. State Net State + + inputs utput utput = state + Map of = + Map of = + = = + = = Profs. N. Tait and J. Knight 9/4/9 page 3, of 8

4 arleton University lectronic ngineering L267 Name 4% 4 Synchronous ircuits (ontinued) b) Sketch the waveforms for, and. Their initial values are, and respectively as shown. synch eset lock 4 a) vg 34.8% 3% This circuit is called a Johnson or Mobius ounter ommon errors: Not realizing just after the clock edge must be what was just before that edge. Not realizing just after the clock edge must be what was just before that edge. esetting c) The circuit below shows a three-bit binary counter. dd the circuitry for the synchronous clear so the count will be 2 = on the net active clock edge after synchronous clear is made. There is no synchronous clear on these flip-flops. SNHNUS L = ( ) From the Midi lab. 4 c) vg 45.% = ( ) = ( 2 ( ) 6% d) The circuit below uses the same three-bit binary counter as above after the synchronous clear is added. Use it and etra gates to make a circuit which will generate the pulse P as shown. P comes up on the 4th cycle after the clear and every 8 cycles thereafter. SNHNUS L P e) vg 43.2% SNHNUS L 3-IT UNT 2 P This is straight from the Midi lab. lternately: The counter counts ->->2->3->4->5->6->7-> ou need an output P when the count is 4 () The gate does that. Then P goes to zero when the count continues 5->6->7->8->->->2->3-> and becomes, eight counts later on the second 4. Profs. N. Tait and J. Knight 9/4/9 page 4, of 8

5 arleton University lectronic ngineering L267 Name 4 Synchronous ircuits (ontinued) e) (i) Find a state assignment for the circuit below with logic minimization as the objective. 6% Make the reset state, and give a brief eplaination. (ii) Fill in the two-column net-state table. 4 a) vg State Table 48.5% STT 2 NT STT UTPUT ule. Parents of the same child (same input) should cuddle -up on the K-map. ( and ), ( and ), ( and ) ule 2. Sisters should cuddle up (, ), (,), (,), (,), (,) einforces ule. annot make both (,) and (,) adjacent, and still follow ule. K-map like, State Table STT NT STT NT STT STT = = = = = = = = = = = = = = = STT NT STT Scratch Table NT STT STT ne choice. nother choice Still Used in the another K-map like choice state table 5% f) raw a logic circuit with 2 inputs and y, and an output z. z= if y=, z= if y=, and z stays at its previous value if y=. The y= input never happens. (L) y S(H) z + 4 f) vg 27.% lternately make an asynchronous state macine with state and net state z + This is the set-reset latch latch described in the notes with =S(H) and y=(l) Net state z + State y= y= y= y= d d y d d z + = z y + 4% g) ssume it takes ns for a signal change to go from the input of a NN N or NT gate to the output. raw a circuit which will oscillate with a half period of 3ns. 3ns dd number of inverters gives an oscillator. Input change to output change = 3ns This feeds back and changes the input again. 4 h) vg 4.5% Profs. N. Tait and J. Knight 9/4/9 page 5, of 8

6 arleton University lectronic ngineering L267 Name 4 Synchronous ircuits (ontinued) h) i) omplete the waveforms and 4% ii) fill in the state for the machine shown. Initially =. 4 a) vg Synchronous State raph LK 72.6% = = = z== z= Initially = so State is. State n active clock edge =, so State stays ait till net active clock edge =, so state changes to. ait till net active clock edge =, so state changes to ait till net active clock edge =, so state changes to 7% State i) (i) educe the state table below to the minimum number of states. (ii) Make a new state table with the minimum number of states. Net State = = utput = = F 4 i) vg 8.8% F utputs Incompatable F. an merge, and, and, F and.. State Net State = = utput = = F Profs. N. Tait and J. Knight 9/4/9 page 6, of 8

7 arleton University lectronic ngineering L267 Name 5 Hazards 4% a) eneral hazard question. i) Is it possible to construct a logic circuit for an arbitrary combinational (no storage, no feedback) function using nothing but N, and NT gates in a sum-of-product form? yes ii) Is it possible to construct a logic circuit for an arbitrary combinational function which has no single-variable change hazards? yes If so, describe the major design steps for a small circuit (up to 4 inputs): Multiply out to sum-of-product form Plot on a K map Mask all the hazards on the map. iii)is it possible to construct a logic circuit for an arbitrary combinational function which has no multiple variable-change hazards? No, one cannot mask function hazards If so, describe the major design steps: 5 a) vg 66.3% 7% b) Identify hazards in a logic function constructed according to the formula: F = ( + ) ( + ) + 5 c) vg 63.7% No hazards in since there is no ; also no hazards in. Hazard in when () ( + ) + = (static ) ( +) ( + ) + () ( + ) + Hazard in when = (dynamic ) ( + ) ( + ) + No hazard in ( + ) ( + ) + No hazard in ( + ) ( + ) + ( ) ( + ) () ( + ) Hazard in when = d (static ) No hazard in Profs. N. Tait and J. Knight 9/4/9 page 7, of 8

8 arleton University lectronic ngineering L267 Name 6 synchronous ircuits a) Make a state table for the circuit shown. 7% State Table 6 a) vg STT NT STT a + c + a % c + a + = + = + + = + + c + = b) synchronous state table 2% 6 c) vg State Net State a + b + ircle all stable states s= s= Indicate any races or cycles with arrows. 53.8% For each race/cycle indicate if it is: critical, non-critical, who-cares, oscillating cycle, ace cycle which dies out. Starting in stable state with S=, change S ->. The state table says the net state is which is stable. State Net State a + b + However, because of the race, it might also be or. s= s= From transient state (S=) the net state is so the result is the same as if one had gone directly. From transient state, the net state is which will again send the the machine to. ven with the race, the final state will always be, so the race is non-critical. c) synchronous state table 2% 6 e) vg State Net State a + b + ircle all stable states s= s= Indicate any races or cycles with arrows. 7.3% For each race/cycle indicate if it is: critical, non-critical, who-cares, oscillating cycle, cycle which dies out. Starting from stable state (S=), one gets a cycle immediately when S changes to. Starting from state,with S-> one travels to state and then to state before entering the cycle. State Net State a + b + s= s= Profs. N. Tait and J. Knight 9/4/9 page 8, of 8

CARLETON UNIVERSITY Final rev EXAMINATION Fri, April 22, 2005, 14:00

CARLETON UNIVERSITY Final rev EXAMINATION Fri, April 22, 2005, 14:00 LTON UNIVSITY Final rev MINTION Fri, pril 22, 25, 4: Name: Number: Signature: UTION: 3 HOUS No. of Students: 258 epartment Name & ourse Number: lectronics L 267, and ourse Instructor(s) T..ay and J. Knight