CARLETON UNIVERSITY Final rev EXAMINATION Fri, April 22, 2005, 14:00

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1 LTON UNIVSITY Final rev MINTION Fri, pril 22, 25, 4: Name: Number: Signature: UTION: 3 HOUS No. of Students: 258 epartment Name & ourse Number: lectronics L 267, and ourse Instructor(s) T..ay and J. Knight UTHOIZ MMON TUN OFF cell phones and personal communications equipment and LV THM T TH FONT. Notes, books, any non-communicating calculator are allowed. Students MUST count the number of pages in this examination question paper before beginning to write, and report any discrepancy immediately to a proctor. This question paper has 9 pages. This examination paper May Not be taken from the examination room. In addition to this question paper, students require: an examination booklet yes no x may request a Scantron sheet yes no x Please answer on the examination paper. The correct answers should easily fit in the space given. You may ask for a booklet if you need it. % oolean a) Write the dual of f = + + f UL = ( + )( + )( + ) % b) iven f = + +, find f without overbars longer than one letter. Put overbars over each letter of the dual f = ( + )( + )( + ) c) onvert f = + + into product-of-sums (Π of Σ). Plot f on the map Plot the map of f which has s where the f map had s ircle the f map f = + Use emorgans eneralized Theorem f =( + )(( + ) d) (i) Simplify f = + + to use the minimum number of gates. (ii) Sketch the circuit. Map of f Map of f From the map of f, f = + 3% e) Simplify g = ( + )( + )( + ) Hint: oes g have any relation to f in parts a) and d)? g = f UL hence f SIMPLIFI-UL = g SIMPILFI g = ( + )( + ) page T..ay and J. Knight page of

2 arleton University lectronic ngineering L267 2 oolean a) Factor + Using the extended 2 rule (+)(+)(+) b) Factor = + + using + x = (simplification) = + using simplification again = ( + )( + ) using 2 4% c) omplete the factoring of (+)(+Z) + ( + Y) = [(+)+ ( + Y)][(+Z) + ( + Y)] using + = ( +)( + ) (2 law) = [ Y][ + Z + + Y] 4% d) raw a circuit to implement g = (+)(Y+) + ( + Y)( + ) Using only real gates i.e. NN, NO and NOT gates. The best solution needs only one NOT gate. The best solution is a bit harder than a solution with several NOT gates. % e) i) Simplify ( + )() = () = ii) Simplify + = + + Using emorgan = Using + = T..ay and J. Knight 3/3/9 page 2, of 9

3 arleton University lectronic ngineering L267 Name 6% 3 oolean a) g = Would take 5 gates and 6 letters if implemented as above. It is possible, but not obvious, to implement g with 8 letters. Find this implementation. However be careful how much time you spend for 6 marks. This is much simpler as a product of sums Plot g on one map. Plot g on the other. g= Use emorgan get g = ( + )( + )( + )( + ) 8 letters Map of g Map of g 8% 4 Mux Logic Show how to implement the function g using only MUs and inverters. Minimization of hardware is expected. g = + + g(=) = + g(=) = + = = using simplification rule T..ay and J. Knight 3/3/9 page 3, of 9

4 arleton University lectronic ngineering L267 7% 6% 5 Programmable Logic Program the PL to implement the logic defined by the equations shown below. The inverted lines are made thinner to help avoid using the wrong line. write each N term F H F = here = + (This is the only size of PL available to you.) F= = + H= + + Map of F H = Synchronous ircuits a) omplete the waveforms for F, F2, F3 and F4. Their initial values are all as shown. lock synch eset F F2 F3 F F2 F3=F2&F F4 lone one Map of Map of H synchronous reset: ll FF outputs are while is high; they stay until the next active clock edge. F3 = F2 F. It is not wait for a clock edge because it is not a flip-flop output. F just after the active clock edge is what was just before the clock edge. F2 just after the active clock edge is what F was just before the clock edge. F4 just after the active clock edge is what F3 was just before the clock edge. 3% b) For the state-graph below, with Z= initially: i)omplete the waveform for Z and ii) fill in the states on the line under Z. Synchronous raph x= x= x= z=x= z= LK Z Use arrows to indicate state durations. T..ay and J. Knight 3/3/9 page 4, of 9

5 arleton University lectronic ngineering L267 Name 3% c) For the state-graph below: (It is the same one as for part b) i)omplete the state table. ii) raw the complete circuit. Synchronous raph x= x= x= z=x= z= state S S + next state output x= x= z S x S + =x x lk z 8% 7 eduction (i) Find the equivalent states in the table below. (ii) Make a new state table with the minimum number of states.. evised Table = = Output Z = = Output Z F F H F H H & can merge & H can merge F F H H F H, F,,,F H, F, H,, F H, F, H,, H, H, H,,F,, F T..ay and J. Knight 3/3/9 page 5, of 9

6 arleton University lectronic ngineering L267 % 8 Synchronous raph raw the state graph for a machine to meet all the following requirements: Has one input, and one output Z. Z= in the cycle after the machine receives the complete sequence =, and Z= in the cycle after the machine receives the complete sequence =. The leftmost bit of is received first. Overlapped sequences are to be detected including a sequence overlapping itself Z = except for the single clock period after the appropriate sequence is completed. The machine starts at the ST state. raw only the state graph. Use the states provided below and do not change anything already given eset Z= Z= Z= Z= Z= 5 Z= Z= Z= Z= T..ay and J. Knight 3/3/9 page 6, of 9

7 arleton University lectronic ngineering L267 Name 9 Hazards a) raw a circuit which will implement the function + + and is free of all static and dynamic hazards. To mask the hazards, add + +. on t forget the hazard in the wraparound. Sum of product circuits have no static- or dynamic hazards if they are free of static- hazards. The sum of products circuit would implement F= However F = + found by circling the zeros If = no hazards possible If = If = no hazards possible no hazards possible If F has no has hazards, inverting it does not add them F 5% b) five-variable function, F, is shown by the implicants (N terms) drawn on the Karnaugh map below. List the implicants (N terms) that are required to mask the static- hazards in F. = = List of implicants (N terms): add these implicants 5% c) -latch, is designed as an asynchronous circuit. It has a potential problem which was not admitted in the original description. Its circuit is shown below. i) What is wrong with the design? It has a static- hazard in when,=,. ii) raw a circuit without the problem. q + = + q + q + = + + q + 3% d) Was the controller circuit in the midi lab designed to be free of hazards? No If (yes) describe in two lines what you did. Hazards are not important in synchronous circuits. They die out before the next clock edge, and thus are never captured by the flip flops. If (no) describe in two lines why it was not done. T..ay and J. Knight 3/3/9 page 7, of 9

8 arleton University lectronic ngineering L267 o either a) or b) but not both. a) synchronous ssignment. For the following state table, revise the table and select a critical-race-free state assignment. o not add any states or change the stable states. Keep as state. o not increase the number of rows in the table. -- means don t care. Y= Y= Y= Y= Try The only bad transition is -> but that is a triple jump. Try Write your revised state table below. Write the bit pattern for the state assignment in the leftmost, the, column after the =. Fill in the columns using letters only. lso write your state assignment in the table/map on the right. Y= Y= Y= = -- = -- = -- = = -- Y= an make go to or in 2 jumps. Looks OK. Write your state assignment here One of many solutions Put bit patterns here Only put letters here T..ay and J. Knight 3/3/9 page 8, of 9

9 arleton University lectronic ngineering L267 Name b) Synchronous ssignment. (If you do this question, skip the previous one) (i) Find a state assignment for the machine below with logic minimization as the objective. (ii) What assignment should the reset state have? Why? We are looking for two concepts. Logic size will stay the same if on state is picked arbitrarily. The reset signal naturally takes flip flops to state, so that is easy to use. 2 (iii) Show how you used the rules to get the other assignments. (iv) Fill in the two-column assigned next-state table in K-map order. Table = = Output = = F F F (iii) Use of rules ule ; Parents of same state for same input (,) (,,) ule 2; Sisters should cuddle (,F)(,) 2 (,)(F,)(,)(,) F In the state table below: In the state columns put both the letter and the bits of the state assignment. In the next state columns put only the letters. Table in K-Map Order 2 = = = = = F = = = = F = F = = note reversed columns Thick lines are rule Then lines are rule 2. Only F- is not close ule 3; Outputs (F)(F) will be ignored One state assignment F otate and flip this to fit in the state assignment map. 2 F d Write your final state assignment here = = Scratch Table = = = = = = = = = = Scratch 2 2 d d T..ay and J. Knight 3/3/9 page 9, of 9