Unit 12 Problem Solutions

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1 Unit 2 Problem Solutions 2. onsider 3 Y = Y Y Y, that is, we need to add Y to itself 3 times. First, clear the accumulator before the first rising clock edge so that the -register is. Let the d pulse be for 3 rising clock edges and let the Y register contain the desired number (y 5 y 4 y 3 y 2 y y ) which is to be added three times. The timing diagram is on FL p. 65. Note: lrn should go to and back to before the first rising clock edge. d should be before the same clock edge. However, it does not matter in what order, that is, d could go to before lrn returns to, or even before it goes to. 2.2 Serial input connected to for left shift. Sh =, L = causes a left shift. Sh =, L = or causes a right shift Serial Out 2.3 See FL p. 65 for solution. SI SH Ld lock Q 3 Q 2 Q Q 4-bit Parallel In Parallel Out Shift Register (a) Present State Next State Flip-Flop Inputs T T T T ' T ' T lock s explained in Section 2.3, it can be seen that changes on every pulse: T = changes only when = : T = changes only when both and = : T = changes only when,, and = : T = ' T ' T 2.4 (b) The binary counter using flip-flops is obtained by converting each T flip-flop to a flip-flop by adding an OR gate. See FL p. 65 and Figure 2-5 on FL p Equations for,, and are from Equations (2-2) on FL p eginning with (b) of Problem 2.4 solutions, = = ' ()' = ' (' ' ') = ' ' ' '

2 2.6 In the following state graph, the first flip-flop () takes on the required sequence,,,,,, (repeat).. = '' = ' = ' 2.7 (a) = ' For flip-flop: goes to because = = ' ' = '' '' = '' ' 2.7 (b) T T T T = '' '' T = '' T = ' ' ' For T flip-flop: goes to because T T T = 2

3 2. (a) J K J K J K J = ' K = '' J = ' K = J = K = ' ' In state, J = ' =, K = '' =, = ' = J = ' =, K = =, = J = =, K = ' ' =, = = So the next state is = 2. (b) S R S R S R S = ' S = '' R = '' S = ' R = S = ' R = ' ' In state, S = ' =, R = '' =, = S = ' =, R = =, = S = ' =, R = ' ' =, = = So the next state is = 3

4 2.9 (a) Q Q M N 2.9 (b) M M = N N = M N M = ' N = ' M M = ' 2. See Lab Solutions for Unit 2 in this manual. N N = ' 2. The flip-flops change state only when Ld or Sh =. So E = Sh Ld. Now only a 2-to- MU is required to select the input to the flip-flop. SI Q Q 3 2 Q Q 3 2 E E E E Sh Ld 4

5 2.2 (a) When ShLd =, the MU for flip-flop i selects Q i to hold its state When ShLd =, the MU for flip-flop i selects i to load. When ShLd = or, the MU for flip-flop i selects Q i to shift left. Q Q Q Q 3 2 SI 3 2 Sh Ld 2.2 (b) Q 3 = Ld'Sh'Q 3 LdSh' 3 ShQ 2 ; Q 2 = Ld'Sh'Q 2 LdSh' 2 ShQ ; Q = Ld'Sh'Q LdSh' ShQ Q = Ld'Sh'Q LdSh' ShSI 2.3 Notice that Sh overrides Ld when Sh = Ld = lock Sh Ld Q Q SI = Q Q 2.4 (b) Similar to problem 2.4 (b), E = E.,,, and, remain unchanged. 2.4 (a) Similar to problem 2.4 (a), T E =. T, T, T, and T, remain unchanged. E' E E' E E T E lk lk E bit Johnson counter using J-K flip-flops: J 4 Q 4 J 3 Q 3 J 2 Q 2 J Q K 4 Q' 4 K 3 Q' 3 K 2 Q' 2 K Q' LK Starting in :,,,,,,,, (repeat),... Starting in :,,,,,,,, (repeat),... 5

6 2.6 When U =, =, add. When U =, =, subtract : add. When U =, =, no change: add. U =, =, can never occur. So add the contents of the register to 2, where 2 = = and = U. (Note: to save the OR gate, let = and in = U.) Q 2 Q Q 2 lk S 2 S S 3-IT ER in Y 2 Y Y (a) = ' = '' ' = ' ' ' = ' U 2.7 (b) See table 2-7 (c) on FL p J = J = J = ' J = K = K = 6 K = K =

7 2.7 (c) See table 2-5 (c) on FL p S S S S S = S = ' S = '' S = ' R R R R R = ' R = R = R = R = R = ' 2.7 (d) See table 2-4 on FL p T T T T T = T = T = ' T = 2.7 (e) Use equations to find next states for unused states. State : J = =, K = =, = J = =, K = =, = = J = ' =, K = =, = J =, K =, = ' = So the next state is. Other next states can be found in a similar way. 7

8 2. 2. (a) 2. (b) 2. (c) 2. (d) 2. (e) = '''' ; = '; = '' '; = ' J = ''', K = '; J = ', K = ''; J = ' ', K = '; J =, K = S = '''', R = '; S = '', R = '' or '''; S = '' ', R = ', S = ', R = T = '''; T = '' ''; T = ' ' '; T = (a) = ' ; = '; = ' ' 2.2 (a) Q Q L M 2.9 (b) 2.9 (c) 2.9 (d) 2.9 (e) 2.2 (b) J = ', K = '; J =, K = '; J = ' ', K = '' T = '' '; T = ' '; T = '' '' '' S = ', R = '; S =, R = '; S = ' ', R = '' State goes to, because =.

9 2.2 (b) L =, M = ; L = ', M = ' '; L = '', (contd) M = ' L = M = L = ' M = ' ' L = '' M = ' 2.2 J K J K J K J K Using Karnaugh maps: J =, K = ; J =, K = ; J = ', K = '; J =, K = 2.22 lock ycle Input ata EnIn End Ldc Ldd ccumulator Register ddend Register us escription Input to accumulator 3 3 Input to addend Sum to accumulator Input to addend Sum to accumulator Input to addend Sum on bus Note: Register values change after the clock edge. So a value loaded from the bus appears in the register on the next clock cycle after the load signal and bus value are present. 9

10 2.23 (a, b) NN gates Y E ' k E En E E R k E En k E En k E En E 2 G G 2-to-4 decoder E ' ' E 2 ' E E (c) all the values beginning in the & registers and Y, respectively. We want = Y = ('Y')'. Invert using M' = NN M. To invert a value on the right side, in register or, we will need a on the left side, in register or. This can be accomplished using = NN (anything.) There are several solutions using different registers. Here is an example: lock ycle G G E E E 2 escription NN = ' = ' 2 NN = 3 NN = NN Y = Y' 4 NN = ' NN Y' = Y lternate three-cycle solution: Use Y = 'Y = (' ('Y)')' lock ycle G G E E E 2 escription NN = ' = ' 2 NN = ('Y)' 3 NN = (' ('Y)')' = Y 2.24 (a) For bit reversal using the inputs of the shift register: Sh =, Ld = Ld Sh SI lk Q 3 Q 2 Q Q (b) Same as Figure 2- (b) on FL p. 33, except that for the "" input of each MU, instead of SI, Q 3, Q 2, or Q, use Q, Q, Q 2, or Q 3, respectively. lso, replace Sh with and Ld with. 9

Logic Design II (17.342) Spring Lecture Outline

Logic Design II (17.342) Spring 2012 Lecture Outline Class # 10 April 12, 2012 Dohn Bowden 1 Today s Lecture First half of the class Circuits for Arithmetic Operations Chapter 18 Should finish at least