SYNCHRONOUS SEQUENTIAL CIRCUITS


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1 CHAPTER SYNCHRONOUS SEUENTIAL CIRCUITS Registers an counters, two very common synchronous sequential circuits, are introuce in this chapter. Register is a igital circuit for storing information. Contents of registers can also be manipulate for purposes other than storage. A counter is a evice that performs state transitions. Analysis an synthesis of synchronous sequential circuits are also introuce in this chapter.. Registers An nbit register is a circuit that can store n bits of information. Every bit in a register is assigne a position number. The position numbers ranges from to n, with assigne to the rightmost bit an incremente towar the left. Since a flipflop can store one bit of information, a register can be constructe from n flipflops. Figure.(a) shows the bit positions an the contents of a 4bit register. The contents are 2 2. Figure.(b) shows the circuit of a 4bit register. When a 4bit ata a 3 a 2 a a is applie to the inputs of the four flipflops, they will be store in the register when the flipsflops are triggere by the positive ege of a clock pulse. (a) 3 2 Bit position 3 2 Contents a 3 3 a 2 2 a a Clock (b) Figure. (a) Notation for a 4bit register. (b) Circuit for a 4bit register. The usage of a register is limite if it can only store information. A shift register not only can store information but also can shift its contents to either right or left. The operation of a 4bit shiftright register is shown in Figure.2(a). A circuit iagram for this register is given in Figure.2(b). 3 2 can be shifte to the right one bit in each clock cycle. SR in is an eternal bit shifte into position 3. is lost after the shift. 69
2 The contents are SR in 3 2 after shifting. If is connecte to the input of the leftmost flipflop, i.e. SR in =, the contents will be 3 2 after shifting. This is calle a right rotation. Implementation of a shiftright register is simple. As shown in Figure.2(b), the output of one flipflop is connecte to the input of the net (less significant) flipflop. Figure.2 (a) Operation of a 4bit shiftright register. (b) Circuit of register. (a) 3 2 SR in SR in 3 2 Clock (b) A universal 4bit shiftregister that performs four ifferent functions is introuce. The four functions are hol, shift right, shift left, an parallel loa. The function hol leaves the contents of the register intact after the register is triggere by a clock pulse. Parallel loa allows a 4bit ata to be loae into the register following the positive ege of a clock pulse. The functions an the contents of the register after being triggere by a clock pulse are liste in Table.. The function to be eecute is efine by two selection signals s an s. Table. Function table for a 4bit universal shift register. Function s s Contents Bit position 3 2 Hol 3 2 Shift right SR in 3 2 Shift left 2 SL in Parallel loa a 3 a 2 a a Figure.3 is a esign of the universal 4bit shift register. A 4to multipleer is use to select the ata to be store in each flipflop. The right column in Table. lists 7
3 the contents of the register after an operation has been carrie out. Therefore they are the inputs to the multipleers as shown in Figure.3. SL in is an eternal bit shifte into position for leftshift. a 3 a 2 a a is a 4bit ata to be loae into the register. 4to MUX 3 SR in 2 a to MUX 2 3 a to MUX 2 a to MUX SL in a 2 3 s s CLK Figure.3 esign of a 4bit universal shift register. 7
4 .2 Counters A counter is a synchronous sequential circuit that can generate a sequence of numbers or states. The sequence can be in escening, ascening, or ranom orer. Figure.4 is the state iagram of a counter of si ifferent states. It is calle a 6state counter. The sequence is repeate every si clock cycles. Assume is the initial state, followe by five other states in the orer of,,,, an. The three binary values are the outputs 2,, an of three flipflops use to implement the counter. The timing iagrams for the counter are shown in Figure.5. Present state Net state 2 2 Figure.4 State iagram of a 6state counter. clock 2 State Figure.5 Timing iagram of the 6state counter in Figure.4. 72
5 Ring Counter In a ring counter, each state is represente by one flipflop. An nstate ring counter requires n flipflops. In each state, only one flipflop output is asserte an all the others are easserte. In other wors, only one flipflop output is an all the other flipflop outputs are. Table.2 is the state assignment table for a 4bit or 4state ring counter. The four states are name T, T, T 2, an T 3. State assignment is to assign a combination of flipflop output values to a state, or vice versa. The state iagram of the 4bit ring counter is shown in Figure.6. The asserte output is shifte from left to right an Table.2 State assignment table for a 4state ring counter State 2 3 T T T 2 T 3 Reset T T T 3 T 2 Figure.6 State iagram of a 4state ring counter. V cc Reset 2 3 C P C P C P C P Clock Figure.7 Circuit iagram for a 4bit ring counter. 73
6 is rotate to the leftmost position from the rightmost position. The state transition is T T T 2 T 3 T. Figure.7 is the circuit iagram for the 4state ring counter. Note that it is essentially a rightrotate register. Asynchronous clear (C) an preset (P) are use to initialize the counter to the initial state T by applying a positive pulse to the Reset input. All asynchronous preset an clear inputs are easserte uring normal counting..3 Analysis of Synchronous Sequential Circuits Analysis is the reverse of synthesis or esign. It is a process to unerstan the function of a circuit. Two moels of synchronous sequential circuits are use to show the proceure in analysis. Moore Moel The circuit iagram for a synchronous sequential circuit of Moore moel is given in Figure.8. The circuit has one input, one output Z, an two JK flipflops. The combinational portion of the sequential circuit consists of one AN gate an one XOR gate. The analysis can be carrie out in a number of steps. J clock K 2 Z J K Figure.8 Synchronous sequential circuit of Moore moel for analysis. Step : Write the ecitation an output functions. J 2 = K 2 = J = K = 2 Z = 2 Step 2: Substitute the ecitation functions into the characteristic equations for the two flipflops to get the netstate equations. 74
7 2 = J 2 2 K 2 2 = 2 ( ) 2 = = J K = ( 2 ) = 2 2 Step 3: Convert the netstate equations to netstate maps Figure.9 Netstate maps. Step 4: Convert the netstate maps to a table. The table is calle a transition table because it shows the transition from present states to net states. If the output is also inclue in the table, it is calle a transition/output table. Table.3 Transition/output table. 2 2 = = Step 5: Replace the states in the transition/output table using the state assignment in Table.4. The transition/output table is converte to a state/output table. Z Table.4 State assignment. Table.5 State/output table. 2 State Present state Net state = = A A A C B B A C C C C B Z 75
8 Step 6: Convert the state/output table to a state iagram. A/ B/ / C/ Figure. Moore moel state iagram. In this eample, the output of the circuit is a function of 2 an. It oes not epen on the present input of. Therefore the output is place together with the state name insie the circle. A synchronous sequential circuit is calle a Moore moel machine if the outputs are functions of the present state but not of the present inputs. A synchronous sequential circuit with a finite number of states is also calle a finitestate machine. Mealy Moel The circuit in Figure. is a sequential circuit of Mealy moel. The output of this circuit epens on the present state as well as the present input. The proceure for analyzing a Mealy moel machine an a Moore moel machine are the same, ecept some minor ifferences ue to ifferent types of outputs. 2 Z clock T Figure. Synchronous sequential circuit of Mealy moel for analysis. 76
9 Step : Write the ecitation an output functions. 2 = ( 2 ) T = 2 = ( 2 ) = 2 Z = 2 Step 2: Substitute the ecitation functions into the characteristic equations to get the netstate equations. 2 = 2 = ( 2 ) = 2 = T = 2 Step 3: Convert the netstate equations to netstate maps. is the same as the function in Eample Figure.2 Netstate maps. Step 4: Convert the netstate maps to a transition/output table. Note that the values of Z o not have to be liste separately. They are place net to the values of 2 because Z is also a function of 2,, an. Table.6 Transition/output table. 2 2, Z = =,,,,,,,, 77
10 Step 5: Convert the transition/output table to a state/output table using the state assignment in Table.7. Table.7 State assignment. Table.8 State/output table. 2 State Present state Net state, output = = A A A, B, B B C, A, C C, C, B, A, Step 6: Convert the state/output table to a state iagram. Because Z is a function of the present state an the input, its values are place after an separate by a slash. / A / / B / / / / C / Figure.3 Mealy moel state iagram..4 esign of Counters The esign of a logic circuit usually starts with a wor escription of the function or behavior of the circuit. In synchronous sequential circuit esign, a state iagram is usually constructe first from the wor escription. Construction of a state iagram probably is the most ifficult step in the esign proceure. Lack of unerstaning in the behavior of a circuit may lea to an incorrect state iagram. Sample inputs an their corresponing outputs may be rawn in the form of timing iagrams or in other forms to better unerstan the behavior of the circuit. The rest of the esign proceure can more or less follow the analysis proceure in reverse orer. 78
11 .4. Counter esign The esign of an 8state counter is given to illustrate the esign proceure. The sequence is in the orer of,, 2, 3, 4, 5, 6, 7,... More specifically, it is calle a moulo8 counter. The state that is also the outputs is 2. As shown in Table.9, a transition table, after being constructe from the state iagram in Figure.4, is converte to three netstate maps in Figure.5. The netstate equations can be obtaine irectly from the netstate maps. 2 = = 2 ( ) 2 = ( ) 2 ( ) 2 = ( ) 2 = = = Table.9 Transition table for moulo8 counter. Figure.4 State iagram for a moulo8 counter. Present state 2 Net state Figure.5 Netstate maps for moulo8 counter. The net step is to etermine the ecitation functions. It is necessary to ecie what type of flipflops to use in the esign before the ecitation functions can be etermine. The use of flipflops will first be emonstrate because of its simple characteristic. 79
12 esign with FlipFlops Because the ecitation is the same as the net state for flipflops, the ecitation functions are available without further erivations. Figure.6 is the circuit iagram of the counter using flipflops. 2 = 2 = ( ) 2 = = = = 2 clock Figure.6 Circuit iagram for moulo8 counter. esign with JK FlipFlops by Ecitation Table In analysis, the netstate equations are obtaine by substituting the ecitation functions into the characteristic equations. is a function of the ecitations or flipflop inputs an the present state. In esign, the ecitations are to be etermine from an. The information of an is given by the netstate maps or netstate equations. The characteristic table for JK flipflops provies if J, K, an are given. The ecitation table etermines the values of J an K if an are given. The ecitation table for JK flipflops is given in Table.. From the table, it is seen that each combination of an values can result from two ifferent functions of JK flipflops. For eample, for the transition of from to, it can be either no change or reset. The JK values for those two functions are an respectively. Thus the value of J is. The value of K can be either or, which is enote by a on tcare value. By using the ecitation table, the flipflop inputs J i an K i for i =,, 2 can be etermine as shown in Table.. The first two columns are the transition table in 8
13 Table.9. To etermine the ecitations for state transitions, the transition from 2 = to is eplaine. For the transition of 2 from to, J 2 = an K 2 =. For to change from to, J = an K =. For to change from to, J = an K =. After the ecitations have been etermine, Table. becomes the truth table for all J i an K i after removing the highlighte column for 2. Table. Ecitation table for JK flipflops. J K Function No change (JK = ) or reset (JK = ) Set (JK = ) or toggle (JK = ) Reset (JK = ) or toggle (JK = ) No change (JK = ) or set (JK = ) Table. J an K ecitations for a moulo8 counter. Present state 2 Net state 2 Ecitations J 2 K 2 J K J K 2 J J 2 2 J 2 K 2 K Figure.7 Kmaps for ecitation functions. K 8
14 The Kmaps for the ecitation functions in Table. are plotte in Figure.7. The simplest sumofproucts epressions for the ecitation functions are J 2 = J = J = K 2 = K = K = esign with JK FlipFlops by Partition esign of synchronous sequential circuits with JK flipflops using the ecitation table is straightforwar but teious. A better metho that partitions a netstate map into two submaps, one for J an one for K, is introuce. If a synchronous sequential circuit consists of n JK flipflops an A set of eternal inputs X, the netstate equation i for flipflop i is a function of all the flipflop outputs an X. As shown below, i can be epane to two subfunctions by Shannon s epansion theorem. i ( n, n 2,..., i,...,,, X) = i i ( n, n 2,..., i =,...,,, X) i i ( n, n 2,..., i =,...,,, X) By comparing the above equation with the characteristic equation of JK flipflops which is i = J i i K i i It is seen that J i an K i are in fact the two subfunctions of i with i as the epansion variable. J i = i ( n, n 2,..., i =,...,,, m, m 2,.,, ) = ( i ) i = K i = i ( n, n 2,..., i =,...,,, m, m 2,.,, ) = ( i ) i = The epansion of the netstate equation for i is shown in the following binary iagram. i ( n, n 2,..., i,...,,, X) Netstate equation for flipflop i J i = ( i ) i = K i = ( i ) i = Figure.8 Epansion of netstate equation into J an K ecitations. 82
15 From the net state equations of the moulo8 counter, which are 2 = ( ) 2 = = the ecitation functions can be obtaine as follows: J 2 = ( 2 ) 2 = = ( ) = K 2 = [( 2 ) 2 = ] = [( ) ] = J = ( ) = = = K = [( ) = ] = ( ) = J = ( ) = = K = [( ) = ] = The results are ientical to those using the ecitation table. esign with T FlipFlops A T flipflop can perform two functions, either no change or toggle. The ecitation table can be reaily constructe, as shown in Table.2. When =, it is no change, T =. When, the state is toggle, T =. Therefore the ecitation equation is T = Table.2 Ecitation table for T flipflops. T Function Hol (No change) Toggle Toggle Hol (No change) The ecitation functions for the moulo8 counter can be obtaine by substituting the netstate equations into the above equation. 83
16 T 2 = 2 2 = 2 ( ) 2 = T = = = T = = = The Kmaps for the ecitation functions can also be erive irectly from the netstate maps. By eamining the ecitation equation, it is apparent that T i = i when i =. When i =, T i = ( i ). Therefore the Kmap for T i can be obtaine from the netstate map i by complementing the portion in which i =. The Kmaps for T 2, T, an T are shown in Figure.9. The highlighte portion in each map is the complement of the netstate map T 2 Figure.9 Kmaps for the ecitations of T flipflops. T T.4.2 SelfCorrecting Counter The state iagram for a 6state counter is given in Figure.2. The transitions of states are not in escening or ascening orer. It is a ranom orer. Three flipflops are require in the implementation of this counter. States 2 an 7 are not use. They are calle unuse or invali states. If for any reason the counter starts from an unuse state or goes astray to one of the unuse states, it shoul be able to return to the normal count sequence. Such a counter is sai to be selfcorrecting. Table.3 is the transition table. The netstate of an unuse state is a on'tcare state. Netstate verification for the two unuse states is require at the completion of esign to ensure that the counter is selfcorrecting. The following ecitation functions are obtaine from the netstate maps in Figure.2 if flipflops are use. 2 = 2 = 2 = = 2 2 = ( 2 ) = = 2 84
17 Figure.2 State iagram for a 6state selfcorrecting counter. Table.3 Transition table for a 6state selfcorrecting counter. Present state 2 Net state Figure.2 Netstate maps for the 6state selfcorrecting counter. The netstate of an unuse state can be etermine by substituting the values of 2 into the above equations. An easier approach is to eamine the groupings of  cells on the netstate maps. A on tcare value is equal to if it is groupe with cells. Otherwise it is. Eamination of the on tcare values on the netstate maps shows that the net states of an are an respectively. If the counter happens to be in the state, it will stay in this state forever an cannot return to the normal sequence. Since the counter is not selfcorrecting, a ifferent esign is necessary Figure.22 Reesign of the 6state selfcorrecting counter. In reesigning the counter, the on tcare terms on the netstate map are left out in grouping. The groupings for 2 an remain unchange. The ecitation function is 85
18 = = 2 2 = ( 2 ) The netstates of an are now an respectively. Thus the counter is selfcorrecting. To implement the counter using JK flipflops, each of the netstate maps in Figure.2 is partitione into two subfunction maps as shown in Figure.23. The K maps in the secon row of Figure.24 are the Kmaps for K 2, K, an K. They are inverte to the Kmaps for K 2, K, an K in the thir row of the figure. The ecitation functions are J 2 = ' K 2 = J = 2 2 = ( 2 ) K = J = 2 K = J 2 = ( 2 ) 2 = J = ( ) = J = ( ) = 2 2 K 2 = ( 2 ) 2 = K = ( ) = K = ( ) = 2 2 K 2 K K Figure.23 Kmaps for JK ecitations. There are various ways to etermine the netstates of the two unuse states. One of them is to fin the net state from the following netstate equations. 86
19 2 = J 2 2 K 2 2 = 2 ( ) 2 = 2 2 = J K = ( 2 ) () = 2 2 = J K = 2 2 = 2 By substituting 2 by in the netstate equations, 2 =. With 2 =, the values of 2 in the netstate equations are. Upown SelfCorrecting Counter The state iagram shown in Figure.24 is another eample of a 6state counter. However, the state transitions can also be in the reverse irection. It is calle an upown counter. Upcount an owncount are controlle by an eternal signal C. When C =, the counting is in the up or forwar irection. When C =, the counting is in the own or backwar irection. Net states are etermine not only by present states but also by C. The transition table is given in Table.4. The netstate maps are shown in Figure.25. The counter is implemente using T flipflops. The Kmaps for T 2, T, an T are obtaine from the netstate maps in Figure.25 using the metho evelope in Section.4. an shown in Figure.26. The highlighte cells are the complements of the corresponing cells in Figure.26. C = C = Figure.24 State iagram for a 6state upown counter. The Kmaps for the ecitations in Figure.27 show high contents of XOR. T 2 = C C = (C ) T = (C ) (C ) = (C ) T = (C ) (C ) = (C ) 87
20 Table.4 Transition table for a 6state upown counter. Present state Net state 2 2 C = C = 2 C 2 2 C 2 C Figure.25 Netstate maps for a 6state upown counter. 2 C T 2 2 C T 2 C T Figure.26 T ecitations for the 6state upown counter in Figure.26. The net states of the unuse states can be rea off irectly from the Kmaps for the ecitations T 2, T, an T. Note that the values for the highlighte cells in Figure.26 shoul be complemente. The netstate maps obtaine from Figure.26 are 88
21 shown in Figure.27. The netstates of the two unuse state rea from Figure.27 are as follows. They are inepenent of the value of C. 2 = 2 = 2 = 2 = 2 C 2 2 C Figure.27 Netstate maps for a 6state upown counter after esign. 2 C.5 Synthesis of Synchronous Sequential Circuits In the esign of a counter, the state iagram can be constructe very easily from a given counting sequence. In general, such is not the case for a synchronous sequential circuit. Sometimes, it is helpful to unerstan the problem by generating a sample input sequence an its corresponing output sequence. A bitsequence etector or recognizer is use as an eample. A bitsequence etector is a synchronous sequential circuit to etect a specific sequence applie to a single input. One bit is inputte to the circuit in each clock cycle. When a specific input sequence is etecte, the output of the circuit becomes ; otherwise the output is. The sequence to be etecte in this eample is a 3bit sequence. After a sequence of is etecte, the circuit starts to etect the net sequence. No part in one sequence can be use as part of the net sequence. This is referre to as a nonoverlapping sequence. The esigns for both Moore moel an Mealy moel will be illustrate. Moore Moel A sample sequence of input an its corresponing output Z are liste in Table.5. All sequences of are highlighte. The output will not become until the clock cycle after the sequence has been etecte. If Z becomes in the same clock cycle as the thir bit, the output is a function of the input. This is then a Mealy moel. For instance, if Z = in clock cycle 7 because of the input sequence in clock cycles 5, 6, an 7, what is 89
22 the value of Z in clock cycle 7 if the input is in clock cycle 7? Z will be, not. The value of Z in clock cycle 7 now epens on the value of. Table.5 Sample input/output sequence for a Moore moel bitsequence etector. Clock cycle Input. Output Z Before constructing the state iagram, it is realize that four ifferent conitions may occur uring etection. Conition A: Nothing has been etecte, not even the first bit of the sequence. Conition B: The first bit,, has been etecte. Conition C: The first two bits,, have been etecte. Conition : All three bits,, have been etecte. A/ B/ / C/ Figure.28 State iagram for a circuit of Moore moel to etect. Therefore, the minimum number of states is four. Sometimes, a state iagram with etra states may be constructe. The state iagram may still be correct. But this will increase the amount of components to be use. For eample, four states can be represente by two flipflops. Five states require three flipflops. For one state iagram with si states an another with eight states, both nee three flipflops. However, the one with si states has two unuse states, the net states of which are on tcare states. With more on t care terms on the netstate or ecitation maps, the ecitation functions may be simpler. Various techniques can be use to minimize a state iagram. But it is not the topic in this chapter. Since the behavior of a synchronous sequential circuit can be escribe by a finite number of states. It is also calle a finitestate machine. 9
23 The state iagram for the bit sequence etector is constructe in Figure.28 base on the four conitions. The state iagram is converte to a state/output table in Table.6. The net step is state assignment. For the four combinations of flipflop output values,,,, an, one of them is assigne to state A. There are four choices. After one of them is selecte for A, there are three combinations left for state B. Then there will be two combinations left for state C. Finally, only one combination is left for state. Thus, there are = 24 ifferent ways to assign the four combinations of values to the four states. A goo assignment will reuce the amount of components use to realize the circuit. The topic of how to get a goo state assignment is not covere here. A ranom assignment as the one in Table.4 is use. The state/output table is transforme to a transition/output table in Table.7. The netstate maps are shown in Figure.29. They are partitione to obtain the JK ecitations in Figure.3. A circuit iagram is given in Figure.3. J 2 = K 2 = ( ) J = K = 2 Z = 2 Table.6 State/output table for bitsequence etector. Table.7 Transition/output table for bitsequence etector. Present state Net state 2 Z 2 = = = = A A B B C B C A A B Z Figure.29 Netstate maps for the bit sequence etector. 9
24 2 J 2 = ( 2 ) 2 = J = ( ) = 2 K 2 = [( 2 ) 2 = ] K = [( ) = ] Figure.3 Kmaps for the ecitations of the bit sequence etector. J 2 clock K Z J K Figure.3 Sequential circuit of Moore moel to etect a sequence of. Mealy Moel To esign the bit sequence etector for as a Mealy moel, a sample input/output sequence is given in Table.8. Overlapping is not allowe. Table.8 Sample input/output sequence for a Mealy moel bitsequence etector. Clock cycle Input. Output Z. 92
25 For Mealy moel, the output becomes in the same clock cycle when the thir bit of the sequence is etecte. There is no nee to wait until the net clock cycle to generate an output of an it saves one state. The three conitions require for a Mealy moel are Conition A: Nothing has been etecte, not even the first bit of the sequence. Conition B: The first bit,, has been etecte. Conition C: The first two bits,, have been etecte. If present input =, Z =. If =, Z =. The state iagram base on the above conitions is plotte in Figure.32. The state iagram is converte to a state/output table in Table.9. By using the following state assignments 2 = 2 = 2 = 2 = for states A for states B for states C Unuse state the state/output table is converte to the transition/output table in Table.2. Note that / A / B / /, / / C Figure.32 State iagram of a Mealy moel circuit for etecting a sequence of. Table.9 State/output table for bitsequence etector. Table.2 Transition/output table for bitsequence etector. Present state Net state, Z 2, Z 2 = = = = A A, B,,, B C, B,,, C A, A,,,,, 93
26 The transition/output table is further converte to two net state maps an the Kmap for Z in Figure.33, from which the following ecitation an output functions are obtaine. A circuit iagram is given in Figure.34. J 2 = K 2 = J = 2 K = Z = Figure.33 Netstate maps an output Kmap. Z J 2 clock K J Z V cc K Figure.34 Sequential circuit of Mealy moel to etect a sequence of. Overlapping of Sequences If overlapping is allowe in the etection of the sequence, the state iagrams for Moore moel an Mealy moel can be easily moifie. For Moore moel, state represents the following situation. A sample input/output sequence for Moore moel with consieration of overlapping is given in Table.9. 94
27 Table.9 Sample input/output sequence for a Moore moel bitsequence etector with overlapping. Clock cycle Input. Output Z Conition : All three bits,, have been etecte. It is a state for the thir bit of the sequence just etecte an for the first bit of the net sequence. Therefore, if the input is in state, the first two bits of the net possible sequence,, have been etecte. The net state shoul then be C. If the input is in state, the secon bit of the previous sequence can be ignore because only one bit is neee for the first bit of a new sequence. Thus the transition is from state to state B. The moifie state iagram for Moore moel is given in Figure.35. A/ B/ / C/ Figure.35 Moore moel state iagram for overlapping sequences. To moify the state iagram to allow overlapping for Mealy moel, a sample input/output sequence is shown in Table.29. Conition C is eplaine below. Conition C: The first two bits,, have been etecte. If the present input =, Z =. If =, Z =. When =, it also serves as the first bit of the net sequence an the net state is state B. Table.2 Sample input/output sequence for a Mealy moel bitsequence etector with overlapping. Clock cycle Input. Output Z. 95
28 The moifie state iagram is given in Figure.36. / / A B / / / / C Figure.36 Mealy moel state iagram for overlapping sequences. PROBLEMS. Analyze the synchronous sequential circuit in Figure P. using the following state assignment: A: B: C: : 2. Repeat Problem for the synchronous sequential circuit in Figure P.2. J Z clock Figure P. K J K 96
29 z Figure P.2 clock T 3. Given below are the ecitation an output functions of a Moore moel synchronous sequential circuit. J = ( ) K = T = Z = Analyze the synchronous sequential circuit. 4. Given below is the transition table for an 8state counter known as Johnson counter. Realize the counter using flipflops Given below are the state table an state assignment for a synchronous sequential circuit. Realize the circuit using flipflops. State assignment 2 Present state A B C E Net State, output = = B, E, A, C, B, C, C, E,, A, 97
30 6. Realize the following Moore moel state table using (a) flipflops, (b) JK flipflops. State assignment Present state Net state Output Z = = A B C B B A A C C 7. Realize the following state table using (a) flipflops, (b) T flipflops, an (c) JK flipflops. State assignment Present state A B C Net state, output = = A, C,, B, B, B, B, A, 8. Realize the following state table using JK flipflops. State assignment 2 Present state A B C E F Net State, output = = B,, A, C,, C, B, E, C, A, E, F, 9. Construct a state iagram for a synchronous sequential circuit that etects an input sequence of. The output z is when the sequence is etecte. Otherwise z is. Sequences are allowe to overlap. A sample input/output is given below. Input Output z. esign a synchronous sequential circuit of Moore moel that recognizes the input sequence. The output Z is when the sequence is etecte. Otherwise Z is. Use flipflops in the realization. A sample input/output is given below. Input Output z 98
31 . esign the bitsequence recognizer in Problem as a Mealy moel machine. 2. esign a synchronous sequential circuit of Moore moel that recognizes the input sequence. When the sequence is etecte, the output z becomes. z will return to after two consecutive s are etecte. The circuit will then start the etection of the net sequence. Use T flipflops. A sample input/output sequence is given below. Input Output z 99
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