CPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner

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1 CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2

2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections Register Cell The Register File Read Appendix B CPS4 GBL.2 RW Fall 2

3 Overflow Detection and Carries In Addition and Subtraction operations, Overflow occurs when two number of same sign are added, and result has different sign. Must be a function of what happens in high-order full-adder A 3 B 3 Cin 3 S 3 Cout 3 OVF Cin= Cout F Y T N F Y F Y F Y F Y T N F Y CPS4 GBL.3 RW Fall 2

4 Add/Subtract With Overflow detection Overflow S n- S n- 2 S S Full Adder Full Adder Full Adder Full Adder Add/Sub b n- a n- b n- 2 a n- 2 b a b a CPS4 GBL.4 RW Fall 2

5 MIPS ALU Slice Cin a b 3 2 A F a + b a - b - NOT b - 2 a OR b - 3 a AND b Add/sub 2 Cout Add/sub F CPS4 GBL.5 RW Fall 2

6 The MIPS ALU Overflow = Zero n- n-2 ALU Slice ALU Slice ALU Slice ALU Slice ALU control b n- a n- b n-2 a n-2 b a b a CPS4 GBL.6 RW Fall 2

7 CPS4 GBL.7 RW Fall 2 Shifter a a a2 a3 a4 a5 a6 a Shift- Shift-2 Shift-4

8 Memory Elements All the circuit we looked at so far are combinational circuits: the output is a Boolean function of the inputs. We need circuits that can remember values. (registers) The output of the circuit is a function of the input AND a function of a stored values (state). Circuits with memory are called sequential circuits. CPS4 GBL.8 RW Fall 2

9 Reset-Set Latch S R R S A() E() F F F F S F F T T S F T F T U F T T T S T F F F S T F T F U T T F F? T T T F U R S F F F T T T F F T T - Pick a wire in each cycle, call it a variable. (Here, ). A() = Activation of = current value of. Treat as input. E() = Excitation of = next future value of. Treat as output. When A()=E(), circuit is stable = doesn t change state When A()!=E(), circuit state goes from A() to E() CPS4 GBL.9 RW Fall 2

10 Reset-Set Latch (cont.) S S R R With S== and R==, BOTH states of wire are stable. CPS4 GBL. RW Fall 2

11 CPS4 GBL. RW Fall 2 Reset-Set Latch (cont.) S R S R S R S R R e s e t S e t

12 Data-Latch Data Enable D E - Negative Edge D-Latch CPS4 GBL.2 RW Fall 2

13 Data-Latch (cont.) Data Enable D E - Positive Edge D-Latch CPS4 GBL.3 RW Fall 2

14 Data Master-Slave Data-Flip-Flop Master Slave Clock While Clock false (low) D is copied to the master stage and the slave is stable. On Clock the Master stage is transferred into the slave stage (output), and the master stage is stable until Clock falls again. CPS4 GBL.4 RW Fall 2

15 Data DFF Timing M Clock Clock D M Time CPS4 GBL.5 RW Fall 2

16 Tri-State Driver The Tri-State driver is like a (one directional) switch: When Enable is on (E=) it transfers the input to the output. When Enable is off (E=) it disconnects the output from the input. D E D E - Z E Z :- High Impedance D CPS4 GBL.6 RW Fall 2

17 Bus Connections The Bus: Many to many connections. Mutual exclusion: At most one Enable is on! D n- D n-2 D D E n- E n-2 E E CPS4 GBL.7 RW Fall 2

18 Register Cells on a bus RE D E D latch WE RE D E D latch WE RE D E D latch WE RE D E D latch WE One can source and sink from any cell on the bus by activating the right controls (WE and RE). CPS4 GBL.8 RW Fall 2

19 3-Port Register Cell Data-In Bus-C Bus-B DinEnable OutA OutB Bus-A CPS4 GBL.9 RW Fall 2

20 3-Port Register EC EA EB Bus-C Bus-B Bit-2 Bus-A Bus-C Bus-B Bit- Bus-A Bus-C Bus-B Bit- CPS4 GBL.2 RW Fall 2 Bus-A

21 Address Decode circuit Bus-C Bus-B Bus-A Register address: For different address, change dots A A EA B B EB C C CPS4 GBL.2 EC RW Fall 2

22 Register File Reg-3 Reg-2 Reg- Reg- A3 B3 C3 A2 B2 C2 A B C Addresses selected by bubbles on AND gates A B C A-En Add-A Add-A B-En Add-B Add-B C-En Add-C Add-C CPS4 GBL.22 RW Fall 2

23 Summary So far we saw how to take a Boolean function and generate a circuit that realizes the function. We learned to construct circuits that can add and subtract. We learned about the ALU: a circuit that can add, subtract, detect overflow, compare, and do bit-wise operations (AND, OR, NOT) Saw how to construct a shifter circuit. Learned about the memory elements: RS-Latch, D-Latches and D-Flip-flops. Learned about Tri-State drivers and BUS Communication. (many-to many) Learned how to construct a register file. Saw how control signals can modify what the circuit will do with inputs. Examples: ALU, Shift, Register read-write,... CPS4 GBL.23 RW Fall 2

ALU A functional unit

ALU A functional unit that performs arithmetic operations such as ADD, SUB, MPY logical operations such as AND, OR, XOR, NOT on given data types: 8-,16-,32-, or 64-bit values A n-1 A n-2... A 1 A 0 B n-1