Design at the Register Transfer Level

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1 Week-7 Design at the Register Transfer Level Algorithmic State Machines

2 Algorithmic State Machine (ASM) q Our design methodologies do not scale well to real-world problems. q Logic Design / Algorithmic State Machines (ASM) 2

3 Algorithmic State Machine (ASM) q Procedure for implementing a problem with a given piece of equipment. q Define digital algorithmic solutions for hardware. q Resembles a conventional flow chart but interpreted differently: ASM describes the sequence as well as the timing of events. Adapted to specify the control sequence and data processing operations Logic Design / Algorithmic State Machines (ASM) 3

4 Control and Datapath q A digital system can be split into two components: q Datapath: Manipulates data according to the system requirements. q Control (Unit/Logic): Generates the signals for sequencing the operations in the data processor Logic Design / Algorithmic State Machines (ASM) 4

5 State Box Logic Design / Algorithmic State Machines (ASM) 5

6 Decision Box Logic Design / Algorithmic State Machines (ASM) 6

7 Conditional Box Logic Design / Algorithmic State Machines (ASM) 7

8 ASM Block q q q q One entrance path Any number of exit paths Describes the state of the system during one clock-pulse interval. The operations within the state and the conditional boxes are all executed with a common clock pulse while the system is in state T Logic Design / Algorithmic State Machines (ASM) 8

9 ASM chart State diagram Logic Design / Algorithmic State Machines (ASM) 9

10 Timing All the following operations occur simultaneously (in parallel): A ß A+1 If E == 1 then R ß 0 Depending on the values of E and F, the state is changed to T 2, T 3 or T Logic Design / Algorithmic State Machines (ASM) 10

11 Design Problem q Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flipflops of A are denoted by A 4, A 3, A 2, and A 1 (where A 4 holding the MSB). q A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A 3 and A 4 determine the sequence of operations: If A 3 == 0, E is cleared to 0 and the count continues. If A 3 == 1, E is set to 1; then if A 4 == 0, the count continues, but if A 4 == 1, F is set to 1 on the next clock pulse and the system stops counting Logic Design / Algorithmic State Machines (ASM) 11

12 Control & Datapath Status Signals Logic Design / Algorithmic State Machines (ASM) 12

13 ASM Chart q q Design a digital system with two flipflops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A 4,A 3,A 2, and A 1 (where A 4 holding the MSB). A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A 3 and A 4 determine the sequence of operations: If A 3 == 0, E is cleared to 0 and the count continues. If A 3 == 1, E is set to 1; then if A 4 == 0, the count continues, but if A 4 == 1, F is set to 1 on the next clock pulse and the system stops counting Logic Design / Algorithmic State Machines (ASM) 13

14 Sequence of Operations Counter Flip-flops Conditions State A4 A3 A2 A1 E F A3=0, A4= L A3=1, A4= L A3=0, A4= L T 1 L1, L3 L T T Logic Design / Algorithmic State Machines (ASM) 14

15 Sequence of Operations Counter Flip-flops Conditions State A4 A3 A2 A1 E F A3=0, A4=0 T A3=1, A4= A3=0, A4= T T Logic Design / Algorithmic State Machines (ASM) 15

16 The Datapath Logic Design / Algorithmic State Machines (ASM) 16

17 The Datapath Logic Design / Algorithmic State Machines (ASM) 17

18 State Diagram for Control Logic Design / Algorithmic State Machines (ASM) 18

19 State Table Present state symbol Present state Inputs Next state Outputs G0 G1 S A3 A4 G0 G1 T0 T1 T2 T X X T X X T1 0 1 X 0 X T1 0 1 X T1 0 1 X T2 1 1 X X X Logic Design / Algorithmic State Machines (ASM) 19

20 State Table Present state symbol Present state Inputs Next state Outputs G0 G1 S A3 A4 G0 G1 T0 T1 T2 T X X T X X T1 0 1 X 0 X T1 0 1 X T1 0 1 X T2 1 1 X X X q D G0 = T 1 A 3 A 4 q D G1 = T 0 S + T 1 q T 0 = G 1 q T 1 = G 0 G 1 q T 2 = G Logic Design / Algorithmic State Machines (ASM) 20

21 Control Logic Logic Design / Algorithmic State Machines (ASM) 21

22 Control Logic Logic Design / Algorithmic State Machines (ASM) 22

23 Recall q What s an ASM? q What are the components? q What s the design procedure? Logic Design / Algorithmic State Machines (ASM) 23

24 Binary Multiplier q How do we do multiplication by hand? In binary? multiplicand multiplier product Logic Design / Algorithmic State Machines (ASM) 24

25 High-Level View Logic Design / Algorithmic State Machines (ASM) 25

26 Datapath for Binary Multiplier Sum only two binary numbers accumulating the partial sums in Register Q. Instead of shifting the multiplicand to the left, shift the product to the right Logic Design / Algorithmic State Machines (ASM) 26

27 ASM for Binary Multiplier P: the number of bits in the registers Logic Design / Algorithmic State Machines (ASM) 27

28 Initial State Register B 10111! Z=0 =1 101! P 0! 00000! 10011! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 28

29 Q0 = 1; add B first partial product 10111! 00000! ! ! Register B 10111! Z=0 =1 100! P 0! 10111! 10011! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 29

30 Shift Right CAQ Register B 10111! Z=0 =1 100! P 0! 01011! 11001! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 30

31 Q0 = 1; add B second partial product 10111! 01011! ! ! Register B 10111! Z=0 =1 011! P 1! 00010! 11001! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 31

32 Shift right CAQ Register B 10111! Z=0 =1 011! P 1! 10001! 01100! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 32

33 Q0 = 0; Shift right CAQ Register B 10111! Z=0 =0 010! P 1! 01000! 10110! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 33

34 Q0 = 0; Shift right CAQ Register B 10111! Z=0 =0 001! P 0! 00100! 01011! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 34

35 Q0 = 1; Add B fifth partial product 10111! 00100! ! ! Register B 10111! Z=0 =1 000! P 0! 11011! 01011! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 35

36 Shift right CAQ Register B 10111! Z=1 =1 000! P 0! 01101! 10101! C Register A Register Q Logic Design / Algorithmic State Machines (ASM) 36

37 Trace of the Binary Multiplication Initial conditions : B=10111 C A Q P Multiplier in Q 0! 00000! 10011! 101! Q0 = 1; add B 10111! First partial product 0! 10111! 100! Shift right CAQ 0! 01011! 11001! Q0=1; add B 10111! Second partial product 1! 00010! 011! Shift right CAQ 0! 10001! 01100! Q0=0; shift right CAQ 0! 01000! 10110! 010! Q0=0; shift right CAQ 0! 00100! 01011! 001! Q0=1; add B 10111! Fifth partial product 0! 11011! 000! Shift right CAQ 0! 01101! 10101! Final product in AQ = Logic Design / Algorithmic State Machines (ASM) 37

38 Making the design of the control logic easier Z= Logic Design / Algorithmic State Machines (ASM) 38

39 Control Logic Signals to be generated: T 0 -T 3 L (The Load signal for Register A, that allows the loading the sum into register A Logic Design / Algorithmic State Machines (ASM) 39

40 Control Circuit implemented with D flip-flops + Decoder Logic Design / Algorithmic State Machines (ASM) 40

41 One FF per state T 0 = T 0 S + T 3 Z T 1 = T 0 S T 2 = T 1 + T 3 Z T 3 = T 2 Z= Logic Design / Algorithmic State Machines (ASM) 41

42 ASM with Four Control Inputs Operations are left blank. We are interested in the design of the control part only. Four control inputs: w, x, y, z Four states: T 0 -T 3 needs 2 flip-flops Logic Design / Algorithmic State Machines (ASM) 42

43 Using MUX es to implement the control Two D flip-flops encode the state. The state is decoded into state signals T 0 -T 3 by a decoder. The current state multiplexes the next state. Challenge: how to set the inputs of the MUX es? logic Logic Design / Algorithmic State Machines (ASM) 43

44 Multiplexer Inputs Present state Next State Input conditions Multiplexer inputs G1 G2 G1 G2 MUX1 MUX w 0 w w x 1 x x y yz +yz = yz y yz y z y+y z Y = y+z y z yz y z+y z = y Logic Design / Algorithmic State Machines (ASM) 44

45 The complete circuit Logic Design / Algorithmic State Machines (ASM) 45

46 Count-of-Ones The system consists of two registers R1 and R2 and a flip-flop E. The system counts the number of 1 s in the number loaded into R1 and set R2 to that number. Shift one bit from R1 into E. If E == 1 then R2++ If Z = = 1 (that is R1 == 0) then stop. R2 is initialized to all 1 s. Why? Logic Design / Algorithmic State Machines (ASM) 46

47 Datapath for Count-of-Ones Logic Design / Algorithmic State Machines (ASM) 47

48 Multiplexer Inputs Present state Next State Input conditions Multiplexer inputs G1 G2 G1 G2 MUX1 MUX S 0 S S Z Z Z None E E E E Logic Design / Algorithmic State Machines (ASM) 48

49 Control Logic for Count-of-Ones Logic Design / Algorithmic State Machines (ASM) 49

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