Chapter #7: Sequential Logic Case Studies Contemporary Logic Design

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1 hapter #7: Sequential Logic ase Studies ontemporary Logic Design No. 7- Storage egister Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines 2 LK 3 L D3 D2 D D 7 Q3 9 Q3 Q2 7 Q2 6 Q 2 Q 3 Q Q 5 No. 7-2

2 Input/Output Variations Selective Load apability Tri-state or Open ollector Outputs True and omplementary Outputs LK EN D7 D6 D5 D4 D3 D2 D D Q7 9 Q6 6 Q5 Q4 5 2 Q3 9 Q2 6 Q 5 Q Octal D-type FFs with input enable EN enabled low and lo-to-hi clock transition to load new data into register 8 H 7 G 4 F 3 E 8 D LK QH QG QF QE QD Q Q Q OE Octal D-type FFs with output enable OE asserted low presents FF state to output pins; otherwise high impedence No. 7-3 egister Files Two dimensional array of flipflops ddress used as index to a particular word Word contents read or written E WE W W 3 D4 2 D3 D2 5 D 67 Q4 6 Q3 7 Q2 9 Q Separate ead and Write Enables Separate ead and Write ddress Data Input, Q Outputs ontains 6 D-ffs, organized as four rows (words) of four elements (bits) x4 egister File with Tri-state Outputs No. 7-4

3 Shift egisters Storage + ability to circulate data among storage elements Shift \eset Shift Direction LK LK LK LK \eset Shift Shift Shift Q Q 2 Q 3 Q 4 Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element Master Slave FFs: sample inputs while clock is high; change outputs on falling edge No. 7-5 Shift egister I/O Serial vs. Parallel Inputs Serial vs. Parallel Outputs Shift Direction: Left vs. ight Serial Inputs: LSI, SI Parallel Inputs: D,,, Parallel Outputs: QD, Q, Q, Q lear Signal Positive Edge Triggered Devices bit Universal Shift egister S,S determine the shift function S =, S = : Load on rising clk edge synchronous load S =, S = : shift left on rising clk edge LSI replaces element D S =, S = : shift right on rising clk edge SI replaces element S =, S = : hold state Multiplexing logic on input to each FF! Shifters well suited for serial-to-parallel conversions, such as terminal to computer communications No. 7-6

4 Shift egister pplication: Parallel to Serial onversion Parallel Inputs D7 D6 D5 D4 lock D3 D2 D D Sender S S S 94 S 94 LSI LSI D QD D QD Q Q Q Q Q Q SI SI LK LK L L S S 94 LSI D QD Q Q Q SI LK L eceiver S S 94 LSI D QD Q Q Q SI LK L D7 D6 D5 D4 D3 D2 D D Parallel Outputs Serial transmission No. 7-7 ounters - Proceed through a well-defined sequence of states in response to count signal - 3 it Up-counter:,,,,,,,,, - 3 it Down-counter:,,,,,,,,, - inary vs. D vs. Gray ode ounters counter is is a "degenerate" finite state machine/sequential circuit where the the state is is the the only output No. 7-8

5 Johnson (Mobius) ounter \eset S J Q LK K Q Q S J Q Q 2 S J Q Q 3 S J Q Q 4 LK LK LK K Q K Q K Q End-round Shift + Shift Q Q 2 Q 3 Q 4 8 possible states, single bit change per state, useful for avoiding glitches No. 7-9 atalog ounter P T D 63 LK LOD L O 5 QD Q 2 Q 3 Q Synchronous 4-it Upcounter Synchronous Load and lear Inputs Positive Edge Triggered FFs Parallel Load Data from D,,, P, T Enable Inputs: both must be asserted to enable counting O: asserted when counter enters its highest state, used for cascading counters "ipple arry Output" 746: similar in function, asynchronous load and reset No. 7-

6 7463 Detailed Timing Diagram L LOD D LK P T Q Q Q Q D O lear Load ount Inhibit No. 7- ounter Design Procedure Introduction This procedure can be generalized to implement NY finite state machine ounters are a very simple way to start: no decisions on what state to advance to next current state is the output No. 7-2

7 Example: 3-bit inary Upcounter Next Flipflop Inputs Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? Transition Table Flipflop Input Table This is called "emapping the Next Function" No. 7-3 ounter Design Procedure Introduction This procedure can be generalized to implement NY finite state machine ounters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3-bit inary Upcounter Next Flipflop Inputs Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? Transition Table Flipflop Input Table This is called "emapping the Next Function" No. 7-4

8 K-maps for Toggle Inputs: esulting Logic ircuit: + T = \eset T S Q LK Q ount Q T S Q LK Q Q T S Q Q LK Q Timing Diagram: T = \eset Q Q Q ount T = No. 7-5 More omplex ount Sequence Step : Derive the Transition Diagram ount sequence:,,,, Next Step 2: Transition Table No. 7-6

9 Step : Derive the Transition Diagram Sequence:,,,, Next Step 2: Transition Table Note the Don't are conditions No. 7-7 Step 3: K-Maps for Next Functions + = + = + = No. 7-8

10 Step 3: K-Maps for Next Functions No. 7-9 Step 4: hoose Flipflop Type for Implementation Use Excitation Table to emap Next Functions Toggle Inputs Toggle Excitation Table emapped Next Functions No. 7-2

11 ounter Design Procedure More omplex ounter Sequencing Step 4: hoose Flipflop Type for Implementation Use Excitation Table to emap Next Functions Toggle Inputs Toggle Excitation Table emapped Next Functions No. 7-2 emapped K-Maps T T T T = T = T = No. 7-22

12 emapped K-Maps T T T T = + = xor T = + + T = + No esulting Logic: 5 Gates 3 Input Literals + Flipflop connections ount T S T Q LK Q \ T T S Q LK Q T T S Q LK Q \ \ \eset Timing Waveform: ount \eset No. 7-24

13 Self-Starting ounters Start-Up s t power-up, counter may be in possible state Designer must guarantee that it (eventually) enters a valid state Especially a problem for counters that validly use a subset of states Self-Starting Solution: Design counter so that even the invalid states eventually transition to valid state Implementation in Previous Slide! Two Self-Starting Transition Diagrams for the Example ounter No Self-Starting ounters Deriving Transition Table from Don't are ssignment Inputs to Toggle Flip-flops hanges T T + + Transition Table + Next + + T + No. 7-26

14 Implementation with Different Kinds of FFs -S Flipflops ontinuing with the,,,,,,... counter example Next emapped Next Q+ = S + Q S Exitation Table emapped Next Functions No Implementation with Different Kinds of FFs -S Flipflops ontinuing with the,,,,,,... counter example Next emapped Next Q+ = S + Q S Exitation Table emapped Next Functions No. 7-28

15 Implementation with Different Kinds of FFs S FFs ontinued S S = S = = S = = S = S No Implementation with Different Kinds of FFs S FFs ontinued S S S = S = = + S = = S = No. 7-3

16 Implementation With Different Kinds of FFs S FFs ontinued ount \ Q Q Q LK LK LK S Q \ S Q S S Q \ \ \ \ S esulting Logic Level Implementation: 3 Gates, Input Literals + Flipflop connections No. 7-3 Implementation with Different FF Types J-K FFs Next emapped Next Q+ = J Q + K Q J-K Excitation Table emapped Next Functions No. 7-32

17 Implementation with Different FF Types J-K FFs Next emapped Next Q+ = J Q + K Q J-K Excitation Table emapped Next Functions No Implementation with Different FF Types J-K FFs ontinued J J J K K K J = K = J = K = J = K = No. 7-34

18 Implementation with Different FF Types J-K FFs ontinued J J K K J = K = J = K = + J = K = J K No Implementation with Different FF Types J-K FFs ontinued + ount \ J Q J Q J J Q LK LK LK K Q \ K K Q K Q \ \ K \ J esulting Logic Level Implementation: 2 Gates, Input Literals + Flipflop onnections No. 7-36

19 Implementation with Different FF Types D FFs Simplest Design Procedure: No remapping needed! D = D = + D = D Q D D Q D D Q ount LK Q \ LK Q \ LK Q \ \ \ \ D \ D esulting Logic Level Implementation: 3 Gates, 8 Input Literals + Flipflop connections No Implementation with Different FF Types omparison T FFs well suited for straightforward binary counters ut yielded worst gate and literal count for this example! No reason to choose -S over J-K FFs: it is a proper subset of J-K -S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key D FFs yield simplest design procedure est literal count D storage devices very transistor efficient in VLSI est choice where area/literal count is the key No. 7-38

20 synchronous vs. Synchronous ounters ipple ounters Deceptively attractive alternative to synchronous design style ount T Q T Q T Q LKQ LKQ LK Q ount signal ripples from left to right transitions are not sharp! an an lead lead to to "spiked outputs" from from combinational logic logic decoding the the counter's state state No synchronous vs. Synchronous ounters ascaded Synchronous ounters with ipple arry Outputs First stage O enables second stage for counting (2) O goes high (3) High order 4-bits are incremented () Low order 4-bits = O asserted soon after stage enters state also a function of the T Enable Downstream stages lag in their to transitions ffects ount period and decoding logic No. 7-4

21 synchronous vs. Synchronous ounters The Power of Synchronous lear and Load Starting Offset ounters: e.g.,,,,,,,,,,, P T O L K D Q Q D Q Q D L O D L lock Load D + + Load is the state to be loaded Use O signal to trigger Load of a new state Since 7463 Load is synchronous, state changes only on the next rising clock edge No. 7-4 synchronous vs. Synchronous ounters Offset ounters ontinued Ending Offset ounter: e.g.,,,,...,,, L 6 O 3 P T L K D Q Q Q Q D D L O D L lear signal takes effect on the rising count edge Decode state to determine when to reset to eplace '63 with '6, ounter with sync lear lear takes effect immediately! No. 7-42

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