Menu. Excitation Tables (Bonus Slide) EEL3701 EEL3701. Registers, RALU, Asynch, Synch

Size: px

Start display at page:

Download "Menu. Excitation Tables (Bonus Slide) EEL3701 EEL3701. Registers, RALU, Asynch, Synch"

Gladys Potter
5 years ago
Views:

1 Menu Registers >Storage Registers >Shift Registers More LSI Components >Arithmetic-Logic Units (ALUs) > Carry-Look-Ahead Circuitry (skip this) Asynchronous versus Synchronous Look into my... 1 Excitation Tables (Bonus Slide) Q + =D Q + =TQ' + T'Q Q + =S + R' Q Q + =J Q' + K' Q 2 1

2 Registers D O A Storage Register n n A collection of FFs designed See also Lam Fig to work as a unit (in parallel). CLR 5.24 (on next Commercially available models several pages), , , Mano Fig 5.1 A register is a device that conceptually performs the functions: LOAD, READ, DO NOTHING, DISABLE n We can think of them as a bank of n D-FFs. D Q n LOAD Q Do not use this!!! A gated-clock n n n READ 3 Lam Fig bit Storage Register with Master Reset (74 273) 4 2

3 8-bit Storage Register / Tri-State Buffer (74 373) OE LE D i Q + i L 0 - Q i L L H - - Z 5 8-bit Storage Register / Tri-State Buffer (74 573) OE LE D i Q + i L 0 - Q i L L H - - Z 6 3

4 Octal 3-State Noninverting Flip-Flop with Output Enable (74 574) 7 Lam Fig bit Storage Register with Enable (74 378) 8 4

5 Lam Fig bit Storage Register Using a Counter (74 163) 9 Arithmetic-Logic Units (ALU s) ALU s are at the heart of CPU s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See Lam Fig 6.1 (on next page), Mano Section 7.7 [Example] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals: M = H, S 0 = L, S 1 = L, S 2 = L, and S 3 = L. (c) Wait an appropriate delay and connect the output of the ALU (F 3 -F 0 ) to the input of the A register to reload the A register. 10 5

6 Lam Fig 6.1 ALU (74 181) Active-High View 11 Lam Fig 6.1 ALU (74 181) Active-Low View 12 6

7 Arithmetic-Logic Units (ALU s) ALU s are at the heart of CPU s - They are the combinational circuit elements that perform common functions: A set of logical functions & a set of arithmetic functions. See Lam Fig 6.1 (on previous page), Mano Section 7.7 [Example] Let a computer instruction to complement the A register be COMA. The instruction COMA must do the following 3 things: (a) Connect the output of the A register to the A input of the ALU. (b) Present the ALU with control signals: M = H, S 0 = L, S 1 = L, S 2 = L, and S 3 = L. (c) Wait an appropriate delay and connect the output of the ALU (F 3 -F 0 ) to the input of the A register to reload the A register. 13 Register Application Application: inside computers (CPU s), the ALU (Arithmetic Logic Unit) performs, say, 4-bit addition. Command Bits S 0 S 1 S 2 e.g., To ADD, say Set S 0 S 1 S 2 to R1 R2 4 4 Result Reg. 4 BIT ALU C0 4 1 bit register Carry FF C out BUS 14 7

8 Shift Registers MSB LSB 3 0? 1? 2 There are two types & two directions of shift : > logical vs. arithmetic > left vs. right LEFT SHIFT? 2? 1 RIGHT SHIFT Shift Right Shift Left? 1? 2 Logical:?1 = lost,?2 = 0?1 = 0,?2 = lost Arithmetic:?1 = carry,?2 = 0?1 = MSB,?2 = lost or placed in a FF 15 More Shift Registers? 1 LEFT SHIFT If we let?2 =?1 on a Left Shift or?1 =?2 on a Right Shift, we get a Circular Shift or a Rotate Shift. Some computers (CPU s) use the Carry FF as an agent in their SHIFT operations. Especially in those that have Rotates, a copy of the last bit that participated in the shift is copied into the Carry 1-bit Register (i.e., the Carry FF). Conceptually, Shift Registers perform: Serial Loads, Parallel Loads, Shift Lefts, Shift Rights, Parallel Reads, Serial Reads, Clears, etc. Show Lam Fig , Mano Fig (on next pages)? 2? 1 RIGHT SHIFT?

9 Serial-to-Parallel: Realization of 4-bit Shift Register with D-FF s Lam Fig N-bit Storage Register Make an N-bit storage register using N D-FFs & N 2-input MUXs > Load determines if loading occurs on next clock edge > For each of the i-bits, use one of the below S(L) D i (H) Q i (H) 0 1 Load(H) D S Q R R(L) Q i (H) S(L) D i (H) D Load(H) S Q LD Q i (H) R R(L) Functional Block Diagram 18 9

10 Serial-to-Parallel & Parallel-to- Serial: Bi-directional Universal Shift Register (74 194) Lam Fig 5.27 (Can simulate this with Quartus) 19 Shifting with MUXs Make an N-bit shift register using N D-FFs & N 2-input MUXs > Shift determines if shifting occurs on next clock edge > Example: Shift left (ShL) Shift lefts elements are identical (except for bit 0), i=1,, n-1 Q i 0 D i D i D Q Q i 1 Q i-1 ShL Bit 0 is slightly different Q 0 0 Gnd 1 ShL D 0 R CLR D 0 D Q Q 0 R CLR 20 10

11 D i Async MR Q i t a t b t c t apd t bpd D i Async MR Q i t a t b t c Sync vs Async: Async Reset t a initiate sync load of D i t apd complete load of D i after t PD t b initiate async reset of Q i t bpd complete async reset of D i after t PD t c NO sync load of D i MR t a initiate sync load of D i t apd complete load of D i after t PD t b initiate async reset of Q i t bpd complete async reset of D i after t PD t c initiate sync load of D i t cpd complete load of D i after t PD D Q t apd t bpd t cpd 21 D i Sync MR Q i D i Sync MR Q i t a t b t apd t bpd t a t b t apd t x t c t cpd t c t cpd Sync vs Async: Sync Reset t a initiate sync load of D i t apd complete load of D i after t PD t b sync reset is applied (but ignored) t c initiate sync reset t cpd complete sync reset after t PD D Q MR t a initiate sync load of D i t apd complete load of D i after t PD t b sync reset is applied (but ignored) t x sync reset is removed (no effect) t c initiate sync load of D i t cpd complete load of D i after t PD 22 11

12 The End! 23 12

Design of Sequential Circuits

Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable