CprE 281: Digital Logic
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1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Digital System Datapath circuit To store data To manipulate data To transfer data from one part of the system to another Comprise building blocks such as registers, shift registers, counters, multipliers, decoders, encoders, adders, etc. Control circuit Controls the operation of the datapath circuit Designed as a FSM
4 A Simple Processor [ Figure 7.9 from the textbook ]
5 What are the components? [ Figure 7.9 from the textbook ]
6 Registers [ Figure 7.9 from the textbook ]
7 Data Bus [ Figure 7.9 from the textbook ]
8 Tri-State Drivers [ Figure 7.9 from the textbook ]
9 Arithmetic Logic Unit (ALU) [ Figure 7.9 from the textbook ]
10 Control Circuit [ Figure 7.9 from the textbook ]
11 A Closer Look at the Registers
12 Register R0 [ Figure 7.9 from the textbook ]
13 All Registers [ Figure 7.9 from the textbook ]
14 Registers R0, R, R2 and R3 are accessible to the programmer [ Figure 7.9 from the textbook ]
15 Registers A and G are NOT accessible to the programmer [ Figure 7.9 from the textbook ]
16 4-Bit Register
17 Loading Data into the Register 0 0
18 Loading Data into the Register 0 0
19 Loading Data into the Register 0 0
20 Loading Data into the Register
21 Keeping Data into the Register 0 0
22 Keeping Data into the Register 0 0 0
23 Keeping Data into the Register 0 0 0
24 A Closer Look at the Data Bus
25 Data Bus [ Figure 7.9 from the textbook ]
26 Bus Structure We need a way to transfer data from any register (device) to any other register (device) A bus is simply a set of n wires to transfer n-bit data n Bus What if two registers write to the bus at the same time?
27 One way to implement a data bus is to use multiplexers [ Figure 7.4 from the textbook ]
28 One way to implement a data bus is to use multiplexers (four 5-to- multiplexers) This requires one multiplexer per bit. Assuming there are four 4-bit registers, we need four 5-to- multiplexers. [ Figure 7.4 from the textbook ]
29 One way to implement a data bus is to use multiplexers The reason we need 5-to- is because the external data counts as an "extra register". (four 5-to- multiplexers) [ Figure 7.4 from the textbook ]
30 A Closer Look at the Tri-State Driver
31 Tri-State Driver [ Figure 7.9 from the textbook ]
32 All Tri-State Drivers [ Figure 7.9 from the textbook ]
33 Tri-state driver (see Appendix B for more details) Z: High impedance state [ Figure 7. from the textbook ]
34 Tri-state driver (see Appendix B for more details) Alternative way to implement a data bus Allows several devices to be connected to a single wire (this is not possible with regular logic gates because their outputs are always active; an OR gate is needed) Note that at any time, at most one of e0, e, e2, and e3 can be set to device3 device2 device device0 e3 e2 e e0
35 An n-bit Tri-State Driver can be constructed using n -bit tri-state buffers Input e e e e e Output
36 2-Bit Register IN OUT IN 0 OUT R in Clock
37 How to connect two 2-bit registers to a bus (using tri-state drivers) This shows only two 2-bit registers, but this design scales to more and larger registers. [ Figure 7.3 from the textbook ]
38 Moving the Contents of R to R2 0 0 Register stores the number 2 0 = 0 2 Register 2 stores the number 0 = 0 2
39 Moving the Contents of R to R Initially all control inputs are set to 0 (no reading or writing allowed).
40 Moving the Contents of R to R R out is set to (this enables reading from register ).
41 Moving the Contents of R to R The bits of R are now on the data bus (2-bit data bus in this case).
42 Moving the Contents of R to R R2 in is set to (this enables writing to register 2).
43 Moving the Contents of R to R The bits of R are still on the bus and they propagate to the multiplexers...
44 Moving the Contents of R to R and on the next positive clock edge to the outputs of the flip-flops of R2.
45 Moving the Contents of R to R After the copy is complete R out and R2 in are set to 0.
46 Moving the Contents of R to R All control inputs are now disabled (no reading or writing is allowed).
47 Moving the Contents of R to R Register 2 now holds the same value as register.
48 Another Example
49 Loading Data From The Bus Into R Initially all control inputs are set to 0 (no reading or writing allowed).
50 Loading Data From The Bus Into R The number 3 0 = 2 is placed on the 2-bit data bus.
51 Loading Data From The Bus Into R R2 in is set to (this enables writing to register 2).
52 Loading Data From The Bus Into R The bits of the data propagate the the multiplexers...
53 Loading Data From The Bus Into R and on the next positive clock edge to the outputs of the flip-flops of R2.
54 Loading Data From The Bus Into R After the loading is complete R2 in is set to 0.
55 Loading Data From The Bus Into R Register 2 now stores the number 3 0 = 2.
56 A Closer Look at the Arithmetic Logic Unit (ALU)
57 Arithmetic Logic Unit (ALU) [ Figure 7.9 from the textbook ]
58 Two Registers [ Figure 7.9 from the textbook ]
59 4-Bit Register
60 Adder/Subtractor [ Figure 7.9 from the textbook ]
61 Adder/Subtractor unit y n y y 0 Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
62 The first two stages of a carry-lookahead adder x y x 0 y 0 x 0 y 0 g p g 0 p 0 c 0 c 2 c s s 0 [ Figure 3.5 from the textbook ]
63 A hierarchical carry-lookahead adder x 3 24 y 3 24 x 5 8 y 5 8 x 7 0 y 7 0 Block 3 c 24 Block Block 0 c 0 G 3 P 3 G P G 0 P 0 s 3 24 s 5 8 s 7 0 c 32 c 6 c 8 Second-level lookahead [ Figure 3.7 from the textbook ]
64 Adder/subtractor unit Subtraction can be performed by simply adding the 2 s complement of the second number, regardless of the signs of the two numbers. Thus, the same adder circuit can be used to perform both addition and subtraction!!!
65 Adder/subtractor unit y n y y 0 Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
66 XOR Tricks control out y
67 XOR as a repeater 0 y y
68 XOR as an inverter y y
69 Addition: when control = 0 y n y y 0 Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
70 Addition: when control = 0 y n 0 y 0 y Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
71 Addition: when control = 0 y n 0 y 0 y Add Sub control x n x x 0 c n n -bit adder y n- y y 0 c 0 s n s s 0 [ Figure 3.2 from the textbook ]
72 Subtraction: when control = y n y y 0 Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
73 Subtraction: when control = y n y y 0 Add Sub control x n x x 0 c n n -bit adder c 0 s n s s 0 [ Figure 3.2 from the textbook ]
74 Subtraction: when control = y n y y 0 Add Sub control x n x x 0 c n n -bit adder y n- y y 0 c 0 s n s s 0 [ Figure 3.2 from the textbook ]
75 Subtraction: when control = y n y y 0 Add Sub control x n x x 0 c n n -bit adder y n- y y 0 c 0 s n s s 0 carry for the first column! [ Figure 3.2 from the textbook ]
76 A Closer Look at the Control Circuit
77 Control Circuit [ Figure 7.9 from the textbook ]
78 Control Signals Clear FR in [ Figure 7.9 from the textbook ]
79 Design a FSM with input w and outputs R0 in R0 out R in R out R2 in R2 out A in Gin G out Clear AddSub Extern Done R3 in R3 out FR in
80 Design a FSM with input w and outputs R0 in R0 out R in R out A in Gin G out AddSub Extern Done T 0 T T 2 T 3 X 0 X X 2 X 3 R2 in R2 out Clear I 0 I Y 0 Y I 2 Y 2 R3 in FR in I 3 Y 3 R3 out These are helper outputs that are one-hot encoded. They are used to simplify the expressions for the other outputs.
81 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry 0 Function [ Figure 7. from the textbook ]
82 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En All three decoders are always enabled Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry 0 Function [ Figure 7. from the textbook ]
83 Operations performed by this processor Operation Load Rx, Data Function Performed Rx ç Data Move Rx, Ry Rx ç [Ry] Add Rx, Ry Rx ç [Rx] + [Ry] Sub Rx, Ry Rx ç [Rx] - [Ry] [ Table 7. from the textbook ]
84 Operations performed by this processor Operation Load Rx, Data Function Performed Rx ç Data Move Rx, Ry Rx ç [Ry] Add Rx, Ry Rx ç [Rx] + [Ry] Sub Rx, Ry Rx ç [Rx] - [Ry] Where Rx and Ry can be one of four possible options: R0, R, R2, and R3 [ Table 7. from the textbook ]
85 Operations performed by this processor f f 0 Function 0 0 Load 0 Move 0 Add Sub Rx Rx 0 Register 0 0 R0 0 R 0 R2 R3 Ry Ry 0 Register 0 0 R0 0 R 0 R2 R3
86 Operations performed by this processor è Move R3, R0 f f 0 Function 0 0 Load 0 Move 0 Add Sub Rx Rx 0 Register 0 0 R0 0 R 0 R2 R3 Ry Ry 0 Register 0 0 R0 0 R 0 R2 R3
87 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry è Move R3, R0
88 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry è Move R3, R0
89 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry è Move R3, R0
90 The function register and decoders I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry è Move R3, R0
91 The function register and decoders one-hot encoded one-hot encoded one-hot encoded I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry è Move R3, R0
92 Operations performed by this processor 0 0 è Add R, R3 f f 0 Function 0 0 Load 0 Move 0 Add Sub Rx Rx 0 Register 0 0 R0 0 R 0 R2 R3 Ry Ry 0 Register 0 0 R0 0 R 0 R2 R3
93 Operations performed by this processor è Sub R0, R2 f f 0 Function 0 0 Load 0 Move 0 Add Sub Rx Rx 0 Register 0 0 R0 0 R 0 R2 R3 Ry Ry 0 Register 0 0 R0 0 R 0 R2 R3
94 Operations performed by this processor x x è Load R2, Data f f 0 Function 0 0 Load 0 Move 0 Add Sub Rx Rx 0 Register 0 0 R0 0 R 0 R2 R3 Ry Ry 0 Register 0 0 R0 0 R 0 R2 R3
95 Similar Encoding is Used by Modern Chips [
96 Sample Assembly Language Program For This Processor Move R3, R0 Add R, R3 Sub R0, R2 Load R2, Data
97 Machine Language vs Assembly Language Machine Language Assembly Language Meaning / Interpretation Move R3, R0 Add R, R3 Sub R0, R2 Load R2, Data R3 ç [R0] R ç [R] + [R3] R0 ç [R0] [R2] R2 ç Data
98 Machine Language vs Assembly Language Machine Language Assembly Language Meaning / Interpretation Move Add Sub Load R3, R0 R, R3 R0, R2 R2, Data R3 ç [R0] R ç [R] + [R3] R0 ç [R0] [R2] R2 ç Data
99 Machine Language vs Assembly Language Machine Language Assembly Language Meaning / Interpretation Move R3, R0 Add R, R3 Sub R0, R2 Load R2, Data R3 ç [R0] R ç [R] + [R3] R0 ç [R0] [R2] R2 ç Data For short, each line can be expressed as a hexadecimal number
100 Machine Language vs Assembly Language Machine Language Assembly Language Meaning / Interpretation C Move R3, R0 Add R, R3 Sub R0, R2 Load R2, Data R3 ç [R0] R ç [R] + [R3] R0 ç [R0] [R2] R2 ç Data
101 Intel 8086 [
102 Intel 8086 Memory Address [
103 Intel 8086 Machine Language [
104 Intel 8086 Assembly Language [
105 Intel 8086 Comments [
106 Another Part of The Control Circuit
107 A part of the control circuit for the processor T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter [ Figure 7.0 from the textbook ]
108 What are the components? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter [ Figure 7.0 from the textbook ]
109 2-Bit Up-Counter T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter [ Figure 7.0 from the textbook ]
110 2-bit Synchronous Up-Counter T Q T Q Clock Q Q Clear_n
111 2-bit Synchronous Up-Counter with Enable Enable T Q T Q Clock Q Q Clear_n
112 2-to-4 Decoder with Enable Input T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter [ Figure 7.0 from the textbook ]
113 2-to-4 Decoder with an Enable Input En [ Figure 4.3c from the textbook ]
114 2-to-4 Decoder with an Enable Input (always enabled in this example) [ Figure 4.3c from the textbook ]
115 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter
116 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 0 Clock Clear 0 Reset Q Q 0 Up-counter
117 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 0 Clock Clear 0 Reset Q Q 0 Up-counter
118 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 Clock Clear 0 Reset Q Q 0 Up-counter
119 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 Clock Clear 0 Reset Q Q 0 Up-counter
120 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear 0 Reset Q Q 0 Up-counter
121 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 0 Clock Clear 0 Reset Q Q 0 Up-counter
122 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 Clock Clear 0 Reset Q Q 0 Up-counter
123 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 Clock Clear Reset Q Q 0 Up-counter
124 So How Does This Work? T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 0 0 Clock Clear Reset Q Q 0 Up-counter
125 Meaning/Explanation This is like a FSM that cycles through its four states one after another. But it also can be reset to go to state 0 at any time. The implementation uses a counter followed by a decoder. The outputs of the decoder are one-hotencoded. This is like choosing a state assignment for an FSM in which there is one Flip-Flop per state, i.e., one-hot encoding (see Section 6.2. in the textbook)
126 Deriving the Control Signals
127 Design a FSM with input w and outputs R0 in A in AddSub T 0 X 0 R0 out R in R out Gin G out Extern Done T T 2 T 3 X X 2 X 3 R2 in R2 out Clear I 0 I Y 0 Y I 2 Y 2 R3 in R3 out FR in I 3 Y 3 These are helper outputs that are one-hot encoded. They are used to simplify the expressions for the other outputs.
128 Control Signals [ Figure 7.9 from the textbook ]
129 Control Signals [ Figure 7.9 from the textbook ]
130 Another Control Signal I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En 2-to-4 decoder w w 0 En Clock FR in Function Register f f 0 Rx Rx 0 Ry Ry 0 [ Figure 7. from the textbook ]
131 Yet Another Control Signal T 0 T T 2 T 3 y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock Clear Reset Q Q 0 Up-counter [ Figure 7.0 from the textbook ]
132 Expressing the 'FR in ' signal I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 T 0 T T 2 T 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w 0 En y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock FR in Function Register Clock Clear Reset Q Q 0 Up-counter f f 0 Rx Rx 0 Ry Ry 0 FR in = w T 0 Load a new operation into the function register
133 Expressing the 'Clear' signal I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 T 0 T T 2 T 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w 0 En y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock FR in Function Register Clock Clear Reset Q Q 0 Up-counter f f 0 Rx Rx 0 Ry Ry 0 Clear = w T 0 + Done Reset the counter when Done or when w=0 and no operation is being executed (i.e., T 0 =).
134 Control signals asserted in each time step T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done [ Table 7.2 from the textbook ]
135 Control signals asserted in each time step T T 2 T 3 Time (Load): I 0 (Move): I (Add): I 2 (Sub): I 3 Extern R in = X Done R in = X R out = Y Done R out = X A in R out = X A in R out = Y G in AddSub = 0 R out = Y G in AddSub = These are the outputs of the first 2-to-4 decoder that is connected to the two most significant bits of the function register. They are one-hot encoded so only one of them is active at any given time (see Fig 7.). G out R in = X Done G out R in = X Done These come from the outputs of the 2-to-4 decoder in Figure 7.0. They are also one-hot encoded. [ Table 7.2 from the textbook ]
136 The I 0, I,I 2, I 3 and T 0,T,T 2,T 3 Signals I 0 I I 2 I 3 X 0 X X 2 X 3 Y 0 Y Y 2 Y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 y 0 y y 2 y 3 T 0 T T 2 T 3 2-to-4 decoder 2-to-4 decoder 2-to-4 decoder w w 0 En w w 0 En w w 0 En y 0 y y 2 y 3 2-to-4 decoder w w 0 En Clock FR in Function Register Clock Clear Reset Q Q 0 Up-counter f f 0 Rx Rx 0 Ry Ry 0 [ Figure 7. from the textbook ] [ Figure 7.0 from the textbook ]
137 Different Operations Take Different Amount of Time T T 2 T 3 (Load): I 0 Extern R in = X Done clock cycle (Move): I R in = X R out = Y Done clock cycle (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done 3 clock cycles (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done 3 clock cycles [ Table 7.2 from the textbook ]
138 Operations performed by this processor Operation Load Rx, Data Function Performed Rx ç Data Move Rx, Ry Rx ç [Ry] Add Rx, Ry Rx ç [Rx] + [Ry] Sub Rx, Ry Rx ç [Rx] - [Ry] Where Rx and Ry can be one of four possible options: R0, R, R2, and R3 [ Table 7. from the textbook ]
139 Simple Processor [ Figure 7.9 from the textbook ]
140 Expressing the 'Extern' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done Extern = I 0 T
141 Expressing the 'Done' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done Done = (I 0 + I )T + (I 2 + I 3 )T 3
142 Expressing the 'A in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done A in = (I 2 + I 3 )T
143 Expressing the 'G in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done G in = (I 2 + I 3 )T 2
144 Expressing the 'G out ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done G out = (I 2 + I 3 )T 3
145 Expressing the 'AddSub' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done AddSub = I 3
146 Expressing the 'R0 in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R0 in = (I 0 + I )T X 0 + (I 2 + I 3 )T 3 X 0
147 Expressing the 'R in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R in = (I 0 + I )T X + (I 2 + I 3 )T 3 X
148 Expressing the 'R2 in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R2 in = (I 0 + I )T X 2 + (I 2 + I 3 )T 3 X 2
149 Expressing the 'R3 in ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R3 in = (I 0 + I )T X 3 + (I 2 + I 3 )T 3 X 3
150 Expressing the 'R0 out ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R0 out = I T Y 0 + (I 2 + I 3 ) ( T X 0 + T 2 Y 0 )
151 Expressing the 'R out ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R out = I T Y + (I 2 + I 3 ) ( T X + T 2 Y )
152 Expressing the 'R2 out ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R2 out = I T Y 2 + (I 2 + I 3 ) ( T X 2 + T 2 Y 2 )
153 Expressing the 'R3 out ' signal T T 2 T 3 (Load): I 0 Extern R in = X Done (Move): I R in = X R out = Y Done (Add): I 2 R out = X A in R out = Y G in AddSub = 0 G out R in = X Done (Sub): I 3 R out = X A in R out = Y G in AddSub = G out R in = X Done R3 out = I T Y 3 + (I 2 + I 3 ) ( T X 3 + T 2 Y 3 )
154 Derivation of the Control Inputs For more insights into these derivations see pages 434 and 435 in the textbook
155 Some Additional Topics
156 The ALU for the Simple Processor For this ALU, A+B if AddSub= A-B if AddSub=0 [ Figure 7.9 from the textbook ]
157 Another Arithmetic Logic Unit (ALU) Arithmetic Logic Unit (ALU) computes arithmetic or logic functions Example: A four-function ALU has two selection bits S S0 (also called OpCode) to specify the function 00 (ADD), 0 (SUB), 0 (AND), (OR) Then the following set up will work A B A B A B A B ADD SUB AND OR 00 0 MUX 0 S S0 Result A B S S0 Function 0 0 ADD 0 SUB 0 AND OR A L U Result Symbol S S0 (OpCode)
158 An Alternative Design of Four-Function ALU The previous design is not very efficient as it uses an adder and a subtractor circuit We can design an add/subtract unit as discussed earlier Then we can design a logical unit (AND and OR) separately Then select appropriate output as result What are the control signals, Add/Sub, Select0, and Select? A B A B A B Add/Sub ADD/SUB 0 MUX AND 0 MUX OR Select0 Select Result S S0 Function 0 0 ADD 0 SUB 0 AND OR
159 Examples of Some Famous Microprocessors
160 Intel's 4004 Chip [
161 Technical specifications Maximum clock speed was 740 khz Instruction cycle time: 0.8 µs (8 clock cycles / instruction cycle) Instruction execution time or 2 instruction cycles (0.8 or 2.6 µs), to instructions per second Built using 2,300 transistors [
162 Technical specifications Separate program and data storage. The 4004, with its need to keep pin count down, used a single multiplexed 4-bit bus for transferring: 2-bit addresses 8-bit instructions 4-bit data words Instruction set contained 46 instructions (of which 4 were 8 bits wide and 5 were 6 bits wide) Register set contained 6 registers of 4 bits each Internal subroutine stack, 3 levels deep. [
163 [
164 [
165 Intel's 8086 Chip [
166 [
167 [ Simplified block diagram of Intel 8088 (a variant of 8086); =main registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 0//2=external address/ data/control bus.
168 Questions?
169 THE END
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