Switching Circuits & Logic Design

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1 Switching ircuits & Logic esign Jieong Roland Jiang 江介宏 epartment of lectrical ngineering National Taiwan University Fall 22 6 Sequential ircuit esign homsky ierarchy 2

2 Outline Summary of design procedure for sequential circuits esign eample code converter esign of iterative circuits esign of sequential circuits using ROs and PLs 3 Summary of esign Procedure for Sequential ircuits. erive state table (and/or state graph) Given the problem statement, determine the required relationship between the input and output sequences and derive a state table For many problems, it is easiest to first construct a state graph 2. Reduce state table minimization by row matching or using an implication table 3. Perform state assignment log 2 m flipflops are needed to encode m states 4. Form transition table Substitute the assigned flipflop states for each state in the reduced state table 5. erive flipflop input equations and output functions Plot netstate maps and input maps for each flipflop to derive the flipflop input equations 6. Realize flipflop input equations and output functions using available logic gates 7. heck design Use signal tracing, computer simulation, or lab testing 4

3 esign ample ode onverter onvert to ecess3 code dd 3 to a binarycodeddecimal digit in the range to 9 ssume serial input and output with the least significant bit first Reset to initial state after receiving every 4 inputs () ode onverter (ecess3) an the converter be realized without delaying the output? t t = () () (2) (3) = () () (2) (3) Input () t t other codes Output (ecess3) t 5 t esign ample ode onverter Step : derive state table and state graph Time t t Input Sequence Received (LS first) reset F G I J K L N P Net = I J K F G L N P Output () = t / t / / / F / / / G / / / / / / / L J N I K P / / / / // / / / / 6

4 esign ample ode onverter Time t t Step 2: Reduce state table Input Sequence Received (LS first) reset F G I J K L N P Net = I J K F G L N P Output () = t Net The matching assumes, under =, the net state is and = The matching imposes no particular condition on these don t cares Output () Time = = t 7 esign ample ode onverter In reducing a state table by row matching, sometimes there can be multiple incompatible choices in matching a row ample R S Net = S S Output () = R can be matched with either or S, but not both 8

5 esign ample ode onverter Step 3: Perform state assignment Need 3 flipflops for 7 states Reduced state table Net Output () Time = = t t ssignment map n even better assignment? 9 esign ample ode onverter Step 4: Form transition table Transition table = = = = t Net Output () Time = = t

6 esign ample ode onverter Step 5: erive flipflop input equations and output functions 2 3 = = 2 = = 3 = = = esign ample ode onverter Step 6: Realize circuit Flipflop input functions I G G2 2 FF FF Output function 5 G5 G3 3 G4 3 LK FF G6 6 G7 2

7 esign of Iterative ircuits any of the design procedures used for sequential circuits can be applied to the design of iterative circuits.g., the design procedure used for the (sequential) serial adder of Uni can be applied to the design of the parallel adder of Unit 4 Unilateral iterative circuit is the simplest form of an iterative circuit linear array of combinational cells with signals between cells traveling in only one direction 2 3 i n ell a ell a ell a a ell a a a ell a i i n n 2 3 i n 2 3 i n i and i are the primary input and output, respectively, of cell i a i and a i resemble the present state and net state, respectively, of cell i 3 esign of Iterative ircuits esign of a omparator ompare two nbit binary numbers = 2 n and Y = y y 2 y n and determine if they are equal or which one is larger if they are not equal ssume and y are the most significant bits (we plan to do the comparison from left to right) y 2 y 2 i y i n y n a a 2 a 3 a i a i a n a n b ell ell ell ell b b 2 b 2 3 i b i i b n b n n Output Network (<Y) 2(=Y) 3(>Y) 4

8 esign of Iterative ircuits esign of a omparator Steps,2: derive and reduce state table S i =Y >Y <Y S i S S S 2 i y i = S S S 2 S 2 S S 2 S S S 2 S S S :<Y 2 :=Y 3 :>Y Steps 3,4: Perform state assignment and form transition table a i b i a b i i y i = state assignment i 2 3 S = S = S 2 = 5 esign of Iterative ircuits esign of a omparator Steps 5,6: derive and realize cell input and output functions Typical cell for comparator y i i i y i a i b i i y i a i b i a i a i a i b i a i =a i i y i b i b i =b i i y i a i Output circuit for comparator b i b i a n b n a n b n a n b n a n (<Y) 2 (=Y) =an b n 3 (>Y) 2 =a n b n 3 =b n 6

9 esign of Iterative ircuits esign of a omparator Sequential comparator i y i a i a i a a i (<Y) Typical ell lock K 2 (=Y) b i b i b b i 3 (>Y) lock K t t n time = 2 n Y = y y 2 y n 7 esign of Sequential ircuits Using ROs and PLs For a ealy sequential circuit, the combinational part can be realized using a RO (PL) For the circuit with m inputs, n outputs, and k state variables, we need k flipflops and a RO with mk inputs (2 mk words) and nk outputs Similarly, for a oore sequential circuit, the netstate and output combinational subcircuits can be realized using two ROs (PLs) or, alternatively, a single RO (PL) 8

10 esign of Sequential ircuits Using ROs ample Realize the prior to ecess3 code converter using a RO and FFs table Transition table state Net = Output () = = = = = 9 esign of Sequential ircuits Using ROs ample (cont d) Realize the prior to ecess3 code converter using a RO and FFs Truth table input lines RO 6 Words 4 its output lines 2

11 esign of Sequential ircuits Using ROs ample (cont d) Realize the prior to ecess3 code converter using a RO and FFs RO 6 Words 4 its 2 3 K 2 K 3 lock K 2 esign of Sequential ircuits Using PLs ample Realize the prior to ecess3 code converter using a PL and FFs ssignment map Transition table = = = = 22

12 esign of Sequential ircuits Using PLs ample (cont d) Realize the prior to ecess3 code converter using a PL and FFs = = 2 = = 3 = = = 23 esign of Sequential ircuits Using PLs ample (cont d) Realize the prior to ecess3 code converter using a PL and FFs PL table 2 3 = = 2 = = 3 = = = N plane OR plane 24

13 esign of Sequential ircuits Using PLs ample segment of a sequential PL realizing the netstate equation = = lock n Inverting Tri Output uffer Programmable N rray 25

UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY

UNIT III Design of Combinational Logic Circuits. Department of Computer Science SRM UNIVERSITY UNIT III Design of ombinational Logic ircuits Department of omputer Science SRM UNIVERSITY Introduction to ombinational ircuits Logic circuits for digital systems may be ombinational Sequential combinational