Simplification of State Machines

Transcription

1 T3 Lecture Notes State Reduction hapter 9 - of Simplification of State Machines This semester has been spent developing the techniques needed to design digital circuits. Now we can compile a list of just what it takes to complete a successful digital design project. Specif the problem erive the state table and/or the state diagram Reduce the # of states to the minimum possible hoose an appropriate state assignment onstruct an appropriate transition table evelop the design equations Implement the circuit

2 T3 Lecture Notes State Reduction hapter 9 - of The onl topic in that list that is left to be discussed is that of minimiing the number of states. iscussion of State Reduction is normall divided into two different areas:. State Reduction in ompletel Specified ircuits. State Reduction in Incompletel Specified ircuits We will limit our discussion to the first area. This topic is epanded on in T 4 and usuall encompasses the second discussion area. The removal of redundant states is important for a number of reasons. () ost: The number of memor elements is directl related to the number of states. () ompleit: The more states the circuit contains, the more comple the design and its associated implementation becomes. (3) ids failure analsis: iagnostic routines are usuall based on the assumption that there are no redundant states. There are 3 major State reduction Methods: Reduction b (a) Inspection (b) Partitioning (c) Implication table. We will stud the st two methods and leave the Implication table method for T 4.

3 T3 Lecture Notes State Reduction hapter 9-3 of Reduction Inspection This is the easiest and most obvious technique. We can merge compatible states if we follow some simple rules.. Two states that have different outputs are not compatible and can t be merged.. Two states are compatible and can be merged if, under all possible input conditions, the net states and outputs are the same. 3. Two states are compatible and can be merged if, under all possible input conditions, the merging of the two states will make the net states compatible and the outputs the same.

4 T3 Lecture Notes State Reduction hapter 9-4 of The following is an eample from Professor Hackworth s T4 tet. (rule ) = = andidates for merging (rule ) Not a candidate (rule ) (rule ) = = Note the substitution of all s with s along with the merger. = = This application of rule 3 is quite often hard to notice. That s wh we need other methods of state reduction. (rule 3) if were merged with then we could replace with and then the Net states and the outputs would match. = = Note that with this final circuit we have made quite a hardware savings. We went from 5 states (3 ff) to states ( ff) along with a significant reduction in control circuitr.

5 T3 Lecture Notes State Reduction hapter 9-5 of Let s look at another small eample. In doing so, we will also look at a couple of new was to write state tables which will help us in our reductions. Y Z 7 7» Two groups of possible candidates for merging. 7»» If we merge and, would the results be the same? 7» = therefore the two states are not compatible. = therefore the two states are not compatible. 's outputs ( ) are different 's outputs ( ) are different

6 T3 Lecture Notes State Reduction hapter 9-6 of Let s do the same thing ecept this time, let s put the table into another form. = Y/ = Y/ = Y/ = Y/ / / / / - / / / / / / / / / / Note that since was redundant, we replaced ever with a. What did we save with this State Merger? Saved on gates, not on s. Let s rewrite the table another wa ON MOR TIM. Y = = = = = = = = -

7 T3 Lecture Notes State Reduction hapter 9-7 of Let s tr a second eample. We will use the Inspection method to reduce the following state table: Let s look at the instances where Z is equal to : Y Y = = = = State had a NT STT of and. ollowing the thread we get: State has NT STTS of and. definition, will be fine, but is not compatible because has an output of and has an output of. If one item in an thread of a state inspection is incompatible, the whole thread (and the state) is bad (fruit of the poison tree) as well!! We don t even have to look at the other thread coming off of but if ou like, note that the thread starts with which we have alread determined to be incompatible. is the other possibilit for Z =. Note that if we work thru the top thread, we get to which we have shown to be incompatible, therefore the entire tree is poisoned. ontinued on the net page:

8 T3 Lecture Notes State Reduction hapter 9-8 of ontinuing the eample, let s now look at the output condition of Z = This time, we will use less eplanation for the failures. Tr to follow wh each tree failed: Y Y = = = = Y Z = = = = Y Z = = = = Note that we replaced the single with an and all the occurrences of with. We reduced the circuit from 7 states (3 ) to 5 states (3). We still didn t save on flip-flops but we most likel saved on control circuitr.

9 T3 Lecture Notes State Reduction hapter 9-9 of Moore Reduction (also known as Partitioning) (page 58) = Y = = =. The st step is to assume that all states are compatible. P =(). Then we start grouping the states based on their outputs. P =()()() 3. Then we group these groups b Net State. or, =, The net state is. Note that in P, is in the same group () so can sta in the same group. However, is not in the same group as was so will have to be separated out into its own group. We now have partition (P ): P =()()()() or, =, The net state is which becomes. were in the same group in the last partition, P so the can still share a group in P 3. P 3 =()()()() or, =, Net state is. Obviousl the are in same group in P 3 so can remain grouped. P 4 =()()()() or, =, Net state is which are all in the same group in P 4, so we can keep together. P 5 =()()()()

10 T3 Lecture Notes State Reduction hapter 9 - of Once a partition repeats itself, ou are finished. So, for this group, we get: Reduced from 7 states (3 ff) to 4 states ( ff) + control circuitr. = = = = Y = = = = Y

11 T3 Lecture Notes State Reduction hapter 9 - of Let s redo our eample on page 7 b using Moore reduction. Y = = = =. ssume the all are compatible. P =(). roup b output. P =()() 3. roup b net state. P = ()()()() P 3 = ()()()()() P 4 = ()()()()() P 3 = P 4 thus reduced Y = = = = Y = = = = Same answer as before.

12 T3 Lecture Notes State Reduction hapter 9 - of (ample 9.3 in Nelson, et. al.) Reduce the following stable b appling Moore s Reduction. Y = = = = P =(H) H H P =()()()(H) P =()()()()(H) P 3 =()()()()(H) P 3 = P, Thus reduced Y = = = = Y = = = = H H H H

13 T3 Lecture Notes State Reduction hapter 9-3 of ample 9.4 (in Nelson, et. al.) / / / / / / / / / / / / P =(H) P =()(H) / / / / P =()()(H) / / / / / / / / / / / / P 3 =()()()()(H) P 4 =()()()()(H) H / / / / P 3 =P 4, Thus reduced / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / H / / / /

14 T3 Lecture Notes State Reduction hapter 9-4 of State ssignments State assignment procedures are concerned with methods for assigning binar values to states in such a wa as to reduce the cost of the combinational circuit which drives the flip-flops (memor elements). These methods are mainl useful when a circuit is viewed as a black bo. Such a circuit ma follow a sequence of internal states, but the binar values of the individual states ma be of no consequence outside of the bo as long as the circuit produces the required sequence of output bits for an sequence of input bits. this definition, this assignment procedure obviousl doesn t appl to circuits whose eternal outputs are taken directl from flip-flops with a particular binar sequence specified. There are man methods of optimiing the state assignments made to a given circuit. Most are etremel involved and are beond the scope of this course. However, one particular method of state assignment optimiation is essentiall simple and eas to follow.

15 T3 Lecture Notes State Reduction hapter 9-5 of In the following rules, there term adjacent assignments means that the state assignments made to a pair of states differ b onl bit, i.e. ra odes. Rule : Rule : Rule 3: States that have the same net states for a given input should be given logicall adjacent assignments. States that are the net states of a given present state, under logicall adjacent inputs, should be given logicall adjacent assignments. If there is a conflict between rule and, rule takes precedence. Let s appl these rules to an eample: ssign. # ssign. # ssign. #3 Y = = = = Using Rule #, the state pair (,) should be given adjacent assignments because both of them go to state for =. Similarl, state pairs (,), (,), and (,) all should be given adjacent assignments; the pair (,) appears twice.

16 T3 Lecture Notes State Reduction hapter 9-6 of The application of Rule # shows that the state pair (,) should be given adjacent assignments because the are net states of the present state. or similar reasons, state pairs (,) and (,) Rule : States that are the net states of a given present state, under logicall adjacent inputs, should be given logicall adjacent assignments. Rule : States that have the same net states for a given input should be given logicall adjacent should be adjacent with (,) appearing twice. 3 ssign. # 3 ssign. # 3 ssign. #3 The figure above demonstrates the three different choices for state assignments which attempt to meet as man of the adjacenc requirements as possible. It can hopefull be seen that ssignment 3 satisfies most of the adjacencies and hence produces a better result then the other assignments. It might be suggested that ssignment

17 T3 Lecture Notes State Reduction hapter 9-7 of produces the same number of adjacencies as #3, but it doesn t fulfill the adjacenc requirement for state pair (,) as determined b Rule. (Note that we don t bother here with an equation for since it is not affected b a state assignment.) Let s take a look at the logic equations produced b each assignment. The actual work to produce these equations follows but will not be covered in class. It is left up to the student to verif the equations for him or herself. s can be easil seen below, our choice of ssign. #3 is clearl the winner in the logic component simplicit contest. J K J K # gates N gate OR gate + wire and a choice between: # or + OR gate or OR gate additional N gates OR gate wire + and a choice between: # or + OR gate or additional OR gate additional N gates N gate # 3 3 wires

18 T3 Lecture Notes State Reduction hapter 9-8 of State ssignment # Y Y J J K K ssign # PS NS J K 3 J J J = + J = + = K K K = K = + =

19 T3 Lecture Notes State Reduction hapter 9-9 of State ssignment # Y Y J K J K ssign # PS NS J K 3 J J J = + = J = K K = + K K =

20 T3 Lecture Notes State Reduction hapter 9 - of State ssignment #3 Y Y J K J K ssign #3 PS NS J K 3 J J J = J = K K K = K =