Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Midterm Examination CLOSED BOOK

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1 Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall Midterm Examination CLOSED OOK Kewal K. Saluja Date: November 2, 203 Place: Room 2535 Engineering Hall Time: 7:5-8:30 PM Duration: 75 minutes PROLEM TOPIC General Questions 0 2 Test Economics 6 3 Modeling 4 Fault Simulation 4 5 SCOP Computation 0 6 Test Generation - Comb 4 7 Test Generation - Seq 0 8 Checking Sequence 5 TOTL 00 POINTS SCORE Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): SOLUTION First Name: ID Number: Fall 203 (Lec: Saluja)

2 . (0 points) General Questions nswer the following in brief and to the point. You must not use more than two to three lines of explanation where an an explanation is needed. (a) ( point) Memory usage by a concurrent fault simulator is smaller than the memory usage by a deductive fault simulator. nswer False. (b) ( point) Memory usage by a serial fault simulator is smaller that the memory usage by a deductive fault simulator. nswer True (c) (2 point) gate level fanout-free realization of a circuit has 20 inputs and 2 outputs. What is the maximum number of tests we will need to test this circuit. Hint: think checkpoints. In a fanout free circuit there are no branches. Therefore only checkpoints in the circuit are primary inputs. Hence the total number of faults for which we need to find tests is 2x20 = 40. Thus the max number of tests is 40. (d) (2 points) If a fault f dominates fault f 2, and the fault f 2 dominates a fault f 3. which of these faults can be deleted to reduce the fault list for fault detection. Give reason. We delete the fault that dominates. Hence delete faults f and f 2. (e) ( point) Method of oolean Difference can be used to determine if a fault in a combinational circuit is redundant. nswer True (f) ( points) Easy/Hard heuristic can only be used in PODEM during backtrace and it can not be used during D-drive. nswer False. (g) ( points) If SCOP CC0 value of a line in a circuit is 25 then it means that this line can always be set to 0 by assigning appropriate values to the inputs to the circuit. nswer False. (h) ( points) If SCOP CC value of a line in a circuit is inf then it means that this line can never be set to no matter what values are assigned to the inputs to the circuit. nswer True 2 Fall 203 (Lec: Saluja)

3 2. (6 points) Test Economics chip manufacturer is to produce ICs in a very large quantity and it has worked out its cost as follows:. Cost of design (amortized on each IC) = $ Production cost of each IC = $.00. Test cost for each IC = $ 2.00 Test as filter has the following properties based on the quality of test:. 95% of the truly good devices will pass the test.. 96% of the bad devices will fail the test. ased on the technology used, it is known that the true yield of ICs being fabricated is 80%. Now answer the following questions: (a) ( point) What percentage of good devices will fail the test? 5% (b) ( point) What percentage of bad devices will pass the test? 4% (c) (3 point) Determine the Yield of the above devices. You must show your work. 0.95x x0.2 = Which is 76.8% (d) (3 point) Determine the Defect Level (DL) of the above devices. You must show your work and write the value of defect level in parts per million? (0.04x0.2)/0.768 = which is 047 ppm 3 Fall 203 (Lec: Saluja)

4 (e) (3 point) Determine the Yield loss due to above testing. You must show your work. 0.05x0.8 = 0.04 which is 4% Note this is corrct answer - but some students felt that yield loss is a ratio of good devices faild to the good devices or devices tested good - I gave points for that if it was explained by the student. (f) (5 points) ssuming that the manufacturer will have to pay $50.00 for every bad device sold to a customer (because customer will return a bad IC), at what price should an IC be sold so that the manufacture breaks even. Let y be the break even cost. Then: y(0.8x x0.04) - 50x0.2x0.04 = Solving for y we obtain the break even cost to be $ Fall 203 (Lec: Saluja)

5 3. ( points) Modeling-sol library cell of a design library realizes a function f(,,c) =.. C. designer, makes a mistake, while building this cell and makes incorrect connections and realizes the function. C.. nswer the following and you must show your work for full credit. (a) (3 points) Write all primitive cubes of f. ll primitive cubes are (I used the order of variable to be C /outpur, same as in f): xx0/ x/ 0x/0 x0/0 (b) (4 points) Write two propagation D-cubes of f: i. a propagation D cube with at least one of the inputs to be logic : D / D ; nother propagation D cube with this property is D / D Clearly complementing D will also obtain additional valid cubes. ii. a propagation D cube with at least one of the inputs to be logic 0: X 0 D / D; nother propagation D cube with this property is 0 x D / D Clearly complementing D and D will also obtain additional valid cubes. (c) (4 points) Write two primitive cubes of failure for the mistake specified in the problem description. Primitive cubes of the faulty function are x / ; x 0 x / ; 0 x / 0; x 0 / 0; These in conjunction with the primitive cubes of f generate the following primitive cubes of fault: 0 / D; 0 0 / D; 0 0 / D; 0 / D 5 Fall 203 (Lec: Saluja)

6 4. (4 points) Fault Simulation - Deductive The circuit of Fig is to be simulated using the pattern given below: pattern = C D E F = C D E 0 k l p j h o 0 0 m i n s u t F 0 0 r Figure : Circuit for deductive fault simulation - Solution The fault list that needs to be simulated for this pattern is given below: / / C/0 D/0 E/0 F/ h/0 i/0 k/0 n/0 s/0 Note: During fault simulation, list associated with any line or gate must not contain a fault that is not in the above list. (a) (2 points) Indicate the true signal values in every gate of the circuit. For your convenience, I have already provided values in one of the gates. True values are shown in the gates. 6 Fall 203 (Lec: Saluja)

7 (b) (0 points) In the table below, provide the deductive fault lists associated with every line in the circuit. gain to get you started, I have already completed the entries associated with all primary input lines. Line Name fault list Line Name fault list / l C/ - - m D/0; h/0 C C/0 n D/0; h/0; n/0 D D/0 o D/0; h/0 E E/0 p C/0; D/0; k/0 F F/ r D/0; h/0; n/0 h D/0; h/0 s C/0; D/0; h/0; k/0; s/0 i E/0 t C/0; D/0; h/0; k/0;/ n/0; s/0 j D/0 u / k C/0; k/0 (c) (2 points) Now, indicate which of the faults will be detected and at which output. Faults detected at output u: / Faults detected at output t: C/0; D/0; h/0; k/0;/ n/0; s/0 7 Fall 203 (Lec: Saluja)

8 5. (0 points) SCOP Computation Consider the circuits shown in Figure 2 for SCOP computations. This circuit is a part of a larger combinational circuit. (30,5)55 (45,24) 46 (45,24) 85 (45,24) 46 2 C (70,3)96 (40,3)30 G (40,3) 7 G2 D (9,73)29 G2 (38,46)7 (40,3) 30 (05,20)97 G3 Z (67,39) 50 Z2 Figure 2: Combinational Circuit for SCOP Computations - solution In this circuit some of the SCOP values, i.e the CC0, CC and CO values, are already computed and shown in the circuit. The notation used is (CC0,CC) CO. While many other values need to be computed. You are to compute all the remaining values, i.e. CC0, CC and CO values which are not shown in the figure. Enter these values in the table below. I have already entered the values shown in the figure in this table, therefore you need only to complete the blank entries. Line Controllability Observability Line Controllability Observability CC0 CC CO CC0 CC CO G G G Z C G D Z Fall 203 (Lec: Saluja)

9 6. (4 points) Combinational Test Generation PODEM like test generator is used to generate a test of for the line 20 s-a- in the circuit of Figure 3. C D E F Figure 3: Circuit for test generation It is still in the process of test generation and has made the assignments at some of the primary inputs as follows and in the order shown: = C = 0 C = = = 0 (a) (3 points) Construct the decision tree for the completed work this far. 0 --> C --> no test (backtrack) change decision --> --> no test (backtrack) 0 --> we are here 9 Fall 203 (Lec: Saluja)

10 (b) (7 points) In the table below indicate all the implications of the above assignments and the D frontier. I have already filled in a few implications for some signal lines. ssignments Implications D frontier Comments =, C=, =0 Lines 2, 5, 8 are ; Lines, 3, 4, 6 are 0; Line 7, 9, 0 are 0; Line, 2, 3, 4, 5, 9 are ; Lines 20 is 0 hence Lines 2, 22, 23 are D; Line 25 is D; Gates 27, 26 and 28 D = Line 24, 28 are ; Line 26 is D and 27 is ; line 29 is null backtrack (c) (4 points) If the next assignment is D =, will that cause a back track or lead to a next new assignment? Show your work in the table above. D frontier will disappear and it will lead to backtrack. 0 Fall 203 (Lec: Saluja)

11 7. (0 points) Sequential Test Generation Consider the sequential circuit given in Figure 4 containing two D-type flip-flops and a logic gate. FF FF2 D Q D Q Z Q Q Figure 4: Figure for a sequential circuit (a) (2 points) In the Figure 5 I have provided two FFs and a box for the combinational part of the circuit. Redraw the combinational part of circuit in the box and make all the connections. Note the FF labels: FF2 is drawn above FF. Z Q D FF2 Q D FF Figure 5: Figure for combinational part of the sequential circuit The circuit within the block is in Figure 6 (b) (4 points) Draw the time frame expansion of this circuit for three time frames. Clearly draw the timeframe boundaries and label them. Mark the inputs, outputs, pseudo primary inputs and pseudo primary outputs appropriately in the model you The draw. timeframe expansion model is shown in Figure 7 Fall 203 (Lec: Saluja)

12 Z Q D FF2 Q D FF Figure 6: Figure for combinational part of the sequential circuit Z Z Z X 0 0 X X X D X X D Figure 7: Time frame expansion of the sequential circuit (c) (4 points) Derive a test sequence that will detect a stuck-at fault at the output of OR gate. You can use any method you like. Use the time frame expansion drawn by you to show clearly the values of the inputs and the time the values are applied. You must also indicate the time the fault is detected and what will be the expected output and the output of the faulty circuit for the input sequence obtained by you. The input sequence will be (t=) 0X, (t=2) X0, (t=3) XX The fault will be detected after application of second clock, i.e. in the third timeframe. The output will be D, i.e. expected output is 0 and faulty circuit will produce a. 2 Fall 203 (Lec: Saluja)

13 8. (5 points) Checking Experiment State table of a finite state machine with four states,,, C, and D; and a binary input alphabet consisting of 0, and ; is given in Table. Table : State Machine for Problem 8 Input 0 /0 C/0 / D/ C /0 D/0 D / D/ Now consider applying the sequence 0 to this machine. Note when this sequence is applied the initial state of the machine is not known. (a) (2 points) What will be the output sequence. When the output is not known write an X for that. The output sequence will be x x x. (b) (2 points) What will be the state sequence. When the state is not known just indicate the state ambiguity. ssume before the sequence is applied the state ambiguity is (CD). The state ambiguities will be: (CD) () (CD) D D (c) ( points) Does this machine initialize to some state during the application of the above sequence. Clearly machine initializes to state D after the input 0. (d) (2 points) Find a shortest synchronizing sequence for this machine. You must show your work otherwise no points will be awarded. This machine has three shortest synchronizing sequences which are initializes to state ; and 0 - initializes to state ; initializes to state D. 3 Fall 203 (Lec: Saluja)

14 (e) (4 points) Now consider a fault which causes the above machine to change to the state table shown in Table 2. Note that there is only one change due the fault and that is next state of with input 0 is C instead of. Table 2: State Machine of the Faulty Machine for Problem 8 Input 0 /0 C/0 C/ D/ C /0 D/0 D / D/ Will the above sequence detect this fault? You must show your work otherwise no credit will be given. The faulty machine will produce the following output sequence: x x x This is same as the fault free machine. Hence, this sequence will not detect the fault. (f) (4 points) ppend a shortest possible sequence to the above sequence to detect the fault described above. gain, you must show your work otherwise no credit will be given. First we notice that the faulty machine has exactly the same state (D) at the end of sequence 0 as the fault free machine. We apply a 0 and transfer the machine to state. Now we apply the input 0 which will transfer the fault free machine to state while the faulty machine will transfer to state C. Now we use Distinguishing sequence to differentiate between the states and C. This machine has two DS, 0 0 and 0. Either of these will work. Thus we must append or to detect the fault. 4 Fall 203 (Lec: Saluja)