Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall Final Examination

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1 Department of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable Design of Digital Systems Fall Final Examination CLOSED BOOK Kewal K. Saluja Date: December 17, 2013 Place: Room 2540 Engineering Hall Time: 12:25-2:25 PM Duration: 120 minutes PROBLEM TOPIC POINTS SCORE 1 General/PreMidterm 10 2 Test Economics 10 3 TEST GEN 10 4 CHECK-SEQ 10 5 MEMORY 14 6 PSEUDO-EXH 12 7 DFT-TEST TIME 16 8 BIST 14 9 BOUNDARY SCAN 4 TOTAL 100 BONUS 5 Name: Last Name: First Name: (Please Print in Capitals) Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Use facing page when ever you need more space to write 1 Fall 2013 (Lec: Saluja)

2 1. (10 points) General and Pre-Midterm Answer the following. Use only the space provided and be brief. (a) (2 points) In a two input NAND gate with inputs A and B and output Z Which of the following fault(s) can be removed due to dominance fault collapsing and why? A s-a-0, A s-a-1, B s-a-1, Z s-a-0 (b) (1 points) True or False. Method of Boolean Difference will always find a test for a fault in the circuit if such a test exists. (c) (4 points) Consider the circuit given in Figure 1 below. I1 I2 A A1 B2 I5 F I3 I4 B A2 B1 I6 G Figure 1: Circuit for Problem 1 - Stuck-fault detection Tests shown in the table below are applied to this circuit. Indicate in the table if the single fault A stuck-at 0, fault B stuck-at 0 will be detected or not by these tests. 2 Fall 2013 (Lec: Saluja)

3 Test # I1 I2 I3 I4 I5 I6 A s-a 0 B s-a (d) (3 points) Consider the circuit given in Figure 2 below. x1 x2 x3 x4 x5 A B x6 (b) Bridging fault F G Figure 2: Circuit for Problem 1 - Bridging-fault detection Assume that the bridging fault as shown in the circuit is an OR type bridging fault between lines A and B. Note that an OR type bridge means that if the lines A and B are bridged and if any of the lines A or B is logic 1 than both A and B will take logic 1 values. Show in the table below which tests will detect the OR types bridging fault in the circuit. Test # X1 X2 X3 X4 X5 X OR-Bridge 3 Fall 2013 (Lec: Saluja)

4 2. (10 points) Test Economics A fab house uses the following yield equation for its devices. Y = [1+a(1 e cf )] b In this equation a, b and c are process parameters and f is fault coverage. (a) (5 points) For the process parameters a = 1.8; b = 0.7; c = 2.8 and fault coverage f = 90% determine the yield of the process. (b) (5 points) In the yield equation given above it is assumed that for the fault coverage of 100% the yield will be true yield containing no bad devices. Determine the defect level for the conditions given in part (a), assume that the test is such that it will never fail a good device. Note that defect level is defined as the ratio of potentially bad devices in a batch to the total devices tested good. Express your answer in ppm (parts per million) 4 Fall 2013 (Lec: Saluja)

5 3. (10 points) Sequential Test Generation Consider the sequential circuit shown in Figure 3 that uses two edge trigger D-type flip-flops. Derive a test sequence for the fault 2/0/1 (output of gate 2 s-a-1) in this circuit. Assume the initial states of both the flip-flops (FF1 and FF2) are set to 0. You can use any method you like. But provide your answer in the following format s-a-1 X 4 3 FF1 FF2 D Q 6 D Q 7 9 Figure 3: Circuit for Test Generation Enter the state and output values using 9 value logic consisting of 0, 1, D, D, G0, G1, F0, F1, and X. In the comments column provide information about need for your action, such as need to excite fault, sensitize fault, etc. Time Present Input Next Output (t) State (X) State (gate 10) Comments FF1 FF FF1 FF2 5 Fall 2013 (Lec: Saluja)

6 4. (10 points) Checking Sequence Consider a six state finite state machine (FSM) given below. Present State Next State/Output x = 0 x = 1 A B/0 A/0 B C/1 B/1 C D/0 C/0 D E/1 D/0 E F/0 E/0 F A/1 A/1 (a) (2 points) Assume that the initial state of this machine is either A or B. Now consider applying a sequence of length four to this FSM. What will be the output sequence? (b) (2 points) Assume that the initial state of this machine is either E or F. Now consider applying a sequence of length four to this FSM. What will be the output sequence? 6 Fall 2013 (Lec: Saluja)

7 (c) (6 points) You are told that on start-up this FSM can NOT be in states A or F. Thus the initial ambiguity of the FSM is {B C D E}. Find a shortest sequence that can differentiate between these four states. You must show your work to get any credit for this question. 7 Fall 2013 (Lec: Saluja)

8 5. (14 points) Memory testing Consider the following March algorithm: { (W0); (R0,W1,R1); (R1,W0,R0)} This algorithm is used to test a large memory consisting of a total of n cells. You can assume that the initialization step correctly sets each memory cell to 0. (a) (2 points) How many march elements this algorithm has and what is the length of the above test. Also label the march elements as M0, M1,... (b) (3 points) Consider a memory fault in which whenever the content of cell 250 is changed, the cell 200 will also change state (inversion coupling fault). While answering below, if a fault is excited or detected multiple times list all those. i. Will the above fault be excited and in which march element? ii. Will the above fault be detected and in which march element? (c) (3 points) Consider a memory fault in which whenever the content of cell 1250 is changed, the cell 5000 will also change state (inversion coupling fault). While answering below, if a fault is excited or detected multiple times list all those. i. Will the above fault be excited and in which march element? ii. Will the above fault be detected and in which march element? 8 Fall 2013 (Lec: Saluja)

9 (d) Consider a three coupling fault in which cell content of a cell i changes when cell j is changed and cell k is 1. i. (2 points) For i = 500, j = 3000, and k = 5500, when will this fault be excited and when will it be detected? ii. (2 points) For i = 3700, j = 3000, and k = 500, Will this fault be detected and in which march element? (e) (1 points) Will the original algorithm detect cell stuck-at 0 and 1 faults in the memory array? (f) (1 points) Will the original algorithm detect transition faults in the memory array? 9 Fall 2013 (Lec: Saluja)

10 6. (12 points) Pseudo-exhaustive testing Consider the circuit below in Figure 4 with 6 primary inputs and 3 primary outputs. This circuit is to be tested using pseudo-exhaustive testing with sensitized partitioning. The partitions are shown in the figure. Note that each gate forms a partition and it must be tested exhaustively using all 4 tests. Also remember when a partition is tested its output must be sensitized to a primary output. Derive a smallest test set (using A B G I C D H K E F J Figure 4: Figure for Pseudo-exhaustive Test Generation fewest test vectors) to test this circuit so that each partition is tested exhaustively. You can derive tests using any method you like but list your tests in the table below which requires you to list and check the inputs and outputs of each partition for each test. Note that you may not need as many vectors as the space provided in the table. Also, some of the column headings repeat to make the checking easier, but these columns must have identical entries to be consistent. 10 Fall 2013 (Lec: Saluja)

11 Test # A B G C D H G I E F J I K 11 Fall 2013 (Lec: Saluja)

12 7. (16 points) DFT and Test application time Block diagram level design of part of a large circuit (embedded circuit) is shown in Figure 5. The circuit details such as R1 consists of 200 FFs, block C1 requires 110 test vectors to test it, are provided in the figure. Additional relevant details about testing are provided below. Scan in R1 flip flops (200 ffs) S1 R4 flip flops (72 ffs) S2 B C1 110 vectors R2 flip flops (150 ffs) C2 25 vectors bypass mux C bist cycles and 10 vectors R5 flip flops (24 ffs) Scan out R3 flip flops (20 ffs) Figure 5: Embedded circuit with serial scan chain and BIST hardware C3 is an interesting block and it is tested in two parts. By initializing R4 and R5 and choosing appropriate control values (see below) it is tested in BIST mode using clock cycles. In addition another 10 scan vectors are needed to test this fully for the desired fault coverage. The control signals (S1, S2, B) are as follows: S1 = 1: R1, R2 and R3 in scan mode; S1 = 0: System mode for R1, R2, R3; S2 = 1 & B = 0: R4 and R5 in scan mode; S2 = 0 & B = 1: C3 in BIST mode, i.e. R4 is Pattern Generator and R5 is MISR; S2 = 1 & B = 1: R4 and R5 hold mode; S2 = 0 & B = 0: System mode for R4 and R5. Note: when B = 1, the mux output (scan input to R2) is the scan-out of R1, thus R4 12 Fall 2013 (Lec: Saluja)

13 and R5 are bypassed. (a) (1 points) What is the number of inputs to the combinational block C1? (b) (1 points) What is the number of outputs of the combinational block C1? (c) (2 points) How may clock cycles are required to initialize all registers using scan and what should be the values of the control signals S1, S2 and B. (d) (2 points) If a test has been applied to all three blocks (C1, C2, C3) and the result of this test needed to be scanned-out, how many clock cycles are needed and what should be the values of the control signals S1, S2, B. (e) (2 points) What is the minimum number of clock cycles to test only the block C1 and what should be the values of the control signals S1, S2, B. (f) (2 points) What is the minimum number of clock cycles to test only the block C2 and what should be the values of the control signals S1, S2, B. 13 Fall 2013 (Lec: Saluja)

14 Figure 5 reproduced below for your convenience Scan in R1 flip flops (200 ffs) S1 R4 flip flops (72 ffs) S2 B C1 110 vectors R2 flip flops (150 ffs) C2 25 vectors bypass mux C bist cycles and 10 vectors R5 flip flops (24 ffs) Scan out R3 flip flops (20 ffs) Figure 5: Embedded circuit with serial scan chain and BIST hardware 14 Fall 2013 (Lec: Saluja)

15 (g) (3 points) What is the minimum number of clock cycles to test the block C1 and C2 and what should be the values of the control signals S1, S2, B. Note this is less then the sum of the clock cycles to test C1 alone and C2 alone. (h) (3 points) What is the minimum number of clock cycles to test only the block C3 and what should be the values of the control signals S1, S2, B. Note to test this block you will have to use BIST and 10 scan vectors and before invoking BIST mode for this, R4 and R5 must be initialized. (i) (5 BONUS points) What is the minimum test application time to test all three combinational blocks. calculate the total number of test cycles. (I will check this part only if your solutions to all the previous parts are correct) 15 Fall 2013 (Lec: Saluja)

16 8. (14 points) BIST Answer the following and you must show your work for full credit. (a) (4 points) Realization of a 4-bit mixed mode (internal/external EOR Linear Feedback Shift Register (LFSR) along with the labeling of flip-flops is given in the Figure 6 below. x3 x2 x1 x0 Figure 6: A mixed mode linear feedback shift register Write the companion matrix T s for the above LFSR by completing the following matrix equation. x0(t+1) x1(t+1) x2(t+1) x3(t+1) = x0(t) x1(t) x2(t) x3(t) (b) (4 points) Companion matrix T s of an LFSR is given below: T s = Write the characteristic polynomial of this LFSR. 16 Fall 2013 (Lec: Saluja)

17 (c) (3 points) For each of the following polynomials indicate if it can be factored or not. And if it can be factored, give its smallest degree factor. i. x 7 +x 3 +x 2 +x ii. x iii. x 51 +x 49 +x 2 +1 (d) (3 points) Give an external exclusive-or (standard) LFSR realization of the polynomial x 4 +x 2 +x Fall 2013 (Lec: Saluja)

18 9. (4 points) Boundary scan Answer the following: (a) (1 points) How many mandatory extra pins does each device need to have relative to non-boundary scan environment and name the signals associated with each of these pins.? (b) (1 points) List all the mandatory instructions required by the Boundary scan standard. (c) (1 points) List two possible optional instructions and explain their functionality that can be integrated with Boundary scan. (d) (1 points) Are the power and ground pins placed in the boundary scan data register? 18 Fall 2013 (Lec: Saluja)