Testability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.

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1 Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27

2 Outline What is simulation? i Circuit modeling True-value simulation algorithms Compiled-code simulation Event-driven simulation Summary Slide 2 of 27

3 Simulation Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Applications of simulation: Verification Debugging Studying design alternative (cost/speed) Computing expected behavior for testing purposes Simulation for design verification: Validate assumptions Verify logic; e.g., independent of power-up state free of critical races & oscillation Verify performance (timing) Slide 3 of 27

4 Simulation Problems of simulation-based design verification Tests are hand crafted A heuristic process that relies heavily on the designer s intuition & design knowledge Not a precise procedure Very hard to prove that a test is complete. Types of simulation: Logic or switch level Timing Circuit Fault Slide 4 of 27

5 Evaluating a Logic Simulator Attributes are accuracy, efficiency and generality Accuracy: close correspondence between the predicted signal values & times, as calculated by the logic simulator and those occurring in the real circuit Efficiency: Simulators must be cost-effective Generality: Should be able to handle a broad class of circuits Synchronous, Asynchronous Combinational, Sequential Race/Hazard detection capabilities Slide 5 of 27

6 Simulation for Verification Specification Synthesis Response analysis Design changes Design (netlist) Computed responses True-value simulation Input stimuli Sharif University of Technology Testability: Lecture 6 Slide 6 of 27

7 Modeling for Simulation Modules, blocks or components described by Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and capacitors Interconnects represent ideal signal carriers, or ideal electrical conductors Netlist: a format (or language) g that describes a design as an interconnection of modules. Netlist may use hierarchy. Slide 7 of 27

8 Example: A Full-Adder a b d HA e c f HA; inputs: a, b; outputs: c, f; AND: A1, (a, b), (c); AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); A B C HA1 D E HA2 F Carry Sum FA; inputs: A, B, C; outputs: t Carry, Sum; HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2, (D, F), (Carry); Sharif University of Technology Testability: Lecture 6 Slide 8 of 27

9 Signal States Two-states (0, 1) can be used for purely combinational logic with zero-delay, and for synchronous circuits with a known initial state. Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. X (unknown state) represents: Initial state of FFs and RAMs Interpreted as either 0 or 1 Four-states (0, 1, X, Z) are essential for MOS devices. 0 0 Z (hold previous value) Analog signals are used for exact timing of digital logic and for analog circuits. Slide 9 of 27

10 Information Loss of 3-Valued Logic 3-value simulation symbolic simulation The three-state logic is pessimistic. Symbolic simulation can be effective if performed locally in a circuit. impractical for large circuits. Sharif University of Technology Testability: Lecture 6 Slide 10 of 27

11 Modeling Levels Modeling level Function, behavior, RTL Circuit Signal Timing description values Programming language-like HDL 0, 1 Clock boundary Application Architectural and functional verification Logic Connectivity of Boolean gates, flip-flops p and transistors 0, 1, X and Z Zero-delay, unit-delay, multipledelay Logic verification and test Switch Transistor size and connectivity, node capacitances 0, 1, X and Z Zero-delay Logic verification Timing Transistor technology Analog data, connectivity, voltage node capacitances Circuit Tech. Data, active/ Analog passive component voltage, connectivity current Sharif University of Technology Testability: Lecture 6 Fine-grain timing Continuous time Timing verification Digital timing and analog circuit verification Slide 11 of 27

12 True-Value Simulation Algorithms True-Value refers to no fault in circuit Compiled-code simulation The compiled code is generated from an RTL or gate-level description of the circuit Simulation is simply execution of the compiled code Applicable to zero-delay combinational logic Timing cannot be properly modeled no hazard or signal propagation is predicted Also used for cycle-accurate synchronous sequential circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits Because time required to simulate a vector = t *N; where t = time required to simulate an element N = number of elements High-level (e.g., C language) models can be used Slide 12 of 27

13 True-Value Simulation Algorithms (cont d) Event-driven simulation Only gates or modules with input events are evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits The ratio of lines which change values to the total number of lines in the circuit is called activity Typically activity = 2-10 % Can be extended for fault simulation Slide 13 of 27

14 Compiled-Code Algorithm Step 1: Levelize combinational logic and encode in a compilable programming language Assign all PI lines level 0 The level l of a gate g is: Lg = 1 + max ( L i1, L i2, L in ) L i1, L i2, L in are levels of inputs of gate g. Step 2: Initialize internal state variables (flip-flops) flops) Step 3: For each input vector St Set primary input variables ibl Repeat (until steady-state or max. iterations) Execute compiled code Elements are simulated in ascending order of logic level Report or save computed variables Slide 14 of 27

15 Compiled Simulation (Example) Given circuit C: 2. Generate code 1. Levelize circuit Level 0: a, b, c, d Level 1: e, f Level 2: g Level 3: i Level 4: j while(1) { Read_in ( a, b, c, d ) ; e = NAND ( a, b ) ; f = INV ( c ) ; g=nor(b b, f); i = AND ( e, i ) ; j = NAND ( i, d ); Print ( e, i, j ) ; } Sharif University of Technology Testability: Lecture 6 Slide 15 of 27

16 Event-Driven Algorithm Slide 16 of 27

17 Event-Driven Algorithm (Event scheduling) a =1 c =1 0 b=1 g 2 2 d = e =1 2 f =0 g =1 Time, t stack Time Scheduled events Activity list t = 0 c= 0 d, e 1 2 d = 1, e = 0 f, g 3 4 g = f = 1 g 7 8 g = 1 Sharif University of Technology Testability: Lecture 6 Slide 17 of 27

18 Gate Evaluation - Input Scanning Assume only dealing with AND, OR, NAND, NOR primitive gates These gates can be characterized by controlling value c & inversion i AND 0 0 OR 1 0 NAND 0 1 NOR 1 1 c i Inputs Output t c x x c i x c x c i x x c c i c c c c i Sharif University of Technology Testability: Lecture 6 Slide 18 of 27

19 Delay Types Transport (propagation) delay: time interval between the generation of a signal transition at a gate output (source) and its arrival at the input of a fanout gate transition independent transition dependent : rise/fall delays specified separately Inertial (switching) delay: time interval between an input change and the output change of a gate. Slide 19 of 27

20 Logic Model of MOS Circuit pmos FETs a b C a C b V D D C c nmos FETs c a b D a D c D b D a and D b are interconnect or propagation delays c C a, C b and C c are parasitic capacitances D c is inertial or switching delay of gate Sharif University of Technology Testability: Lecture 6 Slide 20 of 27

21 Switching Delay Models Zero delay: Output changes instantly in response to an input useful for logic simulation of combinational circuits Unit delay: All gates have one unit delay, no delay for interconnects circuits with feedback can also be simulated Multiple delay: delays are modeled as multiples of some time unit Each gate is assigned a rise delay (d r ) and a fall delay (d f ) Ambiguous delay or Minmax delay Slide 21 of 27

22 Options for Inertial Delay (simulation of a NAND gate) Inputs a b Transient region c (CMOS) c (zero delay) ic simula ation c (unit delay) c (multiple delay) rise=5, fall=3 Logi c (minmax delay) Unknown (X) min =2, max =5 0 5 Time units Sharif University of Technology Testability: Lecture 6 Slide 22 of 27

23 Event-Driven Simulation with Delay Need a time-flow mechanism Sharif University of Technology Testability: Lecture 6 Slide 23 of 27

24 Time Flow Mechanism & Event Scheduling When an element i is simulated and it is determined that its output signal j has changed state; i.e., V new (j) V old (j), then signal j must be scheduled to change to V new (j) at time t+ Δi where t : the current simulation time Δi : the delay of element i The event ( j, Vnew ( j), t+ Δi ) is scheduled to occur in the future. Need an event queue for each time of simulation Slide 24 of 27

25 Time Wheel (Circular Stack) Current time pointer max t= Event link-list Sharif University of Technology Testability: Lecture 6 Slide 25 of 27

26 Efficiency of Event-driven Simulator Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change Steady 0 0 to 1 event Steady 0 (no event) Large logic block without activity Slide 26 of 27

27 Summary Logic or true-value simulators are essential tools for design verification. Verification vectors and expected responses are generated (often manually) from specifications. A logic simulator can be implemented using either compiled-code or event-driven method. Per vector complexity of a logic simulator is approximately linear in circuit size. Modeling level determines the evaluation procedures used in the simulator. Slide 27 of 27

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview

ECE 407 Computer Aided Design for Electronic Systems. Simulation. Instructor: Maria K. Michael. Overview 407 Computer Aided Design for Electronic Systems Simulation Instructor: Maria K. Michael Overview What is simulation? Design verification Modeling Levels Modeling circuits for simulation True-value simulation