Department of Electrical and Computer Engineering University of Wisconsin Madison. Fall

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1 Department of Electrical and omputer Engineering University of Wisconsin Madison Fall - Assignment # Date: Thursday, ctober, Due date: Tuesday, November, Solution utline. ( points) (ushnell and Agrawal) Problem. The following figure shows the SAP testability and controllability values for the combinational circuit. (,) z (,) a (,) e F (,) z c (,) (,) b z (,) f (,)7 7 (,) (,) d z 7 F (,) (,) ircuit of Figure. with combinational SAP measures. Fall (Lec: Saluja)

2 . ( points) (ushnell and Agrawal) Problem. The steps of calculation for SAP testability measures are shown in the three figures that follow. ombinational measures are shown as (, ) and sequential measures as [S, S]S. (,) (,) (,) (,) (,) (, ) [, ] 7 (,) (, ) [, ] (,) (,) (,) (, ) [, ] Q D FF (,) M LK (,) RESET (,) ircuit of Figure.: P and P initialization and first controllability pass. (,) (,) (,) (,) (,) (,) [,] 7 (,) (,) [,] (,) (,) (,) (,7) [,] Q D FF (,) M LK (,) RESET (,) ircuit of Figure.: onverged controllability values. Fall (Lec: Saluja)

3 (,) (,) (,) (,) (,) (,) [,] 7 (,)9 (,)7 [,] 9 9 (,) (,) (,) (,7) [,] Q FF D (,)7 M LK (,) RESET (,) ircuit of Figure.: All controllability and observability values.. ( points) (ushnell and Agrawal) Problem. The required test has two steps: (a) Fault activation. Assuming the present state to be unknown, we set the net state to. For n =, backward justification of n+ = in Figure. (see page of the book) gives us A n = and n =. (b) Path sensitization. For the net vector, the above net state becomes the present state and the fault n s-a- is sensitized. We sensitize a path from n to S n by setting A n = and n =. Thus, the test sequence is (A n, n ) = (,), (,). Fall (Lec: Saluja)

4 . ( points) (ushnell and Agrawal) Problem. The following figure illustrates the time-frame epansion procedure of generating a vector, A =, =, which starting from the unknown state detects the fault A s-a- as /. After the application of the input vector, the flip-flop is clocked before the output can be observed. Even if we add more vectors to the test sequence, the faulty circuit output will not become deterministic. This is because the faulty circuit is not initializable. The fault is only potentially detectable. A A== sa / / / / Time frame / Time frame,, A sa,,,/, /,/,/ /,/,/,/, /,/,/ /,,/ FF,, A sa,/,,,,,/ /,/,/ /,/,/ /,,/ /,/,/,/,/ FF Test simulation with initial state. Test simulation with initial state.,,/ Note: Some test generators will find the potential detection test of the above type. thers will consider the fault untestable (conservative approach.) Most fault simulators will find the fault potentially detectable. nterestingly, the two test simulation scenarios in the figure show that the fault is definitely detectable, though the detection requires multiple observations. f we assume the initial state to be then the fault is detected as / after the application of the first clock. However, this output will be (same as the correct output) if the initial state was. n this case, repeating the same vector and clocking once again will produce a / output. A conventional fault simulator will not report such detection because it does not enumerate the possible initial state scenarios. For such multiple observation tests see reference [] of the book. Fall (Lec: Saluja)

5 . ( points) (ushnell and Agrawal) Problem. The pseudo-combinational circuit and a combinational test, A =, =, for the fault D s-a- are shown in the following figure. Simulation of the sequential circuit with input A =, =, repeated four times shows that the fault will be detected as / appearing as the fourth output. We assume that the initial states of all three flip-flops are. D s a / A Z / E Pseudo combinational circuit for the sequential circuit of Figure.9.. D s a /,/,/,/ A,,,,,, F,,,,,, F,,, E,,, F,,, Z /,/,/,/ Test simulation in sequential circuit.. ( points) The finite state machine M7 in Table has a single input, a single output, and states. (a) s this a strongly connected machine? (b) Find a shortest synchronizing sequence for this machine. (To make grading easier, please designate the left branches of your tree correspond to nput = for all trees in parts (b), (c), and (d).) (c) Find a minimum length distinguishing sequence. Tabulate the output responses, initial and final states of applying your distinguishing sequence to the machine in each of the starting states. (d) Find a minimum length homing sequence which is different from the distinguishing sequence found in part (c). Fall (Lec: Saluja)

6 Table : State Machine M7 for Problem. nput A A/ / E/ E/ / D/ D D/ / E E/ A/ a.) t is strongly connected. b.) You can draw a synchronizing tree and obtain an SS = and final state will be E. c.) A distinguishing tree is given below and two distinguishing sequences are DS = or DS = DS = STATE UTPUT FNAL STATE STATE UTPUT FNAL STATE A D A A E D A D A E E D Fall (Lec: Saluja)

7 (ADE) (EE)(AD) (D)(AE) (E)(D),(E)(A) ()(E),(D)(A) (E)(D),(E)(A) (A),(),(A),()(D) (E),(D),(D),(A) (E),(A),(),(D)() d.) The homing tree is given in the figure below and a Homing sequence = ADE (E)(AD) (D)(AE) (E)(AD) (A)(D)() (E)(D)(E)(A) (E)()(D)(A) (A)(E)(D)() 7. ( points) The finite state machine in Fig. has a single input, a single output, and states. (a) onvert the state machine into a state transition table like the one given in Problem. (b) Find a shortest synchronizing sequence for this machine. (c) Find a minimum length distinguishing sequence. Tabulate the output responses, initial and final states of applying your distinguishing sequence to the machine in each of the starting states. (d) Design a checking sequence for this machine such that the total length of the sequence is small. Note that you can achieve this by choosing appropriate transfers while designing the checking sequence. You may use SS to denote the synchronizing sequence you found in part (a) and DS to denote distinguishing sequence you found in part (b). Likewise, you may use T ij to denote transfer sequence from state i to state j. However, you have to clearly indicate what the sequences are in 7 Fall (Lec: Saluja)

8 terms of inputs, and the states after the application of the sequences. n addition, also indicate the epected outputs whenever the outputs are to be observed. Figure : State Diagram Figure for Problem 7. a)the state machine is given in the tabular form as follows: Table : State Machine for Problem. nput A A/ / E/ / / D/ D / A/ E A/ / Fall (Lec: Saluja)

9 b)the shortest SS for the given State Machine is :. c)there are two shortest length Distinguishing Sequences : and. The initial and final states can be tabulated as follows: DS = DS = nitial utput Final nitial utput Final A A D E D D A D E E E d)a sample test plan can be given as follows. Phase : SS DS DS DS DS DS A A-> -> ->D D->E E->A Phase : Many different solutions possible. n possislbe solution TSA DS TS DS TSD DS TS DS TSA DS TS DS TS DS TSA DS A D A E A D E D A <TS> TSE DS <TS> TS DS E The entries in backets note an inefficency. 9 Fall (Lec: Saluja)