Assignment #1 SOLUTION

Transcription

1 epartment of Electrical and Computer Engineering University of Wisconsin Madison ECE 553: Testing and Testable esign of igital Systems Fall Assignment #1 SOLUTION 1. (10 points) A certain fabrication process has a true yield of 75%, i.e. it produces 75% good devices. The testing mechanism for the finished ICs has an accuracy of 96%. Find the yield and the defect-level of this test process for producing ICs. Note: This problem is similar to Prob 1-1 from the text and does not use the yield model of chapter 3. efect level is defined as the ratio of bad devices tested good relative to the total number of devices tested good. True yield alludes to the device yield with zero defect level. The following convention can be used: P: chip is good F: chip is bad P: chip passes the test F: chip fails the test A 75% good device production means, Prob(P) = 0.75 and Prob(F) = Similarly, from the given data, we can see that Prob(P/P) = 0.96 and Prob(P/F) = We have to calculate the probability of passing Prob(P) ie. the yield. Prob(P) = Prob(P/P) Prob(P) + Prob(P/F) Prob(F) = = 0.73 Bad chips that pass tests efect level = All chips that pass tests = Prob(F P) = Prob(P F)Prob(F) Prob(P) = = The defect level is 13,699 ppm (parts per million) and the yield is 73%. 1 Fall 2014 (Lec: Saluja)

2 2. (10 points) (Bushnell and Agrawal) Problem 1-4 Note: Use Example 1.2 in the textbook for ATE purchase price, deprecation rate, maintenance, and operating cost. Following Example 1.2 of the book (pp ), we obtain ATE purchase price = $1.2M +256 $3,000 = $1.968M Assuming a 20% per year linear rate of depreciation, a maintenance cost of 2% of the price, and an annual operating cost of $0.5M, Running cost = $1.968M 0.2+$1.968M 0.02+$0.5M = $932,960/year Testing cost = $932, 960 = 2.96 cents/second Testing cost of the self-test design is 2.96 cents per second, down from 4.50 cents per second calculated in Example (10 points) (Bushnell and Agrawal) Problem 2-4 Note: Assume that the setup time is 400ps and the clock-to- delay is also 400ps. raw waveform for input/output to explain devised test method. To test a hold time, t hold = 120ps, apply the following waveforms to the chip (a clockto- delay of 400ps is assumed): MC 120ps Inputs CLK 400ps 400ps 450ps Measure Output At an interval of 120ps after the rising CLK edge, we lower the line. If = 1 450ps (note: it must be more than 400ps) after the rising CLK edge, the device passes, otherwise it fails. Using MS instead of MC, repeat the above waveform sequence, but with inverted and the expected signal also inverted. This at an interval of 450ps (i.e, as before more than 400ps) after the rising CLK edge, again measure on the ATE. If = 0, the device passes, otherwise it fails. The same waveforms are applied simultaneously to all five lines, and five simultaneous measurements are made on the five lines. 2 Fall 2014 (Lec: Saluja)

3 4. (15 points) (Bushnell and Agrawal) Problem 3-6 with changed values of f,β,t as follows: f = 1.51 β=0.13 T=0.94 Substituting the given fault density, f = 1.51 faults/cm 2, the fault clustering parameter, β = 0.13, and the fault coverage, T = 0.94, in Equation 3.20 (page 50 of the book), we obtain the defect level as, ( ) β +TAf β L(T) = 1 β +Af ( ) = = or 7360 parts per million The defect level is 7360 parts per million (ppm). (a)toobtainthefaultcoveraget forarequireddefectlevel of1,000ppm, wesubstitute L = 0.001intheequationforL(T)andcomputeT. Noteyouwillgettheexpression for T as in problem 3.5. T = ( ) / = The required fault coverage is 99.17%. (b) For a defect level of 500 ppm (L = ), we get T = ( ) / = The required fault coverage is 99.58%. 5. (15 points) (Bushnell and Agrawal) Problem 3-7 Hint: Of the many ways to do this, one way is to write the binomial expansion of the exponential expression (1+(Af/β)) β and then set β efect level, L(T), given by Equation 3.20 (p. 50 of the book), can be written as: L(T) = 1 (1+TAf/β)β (1+Af/β) β = 1 etaf e Af = 1 e Af(1 T), as β 3 Fall 2014 (Lec: Saluja)

4 Note that, ( 1+ x β) β can be written as e x as β using Taylor expansion. Also, as β, Equation 3.19 (p. 50 of the book) gives the yield, Y = ( 1+ Af ) β = e Af β Substituting this expression for yield in the defect level, we get which is the required result. L(T) = 1 (e Af ) 1 T = 1 Y 1 T 6. (15 points) A digital system board uses 64 ICs manufactured in two different independent processes. 48 of the ICs are manufactured in process A with 86% yield and with 96% fault coverage. The remaining ICs (16) are manufactured in process B with 72% yield and with 98% fault coverage. Assuming that the production process and the test program which is used to identify faulty boards are perfect, what is the yield of the manufactured board? Note: You will have to choose appropriate yield models to compute the defect levels and specify the yield models that are used. The yield model chosen will be L = 1 Y 1 T, because the statistics provided do not specify β and it will be assumed as β. For ICs with Process A: Fault coverage = 96% Yield = 86% L1 = (efectlevel1) = 1 Y (1 T) = For ICs with Process B: Fault coverage = 98% Yield = 72% L2 = (efectlevel2) = 1 Y (1 T) = Board Yield = Pr(all IC s are fault free) = (1 L1) 48 (1 L2) 16 = (15 points) raw each of the following circuits located at the following locations(these files can be accessed using your CAE-UNIX account). ~ece553/testca/nets/hw1-circuits/circuit-1 ~ece553/testca/nets/hw1-circuits/circuit-2 4 Fall 2014 (Lec: Saluja)

5 However, you can also access these circuits on hte course webpage using the links given below this homework link. Though, I would prefer that you start using CAE-UNIX accout now. See figures next page 8. (10 points) Using your circuit drawn for circuit-1 in problem 7, simulate following four vectors and specify the output of each vector. PI V V2 X V X X V4 1 X PO PO PI V V2 X V X X 0 X V4 1 X X 5 Fall 2014 (Lec: Saluja)

6 1 HW1-7 circuit HW1-7 circuit-2 G10 G0 G14 G17 SET CLR G5 G11 SET CLR G6 G1 G8 G9 G7 G2 G3 G16 SET CLR G15 G13 G12 6 Fall 2014 (Lec: Saluja)