MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON

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1 INCH-POUND 2 November 2005 SUPERSEDING MIL-M-38510/71C 23 July 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF SCOPE Inactive for new design after 23 August Scope. This specification covers the detail requirements for monolithic, silicon, Schottky TTL, bistable logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided for each type and are reflected in the complete part number. For this product, the requirements of MIL-M have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein Device types. The device types are as follows: Device type Circuit 01 Dual, D-type edge triggered flip-flop 02 Dual, J-K edge triggered flip-flop 03 Dual, J-K edge triggered flip-flop, no clear 04 Dual, J-K edge triggered flip-flop, common clear and clock 05 Hex, D-type edge triggered flip-flop 06 Quad, D-type edge triggered flip-flop Device class. The device class is the product assurance level as defined in MIL-PRF Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A GDFP5-F14 or CDFP6-F14 14 Flat pack B GDFP4-F14 14 Flat pack C GDIP1-T14 or CDIP2-T14 14 Dual-in-line D GDFP1-F14 or CDFP2-F14 14 Flat pack E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat-pack X CQCC2-N20 20 Square chip carrier 2 CQCC1-N20 20 Square chip carrier Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH , or ed to bipolar@dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at AMSC N/A FSC 5962

2 1.3 Absolute maximum ratings. Supply voltage range V dc to +7.0 V dc Input voltage range V dc at -18 ma to 5.5 V dc Storage temperature range C to +150 C Maximum power dissipation per flip-flop, (P D ) 1/ Device types 01, 02, 03, mw dc Device type mw dc Device type mw dc Lead temperature (soldering 10 seconds) C Thermal resistance, junction-to-case (θ JC )... (See MIL-STD-1835) Junction temperature (T J ) 2/ C 1.4 Recommended operating conditions. Supply voltage (V CC ) V dc minimum to 5.5 V dc maximum Minimum high level input voltage (V IH ) V dc Maximum low level input voltage (V IL ) 3/ V dc (see figures 5 through 16 for individual device type input-setup time and input-hold time.) Case operating temperature range (T C ) C to 125 C 2.0 APPLICABLE DOCUMENT 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents Specifications and standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD Test Method Standard for Microelectronics. MIL-STD Interface Standard Electronic Component Case Outlines (Copies of these documents are available online at or or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA ) 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Must withstand the added P D due to short circuit condition (e.g. I OS ). 2/ Maximum junction temperature should not be exceeded except in accordance with allowable short duration burn-in screening condition in accordance with MIL-PRF / V IL = 0.7 V dc at +125 C. 2

3 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF and herein Logic diagrams. The logic diagrams shall be as specified on figure Terminal connections. The terminal connections shall be as specified on figure Truth tables. The truth tables shall be as specified on figure Schematic circuits. The schematic circuits shall be maintained by the manufacturer and made available to the qualifying activity and the preparing activity upon request Case outlines. Case outlines shall be as specified in Lead material and finish. Lead material and finish shall be in accordance with MIL-PRF (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table 1 and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements for each device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 10 (see MIL-PRF-38535, appendix A). 3

4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55 C T C +125 C Device Limits type Min Max Units High-level output voltage V OH V CC = 4.5 V; I OH = -1 ma All V Low-level output voltage V OL V CC = 4.5 V; I OL = 20 ma All 0.5 V Input clamp voltage V IC V CC = 4.5 V; I IN = -18 ma; All -1.2 V T C = +25 C Low-level input current at I IL1 V CC = 5.5 V; V IN = 0.5 V 01-2 ma D input Low-level input current at I IL2 V CC = 5.5 V; V IN = 0.5 V ma clear input Low-level input current at I IL3 V CC = 5.5 V; V IN = 0.5 V ma preset input Low-level input current at I IL4 V CC = 5.5 V; V IN = 0.5 V 01, 02, ma clock input Low-level input current at I IL1 V CC = 5.5 V; V IN = 0.5 V 02, 03, ma J or K inputs Low-level input current at I IL2 V CC = 5.5 V; V IN = 0.5 V ma clear input Low-level input current at I IL2 V CC = 5.5 V; V IN = 0.5 V ma clear input Low-level input current at I IL3 V CC = 5.5 V; V IN = 0.5 V 02, 03, ma preset input Low-level input current at I IL4 V CC = 5.5 V; V IN = 0.5 V ma clock input Low-level input current, all I IL1 V CC = 5.5 V; V IN = 0.5 V 05, ma inputs High-level input current at I IH1 01, 02, 50 µa J, K, or D inputs V CC = 5.5 V; V IN = 2.7 V 03, 04 High-level input current at I IH µa clear input 2/ 2/ See footnotes at end of table. 4

5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C T C +125 C Device Limits type Min Max Units High-level input current at I IH3 01, µa preset input 03, 04 V CC = 5.5 V; V IN = 2.7 V High-level input current at I IH4 01, 02, µa clock input High-level input current, I IH5 V CC = 5.5 V; V IN = 5.5 V All 1.0 ma all inputs High-level input current, I IH1 05, µa all inputs High-level input current I IH µa at clear input V CC = 5.5 V; V IN = 2.7 V High-level input current I IH µa at clear input High-level input current I IH µa at clock input Short-circuit output current I OS V CC = 5.5 V 3/ All ma Supply current I CC V CC = 5.5 V 4/ 01, ma 03, 04 V CC = 5.5 V 5/ ma V CC = 5.5 V 5/ ma Maximum collector cutoff I CEX V CC = 5.5 V; V OH = 5.5 V All 250 µa current V IH = 5.5 V; V IL = GND Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; Propagation delay time, t PLH1 C L = 50 pf 2 10 ns low-to-high level, preset or clear to Q or Q Propagation delay time, t PLH ns low-to-high level, clock to Q or Q See footnotes at end of table. 5

6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C T C +125 C Device Limits type Min Max Units Propagation delay time, t PHL2 V CC = 5.0 V; ns high-to-low level, clock to Q or Q R L = 280 Ω; Propagation delay time, t PHL3 C L = 50 pf ns high-to-low level, preset or clear to Q or Q. Clock high Propagation delay time, t PHL ns high-to-low level, preset or clear to Q or Q. Clock low Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; Propagation delay time, t PLH1 C L = 50 pf ns low-to-high level, preset or clear to Q or Q Propagation delay time, t PLH ns low-to-high level, clock to Q or Q Propagation delay time, t PHL ns high-to-low level, clock to Q or Q Propagation delay time, t PHL ns high-to-low level, preset or clear to Q or Q. Clock high Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; Propagation delay time, t PLH1 C L = 50 pf ns low-to-high level, preset to Q Propagation delay time, t PHL ns high-to-low level, preset to Q Propagation delay time, t PLH ns low-to-high level, clock to Q Propagation delay time, t PHL ns high-to-low level, clock to Q See footnotes at end of table. 6

7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C T C +125 C Device Limits type Min Max Units Propagation delay time, t PLH3 V CC = 5.0 V; ns low-to-high level, clock to Q R L = 280 Ω; Propagation delay time, t PHL3 C L = 50 pf ns high-to-low level, clock to Q Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; 6/ Propagation delay time, t PLH1 C L = 50 pf ns low-to-high level, preset or clear to Q or Q Propagation delay time, t PHL ns high-to-low level, clock to Q or Q Propagation delay time, t PLH ns low-to-high level, clock to Q or Q Propagation delay time, t PHL ns high-to-low level, preset or clear to Q or Q. Clock high Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; 5/ Propagation delay time, t PLH1 C L = 50 pf ns low-to-high level, clock to Q Propagation delay time, t PHL ns high-to-low level, clock to Q Propagation delay time, t PLH ns low-to-high level, clock to Q, clear inactive Propagation delay time, t PHL ns high-to-low level, clear to Q See footnotes at end of table. 7

8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55 C T C +125 C Device Limits type Min Max Units Maximum clock frequency f MAX V CC = 5.0 V; MHz R L = 280 Ω; 5/ Propagation delay time, t PLH1 C L = 50 pf ns low-to-high level, clock to Q or Q Propagation delay time, t PHL ns high-to-low level, clock to Q or Q Propagation delay time, t PLH ns low-to-high level, clock to Q, clear inactive Propagation delay time, t PHL ns high-to-low level, clear to Q Propagation delay time, t PLH ns low-to-high level, clear to Q Propagation delay time, t PHL ns high-to-low level, clock to Q, clear inactive 1/ Complete terminal conditions shall be as specified in table III. 2/ At T C = +125 C, V IL = 0.7 V, V OL maximum = 0.45 V. 3/ Not more than one output should be shorted at a time, duration of short circuit not to exceed 5 seconds. 4/ With all outputs open, I CC is measured with the Q and Q outputs high in turn. At the time of the measurement, the clock input is grounded. 5/ With all outputs open and 5.5 applied to all data and clear inputs, I CC is measured after a momentary ground, then 5.5 V is applied to clock. 6/ f MAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency. 8

9 TABLE II. Electrical test requirements. MIL-PRF Test requirement Interim electrical parameters Subgroups (see table III) Class S Devices 1 1 Class B Devices Final electrical test parameters 1*, 2, 3, 7, 9, 10, 11 Group A test requirements 1, 2, 3, 7, 8, 9, 10, 11 Group B electrical test parameters when using the method 5005 QCI option 1, 2, 3, 7, 8, 9, 10, 11 Groups C end point electrical parameters 1, 2, 3, 7, 8, 9, 10, 11 Group D end point electrical parameters 1*, 2, 3, 7 9 1, 2, 3, 7, 8, 9, 10, 11 N/A 1, 2, 3 1, 2, 3 1, 2, 3 *PDA applies to subgroup VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. 4.2 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF Screening. Screening shall be in accordance with MIL-PRF and shall be conducted on all devices prior to qualification and conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF

10 4.4 Technology Conformance Inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF and herein for groups A, B, C, and D inspections (see through 4.4.4) Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF and as follows: a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted Group B inspection. Group B inspection shall be in accordance with table II of MIL-PRF Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF and as follows: a. End point electrical parameters shall be as specified in table II herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MIL-STD Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF End-point electrical parameters shall be as specified in table II herein. 4.5 Methods inspection. Methods of inspection shall be as specified in the appropriate tables and as follows: Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 10

11 Figure 1. Logic diagrams. 11

12 Figure 1. Logic diagrams - Continued. 12

13 Figure 1. Logic diagrams - Continued. 13

14 Terminal Terminal name number Device type 01 Device type 02 Device type 03 Device type 04 Device type 05 Device type 06 Cases A,B,C,D Cases X and 2 Cases E and F Cases X and 2 Cases A,B,C,D Cases X and 2 Cases A,B,C,D Cases E and F Cases X and 2 Cases E and F 1 CLR 1 NC CLK 1 NC CLK 1 NC CLR CLR NC CLR 2 D1 CLR 1 K1 CLK 1 K1 CLK 1 K1 Q1 CLR Q1 3 CLK 1 D1 J1 K1 J1 K1 J1 D1 Q1 Q 1 4 PRE 1 CLK 1 PRE 1 J1 PRE 1 J1 PRE 1 D2 D1 D1 5 Q1 NC Q1 PRE 1 Q1 NC Q1 Q2 D2 D2 6 Q 1 PRE 1 Q 1 NC Q 1 PRE 1 Q 1 D3 NC Q 2 7 GND NC Q 2 Q1 GND NC GND Q3 Q2 Q2 8 Q 2 Q1 GND Q 1 Q 2 Q1 Q 2 GND D3 GND 9 Q2 Q 1 Q2 Q 2 Q2 Q 1 Q2 CLK Q3 CLK 10 PRE 2 GND PRE 2 GND PRE 2 GND PRE 2 Q4 GND Q3 11 CLK 2 NC J2 NC J2 NC J2 D4 NC Q 3 12 D2 Q 2 K2 Q2 K2 Q 2 K2 Q5 CLK D3 13 CLR 2 Q2 CLK 2 PRE 2 CLK 2 Q2 CLK D5 Q4 D4 14 V CC PRE 2 CLR 2 J2 V CC PRE 2 V CC D6 D4 Q 4 15 NC CLR 1 K2 NC Q6 Q5 Q4 16 CLK 2 V CC NC J2 V CC NC V CC 17 NC CLK 2 NC D5 18 D2 CLR 2 K2 D6 19 CLR 2 CLR 1 CLK 2 Q6 20 V CC V CC V CC V CC FIGURE 2. Terminal connections. 14

15 Device type 01 Device type 02 Inputs Outputs Inputs Outputs Preset Clear Clock D Q Q Preset Clear Clock J K Q Q L H X X H L L H X X X H L H L X X L H H L X X X L H L L X X H* H* L L X X X H* H* H H H H L H H L L Q0 Q 0 H H L L H H H H L H L H H L X Q0 Q 0 H H L H L H H H H H Toggle H H H X X Q0 Q 0 Device type 03 Device type 04 Inputs Outputs Inputs Outputs Preset Clock J K Q Q Preset Clear Clock J K Q Q L X X X H L L H X X X H L H L L Q0 Q 0 H L X X X L H H H L H L L L X X X H* H* H L H L H H H L L Q0 Q 0 H H H Toggle H H H L H L H H X X Q0 Q 0 H H L H L H H H H H Toggle H H H X X Q0 Q 0 H = High level (steady state). L = Low level (steady state). X = Irrelevant. = Transition from low to high level. = Transition from high to low level. Q0 = The level of Q before the indicated input conditions were established. Toggle: Each output changes to the complement of its previous level on each active transition (pulse) of the clock. * This configuration is unstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level. Device types 05 and 06 (each flip-flop) Inputs Outputs Clear Clock D Q Q L X X L H H H H L H L L H H L X Q0 Q 0 = device type 06 only. Figure 3. Truth table. 15

16 NOTES: 1/ Clear and preset inputs dominate regardless of the state of clock or D inputs. 2/ All diodes are 1N3064 or equivalent. 3/ t f = t r 2.5 ns, t A = 10 ns ±20%, t B = 10 ns ±20%, PRR 1 MHz. 4/ C L = 50 pf ±10% including jig and probe capacitance. 5/ R L = 280 Ω ±5%. FIGURE 4. Clear and preset switching time test circuit and waveforms for device type

17 NOTES: 1/ t f = t r 2.5 ns, t (SETUP) L = 5 ns, t (HOLD) L = 3 ns, t (SETUP) H = 5 ns, t (HOLD) H = 3 ns, PRR 1 MHz, t D = 10 ns. 2/ When testing f MAX for subgroup 9, IN(D) PRR = 75 MHz with t D = 6 ns and for subgroups 10 and 11, IN(D) PRR = 55 MHz with t D = 8 ns 3/ C L = 50 pf ±10% including jig and probe capacitance. 4/ R L = 280 Ω ±5%. 5/ All diodes are 1N3064 or equivalent. 6/ See table III for input conditions. 7/ Setup and hold time functionality may be verified by separate test from propagation delay tests, by monitoring the output at specified setup hold conditions. FIGURE 5. Synchronous waveforms and test circuit for device type

18 FIGURE 5. Synchronous waveforms and test circuit for device type 01 - Continued. 18

19 NOTES: 1/ IN(B) and IN(C) have the following characteristics: t B = t C = 10 ns, t f = t r 2.5 ns, PRR 1 MHz. 2/ Clear and preset dominate regardless of the state of the J, K, and clock inputs. 3/ R L = 280 Ω ±5%. 4/ C L = 50 pf ±10% including jig and probe capacitance. 5/ All diodes are 1N3064 or equivalent. FIGURE 6. Clear and preset switching time test circuit and waveforms for device types 02 and

20 NOTES: 1/ t f = t r 2.5 ns, when testing f MAX IN(A) PRR = 80 MHz, 50% dc for subgroup 9, PRR = 60 MHz, 50% dc for subgroups 10 and 11 2/ t A = 10 ns, PRR 1 MHz. 3/ C L = 50 pf ±10% including jig and probe capacitance. 4/ R L = 280 Ω ±5%. 5/ All diodes are 1N3064 or equivalent. 6/ See table III for input conditions. FIGURE 7. Synchronous switching waveforms and test circuit for device types 02 and

21 NOTES: 1/ t f = t r 2.5 ns for all inputs. 2/ IN(A) has the following characteristics: t A = 10 ns, PRR 1 MHz. 3/ R L = 280 Ω ±5%, C L = 50 pf ±10% including jig and probe capacitance. 4/ All diodes are 1N3064 or equivalent. 5/ Monitor output to verify functionality with t (SETUP), t (HOLD) limit conditions as shown above. FIGURE 8. Test circuits and waveforms for device types 02 and

22 NOTES: 1/ IN(C) has the following characteristics: t C = 10 ns, t f = t r 2.5 ns, PRR 1 MHz. 2/ IN(D) has the following characteristics: t D = 10 ns, t f = t r 2.5 ns, PRR 1 MHz. 3/ R L = 280 Ω ±5%. 4/ C L = 50 pf ±10% including jig and probe capacitance. 5/ All diodes are 1N3064 or equivalent. FIGURE 9. Preset switching test circuit and waveforms for device type

23 NOTES: 1/ IN(B) has the following characteristics: t B = 10 ns, t f = t r 2.5 ns, PRR 1 MHz (when testing f MAX PRR = 80 MHz, 50% duty cycle for subgroup 9, PRR = 60 MHz, 50% duty cycle for subgroups 10 and 11). 2/ C L = 50 pf ±10% including jig and probe capacitance. 3/ R L = 280 Ω ±5%. 4/ All diodes are 1N3064 or equivalent. 5/ See table III for input conditions. FIGURE 10. Synchronous switching waveforms and test circuit for device type

24 NOTES: 1/ IN(E) has the following characteristics: t E = 10 ns, t f = t r 2.5 ns, PRR 1 MHz. 2/ t f = t r < 2.5 ns for IN(F), IN(G), and IN(H). 3/ R L = 280 Ω ±5%. 4/ C L = 50 pf ±10% including jig and probe capacitance. 5/ All diodes are 1N3064 or equivalent. 6/ Monitor output to verify functionality with t (SETUP) limit conditions. FIGURE 11. t (SETUP) waveforms and test circuit for device type

25 NOTES: 1/ All inputs: t f = t r 2.5 ns. 2/ IN(E) has the following characteristics: t E = 10 ns, PRR 1 MHz. 3/ R L = 280 Ω ±5%. 4/ C L = 50 pf ±10% including jig and probe capacitance. 5/ All diodes are 1N3064 or equivalent. 6/ t (HOLD) H = 2ns, t (HOLD) L = 2ns. 7/ See table III for input conditions. 8/ Monitor output to verify functionality with t (SETUP) limit conditions. FIGURE 12. t (HOLD) waveforms and test circuit for device type

26 NOTES: 1/ t f = t r 2.5 ns; IN(F) PRR 1 MHz. 2/ t( SETUP) = 7 ns. 3/ C L = 50 pf ±10% including jig and probe capacitance. 4/ R L = 280 Ω ±5%. 5/ All diodes are 1N3064 or equivalent. 6/ All load circuits are as shown for 6Q. 7/ See table III for input conditions. FIGURE 13. Clear waveforms and test circuit for device types 05 and

27 NOTES: 1/ t f = t r 2.5 ns; IN(A) and IN(B) 2/ IN(A) PRR = 75 MHz 50% dc, IN(B) PRR = 37.5 MHz 50% dc, for subgroup 9; IN(A) PRR = 55 MHz 50% dc, IN(B) PRR = 27.5 MHz 50% dc, for subgroups 10 and 11. 3/ C L = 50 pf ±10% including jig and probe capacitance. 4/ R L = 280 Ω ±5%. 5/ All diodes are 1N3064 or equivalent. 6/ All load circuits are as shown for 6Q. 7/ See table III for input conditions. FIGURE 14. f MAX waveforms and test circuit for device types 05 and

28 NOTES: 1/ t f = t r 2.5 ns; IN(C) PRR 1 MHz, t C = 10 ns. 2/ t( SETUP) L = 7 ns, t (HOLD) L = 5 ns, t( SETUP) H = 7 ns, t (HOLD) H = 5 ns. 3/ C L = 50 pf ±10% including jig and probe capacitance. 4/ R L = 280 Ω ±5%. 5/ All diodes are 1N3064 or equivalent. 6/ All load circuits are as shown for 6Q. 7/ See table III for input conditions. 8/ Setup and hold time functionally may be verified by separate tests from propagation delay tests by monitoring the output at specified setup and hold conditions. FIGURE 15. Synchronous switching waveforms and test circuit for device types 05 and

29 TABLE III. Group A inspection for device type Subgroup Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC 1 V OH V 5.5 V C 2/ 0.8 V -1 ma GND 4.5 V Q1 2.5 V T C = +25 C V 5.5 V C 2.0 V -1 ma Q ma 0.8 V C 5.5 V 2.0 V Q2 4-1 ma 2.0 V C 5.5 V 0.8 V Q V 2.0 V C 5.5 V -1 ma Q V 0.8 V C 5.5 V -1 ma Q ma 5.5 V C 2.0 V 5.5 V Q2 8-1 ma 5.5 V C 0.8 V 5.5 V Q 2 V OL V 5.5 V C 0.8 V 20 ma Q V 5.5 V C 2.0 V 20 ma Q ma 0.8 V C 5.5 V 2.0 V Q ma 2.0 V C 5.5 V 0.8 V Q V 2.0 V C 5.5 V 20 ma Q V 0.8 V C 5.5 V 20 ma Q ma 5.5 V C 2.0 V 5.5 V Q ma 5.5 V C 0.8 V 5.5 V Q2 V IC ma CLR ma D ma CLK ma PRE ma PRE ma CLK ma D ma CLR 2 I IL V 0.5 V GND 5.5 V D ma 26 GND 0.5 V 5.5 V D I IL V 5.5 V GND CLR GND 5.5 V 0.5 V CLR I IL3 29 GND GND 0.5 V PRE V GND GND PRE I IL V GND 0.5 V GND CLK GND 0.5 V GND 5.5 V CLK Unit See footnotes at end of device type 01.

30 TABLE III. Group A inspection for device type 01 - Continued. 30 Subgroup Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B, C, D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC I IH GND 2.7 V 5.5 V GND 5.5 V D1 50 µa V 2.7 V GND D2 50 µa T C = +25 C I IH5 35 GND 5.5 V 5.5 V D1 1 ma V 5.5 V GND D2 1 ma I IH V GND GND 5.5 V CLR µa V GND GND 2.7 V CLR µa I IH5 " V GND GND 5.5 V " " CLR 1 1 ma V GND GND 5.5 V CLR 2 1 ma I IH V 5.5 V C 2.7 V PRE µa V C 5.5 V 5.5 V PRE µa I IH V 5.5 V C 5.5 V PRE 1 1 ma V C 5.5 V 5.5 V PRE 2 1 ma I IH V 5.5 V 2.7 V GND CLK µa 46 GND 2.7 V 5.5 V 5.5 V CLK µa I IH V 5.5 V 5.5 V GND CLK 1 1 ma 48 GND 5.5 V 5.5 V 5.5 V CLK 2 1 ma I OS GND 5.5 V GND Q ma V GND GND Q1 3/ 51 GND 5.5 V GND Q 2 52 GND GND 5.5 V Q2 I CC V GND GND GND GND 5.5 V V CC GND GND 5.5 V 5.5 V GND GND V CC 50 I CEX V 5.5 V C GND 5.5 V Q1 250 µa 56 GND 5.5 V C 5.5 V 5.5 V Q V GND C 5.5 V 5.5 V Q V 5.5 V C 5.5 V GND Q 2 2 Same tests, terminal conditions, and limits as for subgroup 1, except T C = +125 C and V IC tests are omitted. V OL (max) = 0.45 V, V IL = 0.7 V. Unit 3 Same tests, terminal conditions, and limits as for subgroup 1, except T C = -55 C and V IC tests are omitted. See footnotes at end of device type 01.

31 TABLE III. Group A inspection for device type 01 - Continued. 31 Subgroup Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC 7 4/ 5/ 59 B B B B H H GND H H B B B B 4.5 V All H or L as V T C = +25 C 60 B A L L A B outputs shown 6/ " 61 A A L L A A 62 B H L L H B 63 A L L A 64 B H H B 65 A A 66 A L L A 67 A A L L A A 68 B H L L H B 69 A A 70 B B 71 B B B B 72 A L H H L A 73 B H L L H B 74 B A B H H H H B A B 75 B B A B H " " " H B A B B " " " " 76 B A L L A B " " " 77 A A " 78 A B B A " 79 A H L L H A " 80 B B " 81 A A " 82 B L H H L B " 83 A L H H L A " 84 B B H L L H B B " 85 B A H L L H A B " 8 4/ 5/ Same tests, terminal conditions, and limits as for subgroup 7, except T C = +125 C and -55 C. Unit See footnotes at end of device type 01.

32 TABLE III. Group A inspection for device type 01 - Continued. 32 Subgroup Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC 9 f MAX Fig V E IN (D) 5.0 V OUT GND 5.0 V 1Q 75 MHz T C = +25 C 7/ 4/ f MAX Fig OUT 5.0 V IN (D) E 5.0 V 2Q 75 MHz 7/ 4/ t PLH1 Fig IN (A) GND IN (B) OUT CLR 1 to ns Q 1 89 IN (B) GND IN (A) OUT PRE 1 to 90 OUT IN (B) GND IN (A) CLR 2 to Q 2 91 OUT IN (A) GND IN (B) PRE 2 to t PLH2 Fig OUT 5.0 V IN (D) IN (F) F CLK 2 to / 93 OUT F IN (D) IN (E) 5.0 V CLK 2 to Q 2 94 F IN (F) IN (D) 5.0 V OUT CLK 1 to V IN (E) F OUT CLK 1 to Q 1 t PHL V IN (E) F OUT CLK 1 to F IN (F) 5.0 V OUT CLK 1 to Q 1 98 OUT F IN (D) IN (E) 5.0 V CLK 2 to 99 OUT 5.0 V IN (D) IN (F) F CLK 2 to Q 2 t PHL3 Fig OUT IN (B) 2.7 V IN (A) CLR 2 to 16.0 Fig OUT IN (A) 2.7 V IN (B) PRE 2 to 16.0 Q1 Q2 Q2 Q1 Q1 Q2 Q2 Q 2 Unit See footnotes at end of device type 01.

33 TABLE III. Group A inspection for device type 01 - Continued. 33 Subgroup Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC 9 t PHL4 Fig GND OUT IN (A) GND IN (B) 5.0 V PRE 2 to ns T C = +25 C Q OUT IN (B) GND IN (A) CLR 2 to 10.0 t PHL3 104 IN (B) 2.7 V IN (A) OUT PRE 1 to 16.0 Q IN (A) 2.7 V IN (B) OUT CLR 1 to 16.0 t PHL4 106 IN (A) GND IN (B) OUT CLR 1 to IN (B) GND IN (A) OUT PRE 1 to 10.0 Q 1 t SETUP Fig OUT 5.0 V IN (D) IN (F) F Q2 8/ (H) 109 F IN (F) IN (D) 5.0 V OUT Q1 110 F IN (F) IN (D) 5.0 V OUT Q OUT 5.0 V IN (D) IN (F) F Q 2 t SETUP 112 OUT F IN (D) IN (E) 5.0 V Q 2 (L) V IN (E) IN (D) F OUT Q V IN (E) IN (D) F OUT Q1 115 OUT F IN (D) IN (E) 5.0 V Q2 t (HOLD) 116 OUT 5.0 V IN (D) IN (F) F Q2 (H) 117 F IN (F) IN (D) 5.0 V OUT Q1 118 F IN (F) IN (D) 5.0 V OUT Q OUT 5.0 V IN (D) IN (F) F Q 2 t (HOLD) 120 OUT F IN (D) IN (E) 5.0 V Q 2 (L) V IN (E) IN (D) F OUT Q V IN (E) IN (D) F OUT Q1 123 OUT F IN (D) IN (E) 5.0 V Q2 Q2 Q1 Q1 Unit See footnotes at end of device type 01.

34 TABLE III. Group A inspection for device type 01 - Continued. Subgroup 10 T C = +125 C Symbol MIL- STD-883 method Cases X, 2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLR 1 D1 CLK 1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 CLK 2 D2 CLR 2 V CC f MAX Fig , MHz t PLH1 Fig ns Unit t PLH2 Fig. 5 8/ Same tests and terminal conditions as subgroup 9, except T C = +125 C and limits are as shown t PHL2 Fig. 5 8/ t PHL3 Fig t PHL4 Fig " 12.5 " 34 t SETUP (H) t SETUP (L) t (HOLD) (H) t (HOLD) (L) Fig / Same tests, terminal conditions, and limits as for subgroup 10, except T C = -55 C. 1/ Cases X and 2 terminals not designated are NC. 2/ C = Normal clock pulse. D = Momentary connection: 5.0 V to GND to 5.0 V (for subgroup 9, 10, 11. D occurs prior to their input pulses). E = Data input connected to Q output. F = Normal input conditioning is 5.0 V, however, momentary logic 0 may be applied for synchronizing test equipment for preconditioning the device. 3/ For circuit B, I OS(max) is 110 ma. 4/ Only a summary of attributes data is required. 5/ Inputs: A = 2.4 V minimum, B = 0.4 V. 6/ Outputs: H 1.5 V, L 1.5 V. 7/ f MAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency. 8/ SETUP and HOLD time functionality may be verified by separate tests from propagation delay tests, by monitoring the output at specified SETUP and HOLD conditions (see fig. 5).

35 TABLE III. Group A inspection for device type Subgroup Symbol Case X, / MIL- Cases Test limits STD-883 E, F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 1 V OH C 2/ 0.8 V 2.0 V 2.0 V -1 ma GND 2.0 V 4.5 V Q1 2.5 V T C =25 C 2-1 ma 2.0 V 2.0 V 0.8 V C 2.0 V Q2 3 C 2.0 V 0.8 V 2.0 V -1 ma 2.0 V Q ma 2.0 V 0.8 V 2.0 V C 2.0 V Q V 5.5 V 5.5 V 0.8 V -1 ma 2.0 V Q1 6-1 ma 0.8 V 5.5 V 5.5 V 5.5 V 2.0 V Q V 5.5 V 5.5 V 2.0 V -1 ma 0.8 V Q ma 2.0 V 5.5 V 5.5 V 5.5 V 0.8 V Q 2 V OL C 0.8 V 2.0 V 2.0 V 20 ma 2.0 V Q ma 2.0 V 2.0 V 0.8 V C 2.0 V Q 2 11 C 2.0 V 0.8 V 2.0 V 20 ma 2.0 V Q ma 2.0 V 0.8 V 2.0 V C 2.0 V Q V 5.5 V 5.5 V 0.8 V 20 ma 2.0 V Q ma 0.8 V 5.5 V 5.5 V 5.5 V 2.0 V Q V 5.5 V 5.5 V 2.0 V 20 ma 0.8 V Q ma 2.0 V 5.5 V 5.5 V 5.5 V 0.8 V Q2 V IC ma CLK ma K ma J ma PRE ma PRE ma J ma K ma CLK ma CLR ma CLR 1 I IL V 0.5 V 5.5 V D 5.5 V 5.5 V K ma 28 D 5.5 V 0.5 V 5.5 V 5.5 V K V 5.5 V 0.5 V 5.5 V D J V 0.5 V 5.5 V 5.5 V D J2 I IL V 5.5 V 5.5 V 5.5 V 0.5 V CLR I IL V 5.5 V 5.5 V 5.5 V 0.5 V CLR Unit See footnotes at end of device type 02.

36 TABLE III. Group A inspection for device type Case X, / MIL- Cases Test limits Subgroup Symbol STD-883 E,F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 1 I IL V 5.5 V 5.5 V 0.5 V GND 5.5 V 5.5 V PRE ma T C = +25 C I IL V 5.5 V 5.5 V 5.5 V 5.5 V PRE I IL V 5.5 V 5.5 V 5.5 V D CLK 1-2 3/ -4 I IL V 5.5 V 5.5 V 0.5 V D CLK 2-2 3/ -4 I IH GND 2.7 V 5.5 V GND 5.5 V K1 50 µa 38 GND 5.5 V 2.7 V GND 5.5 V K2 39 GND 5.5 V 2.7 V 5.5 V GND J V 2.7 V 5.5 V GND GND J2 I IH5 41 GND 5.5 V 5.5 V GND 5.5 V K1 1 ma 42 GND 5.5 V 5.5 V GND 5.5 V K2 43 GND 5.5 V 5.5 V 5.5 V GND J V 5.5 V 5.5 V GND GND J2 I IH2 " 45 GND 5.5 V GND D " 2.7 V " CLR µa I IH2 46 D GND 5.5 V GND 2.7 V CLR µa I IH5 47 GND 5.5 V GND D 5.5 V CLR 1 1 ma I IH5 48 D GND 5.5 V GND 5.5 V CLR 2 1 ma I IH3 49 GND GND 5.5 V 2.7 V D PRE µa I IH V 5.5 V GND GND D PRE µa I IH5 51 GND GND 5.5 V 5.5 V D PRE 1 1 ma I IH V 5.5 V GND GND D PRE 2 1 ma I IH V GND GND GND GND CLK µa I IH4 54 GND GND GND 2.7 V GND CLK µa I IH V GND GND GND GND CLK 1 1 ma I IH5 56 GND GND GND 5.5 V GND CLK 2 1 I OS V 5.5 V 5.5 V GND GND 5.5 V Q GND GND 5.5 V 5.5 V 5.5 V 5.5 V Q2 4/ V 5.5 V 5.5 V 5.5 V GND GND Q 1 60 GND 5.5 V 5.5 V 5.5 V 5.5 V GND Q 2 I CC V 5.5 V 5.5 V GND GND 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V V CC 50 I CC V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V GND GND V CC 50 Unit See footnotes at end of device type 02.

37 TABLE III. Group A inspection for device type 02 - Continued. Subgroup Symbol Case X, / MIL- Cases Test limits STD-883 E,F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 1 I CEX 63 C GND 5.5 V GND 5.5 V GND 5.5 V 5.5 V Q1 250 µa T C = +25 C V GND 5.5 V GND C 5.5 V Q2 65 C 5.5 V GND 5.5 V 5.5 V GND Q V 5.5 V GND 5.5 V C GND Q 2 2 Same tests, terminal conditions, and limits as for subgroup 1, except T C = +125 C and V IC tests are omitted. V OL (max) = 0.45 V, V IL = 0.7 V. Unit 37 3 Same tests, terminal conditions, and limits as for subgroup 1, except T C = -55 C and V IC tests are omitted. 7 5/ 6/ 67 B B A A L H H GND L A A B B B B 4.5 V All H or L 7/ V T C = +25 C 68 A A outputs as shown 69 B B See footnotes at end of device type B A B B H L L H B B A B A A 71 A A 72 B B 73 B A L H H L A B B B 74 A A 75 A A 76 B B 77 B H L L H B 78 A A 79 A A 80 B B 81 B " A " L H H " L " A " B B B " " " " 82 B B A A " " 83 A A 84 B H L L H B 85 A B B B B A 86 A A 87 A A 88 B L H H L B 89 A A B H H B A A B B 90 B A L L A B B B 91 B B A A 92 A A A A

38 TABLE III. Group A inspection for device type 02 - Continued. 38 Case X, / MIL- Cases Test limits Unit Subgroup Symbol STD-883 E,F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 7 5/ 6/ 93 B A A A H L L GND H A A A B A A 4.5 V All H or L 7/ V T C = +25 C 94 A H L L H A outputs as shown 95 B L H H L B 8 5/ 6/ Same tests, terminal conditions and limits as for subgroup 7, except T C = +125 C and -55 C. 9 f MAX Fig IN (A) 2.7 V 2.7 V 2.7 V OUT GND 2.7 V 5.0 V Q1 80 MHz T C = +25 C 8/ 97 OUT 2.7 V 2.7 V 2.7 V IN (A) 2.7 V Q2 98 IN (A) 2.7 V 2.7 V 2.7 V OUT 2.7 V Q 1 99 OUT 2.7 V 2.7 V 2.7 V IN (A) 2.7 V Q 2 t PLH1 Fig V 2.7 V 2.7 V IN (C) OUT IN (B) PRE 1 to Q ns 101 OUT IN (C) 2.7 V 2.7 V 2.7 V IN (B) PRE 2 to Q V 2.7 V 2.7 V IN (B) OUT IN (C) CLR 1 to Q OUT IN (B) 2.7 V 2.7 V 2.7 V IN (C) CLR 2 to Q 2 t PLH2 Fig IN (A) 2.7 V 2.7 V 2.7 V OUT E CLK 1 to Q OUT 2.7 V 2.7 V 2.7 V IN (A) E CLK 2 to Q IN (A) 2.7 V 2.7 V E OUT 2.7 V CLK 1 to Q1 107 OUT E 2.7 V 2.7 V IN (A) 2.7 V CLK 2 to Q2 t PHL3 Fig V 2.7 V 2.7 V IN (C) OUT IN (B) PRE 1 to Q OUT IN (C) 2.7 V 2.7 V 2.7 V IN (B) PRE 2 to Q V 2.7 V 2.7 V IN (B) OUT IN (C) CLR 1 to Q1 111 OUT IN (B) 2.7 V 2.7 V 2.7 V IN (C) CLR 2 to Q2 t PHL2 Fig IN (A) 2.7 V 2.7 V 2.7 V OUT E CLK 1 to Q OUT 2.7 V 2.7 V 2.7 V IN (A) E CLK 2 to Q IN (A) 2.7 V 2.7 V E OUT 2.7 V CLK 1 to Q1 115 OUT E 2.7 V 2.7 V IN (A) 2.7 V CLK 2 to Q2 t SETUP Fig IN (A) 2.7 V IN (D) E OUT 2.7 V Q1 9/ (L) 117 OUT E IN (D) 2.7 V IN (A) 2.7 V Q2 118 IN (A) IN (D) 2.7 V 2.7 V OUT E Q OUT 2.7 V 2.7 V IN (D) IN (A) E Q 2 t SETUP 120 IN (A) 2.7 V IN (E) 2.7 V OUT E Q1 (H) 121 OUT 2.7 V IN (E) 2.7 V IN (A) E Q2 122 IN (A) IN (E) 2.7 V E OUT 2.7 V Q OUT E 2.7 V IN (E) IN (A) 2.7 V Q 2 See footnotes at end of device type 02.

39 TABLE III. Group A inspection for device type 02 - Continued. 39 Subgroup Case X, / MIL- Cases Test limits Unit Symbol STD-883 E,F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 9 t HOLD Fig IN (A) 2.7 V IN (F) E OUT GND 2.7 V 5.0 V Q1 9/ T C = +25 C (L) 125 OUT E IN (F) 2.7 V IN (A) 2.7 V Q2 126 IN (A) IN (F) 2.7 V 2.7 V OUT E Q OUT 2.7 V 2.7 V IN (F) IN (A) E Q 2 t HOLD 128 IN (A) 2.7 V IN (G) 2.7 V OUT E Q1 (H) 129 OUT 2.7 V IN (G) 2.7 V IN (A) E Q2 130 IN (A) IN (G) 2.7 V E OUT 2.7 V Q OUT E 2.7 V IN (G) IN (A) 2.7 V Q 2 10 f MAX Fig MHz T C = +125 C 8/ t PLH1 Fig ns t PLH2 Fig t PHL3 Fig Same tests and terminal conditions as for subgroup 9, except T C = +125 C and limits are as shown. t PHL2 Fig t SETUP Fig / (L)

40 TABLE III. Group A inspection for device type 02 - Continued. Subgroup Case X, / MIL- Cases Test limits Unit Symbol STD-883 E,F method Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 Q 2 GND Q2 PRE 2 J2 K2 CLK 2 CLR 2 CLR 1 VCC terminal Min Max 10 t SETUP Fig / T C = +125 C (H) t HOLD Same tests and terminal conditions as for subgroup 9, except T C = +125 C and limits are as shown. (L) t HOLD (H) 11 Same tests, terminal conditions, and limits as for subgroup 10, except T C = -55 C. 40 1/ Cases X and 2 terminals not designated are NC. 2/ C = Normal clock pulse. D = V ---0 V E = Normal input conditioning is 5.0 V, however, momentary logic 0 may be applied to input for synchronizing test equipment and preconditioning device under test. 3/ For circuit B, I IL4 (min) is -0.7 ma. 4/ For circuit B, I OS(max) is 110 ma. 5/ Only a summary of attributes data is required. 6/ Inputs: A = 2.4 minimum, 8 = 0.4 V. 7/ Outputs: L 1.5 V, H 1.5 V. 8/ f MAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency. 9/ Setup and hold time functionally may be verified by separate tests from propagation delay tests by monitoring the outputs at specified setup and hold conditions.

41 TABLE III. Group A inspection for device type Subgroup Symbol MIL- STD-883 method Cases X,2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK 2 V CC 1 V OH C 2/ 0.8 V 2.0 V 2.0 V -1 ma GND 4.5 V Q1 2.5 V T C = +25 C 2-1 ma 2.0 V 2.0 V 0.8 V C Q2 3 C 2.0 V 0.8 V 2.0 V -1 ma Q ma 2.0 V 0.8 V 2.0 V C Q V -1 ma Q1 6-1 ma 0.8 V Q2 V OL C 0.8 V 2.0 V 2.0 V 20 ma Q ma 2.0 V 2.0 V 0.8 V C Q 2 9 C 2.0 V 0.8 V 2.0 V 20 ma Q ma 2.0 V 0.8 V 2.0 V C Q V 20 ma Q ma 0.8 V Q 2 V IC ma CLK ma K ma J ma PRE ma PRE ma J ma K ma CLK 2 I IL V 0.5 V GND D 5.5 V K ma 22 D GND 0.5 V 5.5 V K2 23 D 5.5 V 0.5 V 5.5 V J V 0.5 V 5.5 V D J2 I IL V 5.5 V 5.5 V 0.5 V PRE I IL V 5.5 V 5.5 V 5.5 V PRE I IL V 5.5 V 5.5 V D CLK / -4.0 I IL4 28 D 5.5 V 5.5 V 0.5 V CLK / -4.0 I IH GND 2.7 V GND GND K1 50 µa 30 GND GND 2.7 V GND K2 31 C GND 2.7 V 5.5 V J V 2.7 V GND C J2 Unit See footnotes at end of device type 03.

42 TABLE III. Group A inspection for device type 03 - Continued. 42 Subgroup Symbol MIL- STD-883 method Cases X,2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK 2 V CC 1 I IH V GND GND GND GND 5.5 V CLK µa T C = +25 C I IH4 34 GND GND GND 2.7 V CLK 2 I IH3 35 GND GND 5.5 V 2.7 V F 7/ PRE 1 I IH3 36 F 2.7 V 5.5 V GND GND PRE 2 I IH5 " 37 GND 5.5 V GND GND " " K1 1.0 ma 38 GND GND 5.5 V GND K2 39 C GND 5.5 V 5.5 V J V 5.5 V GND C J V GND GND GND CLK 1 42 GND GND GND 5.5 V CLK 2 43 GND GND 5.5 V 5.5 V F PRE 1 44 F 5.5 V 5.5 V GND GND PRE 2 I OS GND GND Q / 46 GND GND Q C 5.5 V GND 5.5 V GND 2.25 V Q V GND 5.5 V GND 5.5 V C Q I CC GND GND GND GND GND GND GND GND V CC 50 I CC C 5.5 V GND 5.5 V 5.5 V GND 5.5 V C V CC 50 I CEX 51 C GND 5.5 V GND 5.5 V Q1 250 µa V GND 5.5 V GND C Q2 53 C 5.5 V GND 5.5 V GND 5.5 V Q V GND 5.5 V GND 5.5 V C Q 2 2 Same tests, terminal conditions, and limits as for subgroup 1, except T C = +125 C and V IC tests are omitted. V OL (max) = 0.45 V, V IL = 0.7 V. 3 Same tests, terminal conditions, and limits as for subgroup 1, except T C = -55 C and V IC tests are omitted. 7 5/ 6/ 55 B A B B H L GND L H B B B B 4.5 V All H or L 7/ V T C = +25 C 56 A outputs as shown 57 B 58 B A 59 A 60 B L H 61 B B A 62 A 63 B H L 64 B B B H L A Unit See footnotes at end of device type 03.

43 TABLE III. Group A inspection for device type 03 - Continued. 43 Subgroup Symbol MIL- STD-883 method Cases X,2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK 2 V CC 7 5/ 6/ 65 B B B B H L GND L H A B A B 4.5 V All H or L 7/ V T C = +25 C 66 L H A outputs as shown 67 H L B 68 A B B 69 A 70 L H B 71 B B 72 A A 73 A A 74 B B 75 B A A A A B 76 A A 77 B L H H L B 78 B B B B B B 79 A A 80 B B 81 B A A A A A B 82 A A 83 B H L L H B 8 5/ 6/ Same tests, terminal conditions and limits as for subgroup 7, except T C = +125 C and -55 C. 9 f MAX Fig IN (B) 2.7 V 2.7 V 2.7 V OUT GND 5.0 V Q1 80 MHz T C = +25 C 8/ 85 OUT 2.7 V 2.7 V 2.7 V IN (B) Q2 86 IN (B) 2.7 V 2.7 V 2.7 V OUT Q 1 87 OUT 2.7 V 2.7 V 2.7 V IN (B) Q 2 t PLH1 Fig IN (C) 2.7 V GND IN (D) OUT PRE 1 to Q ns t PLH1 Fig OUT IN (D) GND 2.7 V IN (C) PRE 2 to Q2 t PLH2 Fig IN (B) 2.7 V 2.7 V E OUT CLK 1 to Q1 t PLH2 Fig OUT E 2.7 V 2.7 V IN (B) CLK 2 to Q2 Unit See footnotes at end of device type 03.

44 TABLE III. Group A inspection for device type 03 - Continued. 44 Subgroup Symbol MIL- STD-883 method Cases X,2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK 2 V CC 9 t PLH3 Fig IN (B) 2.7 V 2.7 V E OUT GND 5.0 V CLK 1 to Q ns T C = +25 C t PLH3 Fig OUT E 2.7 V 2.7 V IN (B) CLK 2 to Q 2 t PHL1 Fig IN (C) 2.7 V GND IN (D) OUT PRE 1 to Q 1 t PHL1 Fig OUT IN (D) GND 2.7 V IN (C) PRE 2 to Q 2 t PHL2 Fig IN (B) 2.7 V 2.7 V E OUT CLK 1 to Q 1 t PHL2 97 OUT E 2.7 V 2.7 V IN (B) CLK 2 to Q 2 t PHL3 98 IN (B) 2.7 V 2.7 V E OUT CLK 1 to Q1 t PHL3 99 OUT E 2.7 V 2.7 V IN (B) CLK 2 to Q2 t SET Fig IN (E) 2.7 V IN (F) E OUT Q1 9/ (H) 101 OUT E IN (F) 2.7 V IN (E) Q2 102 IN (E) IN (F) 2.7 V 2.7 V OUT Q1 103 OUT 2.7 V 2.7 V IN (F) IN (E) Q2 t SET 104 IN (E) 2.7 V IN (G) E OUT Q1 (L) 105 OUT E IN (G) 2.7 V IN (E) Q2 106 IN (E) IN (H) 2.7 V E OUT Q1 107 OUT 2.7 V 2.7 V IN (H) IN (E) Q2 t HOLD Fig IN (E) 2.7 V IN (J) E OUT Q1 (H) 109 OUT E IN (J) 2.7 V IN (E) Q2 110 IN (E) IN (K) 2.7 V E OUT Q1 111 OUT E 2.7 V IN (K) IN (E) Q2 t HOLD 112 IN (E) 2.7 V IN (L) E OUT Q1 (L) 113 OUT E IN (L) 2.7 V IN (E) Q2 114 IN (E) IN (L) 2.7 V 2.7 V OUT Q1 115 OUT 2.7 V 2.7 V IN (L) IN (E) Q2 Unit See footnotes at end of device type 03.

45 TABLE III. Group A inspection for device type 03 - Continued. Subgroup 10 T C = +125 C Symbol f MAX 8/ MIL- STD-883 method Cases X,2 1/ Cases A, B,C,D Test limits terminal Min Max Test no. CLK 1 K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK 2 V CC Fig MHz t PLH1 Fig ns Unit 45 t PLH2 Fig t PLH3 Fig t PHL1 Fig t PHL2 Fig Same tests and terminal conditions as subgroup 9, except T C = +125 C and limits are as shown. t PHL3 Fig t SET(H) Fig / t SET(L) Fig t (HOLD) (L) Fig t (HOLD) (L) Fig Same tests, terminal conditions, and limits as for subgroup 10, except T C = -55 C. 1/ Cases X and 2 terminals not designated are NC. 2/ C = Normal clock pulse. D = Momentary connection: 5.0 V to GND to 5.0 V before measurement is made (for subgroups 9, 10, 11, D occurs prior to other input pulses). E = Normal input conditioning is 2.7 V, however, momentary logic 0 may be applied to input for synchronizing test equipment and for preconditioning the device. F = Momentary GND, then open. 3/ For circuit B, I IL4 (min) is -0.7 ma. 4/ For circuit B, I OS(max) is 110 ma. 5/ Only a summary of attributes data is required. 6/ Inputs: A = 2.4 V minimum, B = 0.4 V. 7/ Outputs: H 1.5 V, L 1.5 V. 8/ f MAX, minimum limit specified is the frequency of the input pulse. The output frequency shall be one-half of the input frequency. 9/ Monitor output to verify functionally with t (SET) and t (HOLD) limit conditions as shown on figures 11 and 12.

46 TABLE III. Group A inspection for device type Subgroup Symbol MIL- STD-883 method Cases A, B,C,D Test limits terminal Min Max Test no. CLR K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK V CC 1 V OH V 0.8 V 2.0 V 2.0 V -1 ma GND C 1/ 4.5 V Q1 2.5 V T C = +25 C 2-1 ma 2.0 V 2.0 V 0.8 V Q V 0.8 V 2.0 V -1 ma Q ma 2.0 V 0.8 V 2.0 V Q V -1 ma 5.5 V Q1 6-1 ma 0.8 V Q V 2.0 V -1 ma Q V -1 ma 2.0 V Q 2 V OL V 0.8 V 2.0 V 2.0 V 20 ma C Q ma 2.0 V 2.0 V 0.8 V Q V 0.8 V 2.0 V 20 ma Q ma 2.0 V 0.8 V 2.0 V Q V 20 ma 5.5 V Q ma 0.8 V Q V 2.0 V 20 ma Q V 20 ma 2.0 V Q2 V IC ma CLR ma K ma J ma PRE ma PRE ma J ma K ma CLK I IL V 0.5 V GND D 5.5 V 5.5 V K ma V D GND 0.5 V K2 27 D GND 0.5 V 5.5 V J1 28 D 5.5 V 0.5 V 5.5 V J2 I IL V 5.5 V 5.5 V 0.5 V PRE V 0.5 V 5.5 V 5.5 V PRE I IL V 5.5 V 5.5 V 5.5 V 5.5 V CLR I IL4 32 D 5.5 V 5.5 V 5.5 V 5.5 V 0.5 V CLK Unit See footnotes at end of device type 04.

47 TABLE III. Group A inspection for device type Subgroup Symbol MIL- STD-883 method Cases A, B,C,D Test limits terminal Min Max Test no. CLR K1 J1 PRE 1 Q1 Q 1 GND Q 2 Q2 PRE 2 J2 K2 CLK V CC 1 I IH GND 2.7 V GND GND GND GND 5.5 V K1 50 µa T C = +25 C 34 GND GND 2.7 V K2 35 GND 2.7 V GND J1 36 GND 2.7 V GND J2 I IH3 37 GND GND 2.7 V PRE V GND GND PRE I IH V GND GND GND GND CLR 200 I IH4 40 GND GND GND GND GND 2.7 V CLK 200 I IH5 " 41 GND 5.5 V GND GND " GND " K1 1.0 ma 42 GND GND 5.5 V K2 43 GND 5.5 V GND J1 44 GND 5.5 V GND J2 45 GND GND 5.5 V PRE V GND GND PRE V GND GND GND GND CLR 48 GND GND GND GND GND 5.5 V CLK I OS V GND GND Q V GND GND Q2 2/ 51 GND 5.5 V GND Q 1 52 GND GND 5.5 V Q 2 I CC V GND GND GND V CC GND 5.5 V 5.5 V GND V CC 50 I CEX V GND 5.5 V 5.5 V 5.5 V C Q1 250 µa V 5.5 V 5.5 V GND Q V GND 5.5 V 5.5 V Q V 5.5 V GND 5.5 V Q 2 2 Same tests, terminal conditions, and limits as for subgroup 1, except T C = +125 C and V IC tests are omitted. V OL (max) = 0.45 V, V IL = 0.7 V. 3 Same tests, terminal conditions, and limits as for subgroup 1, except T C = -55 C and V IC tests are omitted. Unit See footnotes at end of device type 04.