Center for Reliable Computing TECHNICAL NOTE. Some Faults Need an IDDQ Test

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1 Center for Reliable Computing TCHNICAL NOT ome Faults Need an IQ Test amy R. Makar and dward J. McCluskey 96-1 Center for Reliable Computing Gates Room # 235, MC 9020 Gates Building 2A (CL TN ) Computer ystems Laboratory epartments of lectrical ngineering and Computer cience August 1996 tanford University tanford, California Abstract: Fault imulation results of different implementations of 2-1 multiplexers and -latches are presented. These results show that some faults can only be detected by I ddq test. imulation results also show that the ÒimportanceÓ of I ddq as a test method can vary considerably with implementation. Funding: This work was supported in part by the Ballistic Missile efense Organization, Innovative cience and Technology (BMO/IT) irectorate and administered through the epartment of the Navy, Office of Naval Research under Grant No. N J-1782, in part by the Advanced Research Projects Agency under Contract No. ABT63-94-C-0045, and in part by the National cience Foundation under Grant No. MIP It was also funded in part by Cirrus Logic. Copyright 1996 by the Center for Reliable Computing, tanford University. All rights reserved, including the right to reproduce this report, or portions thereof, in any form.

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3 Introduction IQ testing has been used in the last several years as a technique to improve quality of CMO chips [Maxwell 92] [Wiscombe 93], and [awada 92]. In CMO, there are some faults whose presence does not change the functionality of the circuit under test. ome of these cannot be detected (and thus are untestable or redundant). Others that cannot be detected by a Boolean voltage test (since the circuit functionality is correct) can, nevertheless, be discovered by a current test or a delay test [Ma 95] [Hawkins 94]. There are special difficulties in using IQ testing: determining the IQ threshold, ensuring that the design adheres to IQ design rules (so that IQ current of fault-free circuits is low enough to be differentiated from IQ of faulty circuits), and the increase in fault-free IQ values with the shrinking of circuit technology. In this work we examine different implementations of the same circuit to determine how ÒimportantÓ IQ is for each of the implementations. Importance of IQ for a circuit implementation is measured by the percentage of faults that are only detected by an IQ test. We show that regardless of the implementation, some faults can only be detected by an IQ test. However, some implementations have a smaller percentage of faults that can only be detected by an IQ test. In other words, if we cannot use an IQ test, then we will miss fewer faults with such implementations. In this paper we analyze three different implementations of 2-to-1 multiplexers and three different implementations of -latches. Multiplexers and -latches are interesting because there are many different ways of implementing them, and are common in many designs. Our analysis shows that the percentage of faults that require IQ for detection vary considerably with different implementations. In our analysis we perform fault simulation using the CrossCheck fault models, [ucar 89] and [Chandra 93]. The fault models comprise shorted interconnects (TI), open interconnects (OPI), short-to-power (TP), short-to-ground (TG), transistor stuck-on (ON), and transistor stuck-open (OP). In the simulations, faults are injected by modifying a copy of the circuit description. The faulty circuits are simulated using Hpice [Kielkowski 94]. The current limit for IQ testing is often determined experimentally, by plotting the values of many good and bad dies, and selecting an appropriate threshold that would detect as many faulty circuits as possible without discarding many good ones [Hawkins 89] and [Perry 92]. For our simulations, the current limit is determined by first measuring the maximum observed current for the fault-free circuit and for each faulty circuit (circuit with fault injected). An appropriate threshold is selected based on these numbers. 1

4 Multiplexer A 2-to-1 multiplexer is shown in Fig. 1. Three different 2-to-1 multiplexer implementations were simulated. These are shown in Fig. 2. Two different tests were used in the simulations: an exhaustive test, which contains 8 patterns (XH), and a test that applies all single bit transitions (TBT or ingle Transition Bit xhaustive Test), which contains 25 patterns. The tests are shown in Table 1. ach test was run twice, once with a cycle time (cycle time here is defined to be the time between the application of inputs) of 100 ns, and once with a cycle time of 10 ms. Outputs were measured just before applying the next input. The 100 ns cycle time is a typical test time for a boolean test, and the 10 ms cycle time is needed to allow I to settle to its quiescent value. The results of both tests are shown in Table 2 and 3. In these tables several numbers are reported: the total number of faults injected, the number of faults detected when both a boolean and an IQ test are done, the number of faults detected when only a boolean test is done, the number of faults detected when only an IQ test is done, and the number of faults detected by an IQ test but missed by a Boolean test. These tables show that a significant percentage of faults are missed if no IQ test is done. The AOI implementation with TBT test had the fewest faults detected by IQ missed by boolean test. MUX G1 1 1 Z Figure 1 2-to-1 Multiplexer. Table 1a xhaustive Test For Multiplexer Z Table 1b ingle Transition Bit xhaustive Test for Multiplexer Z

5 N1 M8 N M8 N1 N2 Z 1 N 0 N2 N4 N3 Z (a) Transmission Gate Implementation (b) AOI Implementation 0 0N N 0 M8 Z 2 N1 0N N2 N3 Impl. (c) NAN/NAN Implementation Figure 2 Multiplexer Implementations. Table 2 Number of Faults for XH Test on 2-1 Multiplexers. Total Injected Boolean and IQ Boolean Alone IQ Alone Undetectable IQ not by Boolean a (31.9%) b (23.5%) c (21.4%) Impl. Table 3 Number of Faults for TBT on 2-1 Multiplexers. Total Injected Boolean and IQ Boolean Alone IQ Alone Undetectable IQ not by Boolean a (31.9%) b (15.7%) c (17.3%) 3

6 -Latch The -latch circuit is shown in Fig. 3. Three different -latch implementations were simulated. These are shown in Fig. 4. The test used here, shown in Table 4, is a checking experiment from [Makar 95]. A checking experiment guarantees the detection of all faults that do not increase the number of states in the circuit. In [Makar 95], we only presented and analyzed results for the first implementation, and showed that the test detects all detectable faults in the circuit. The other two implementations use the second and third multiplexer implementations 1 C1 Q Figure 3 -Latch Circuit. N M8 N1 N2 Q 1 N N1 M8 N4 Q 0 N2 N3 (a) Transmission Gate Implementation (b) AOI Implementation N N M8 Q 2 N1 N N2 N3 (c) NAN/NAN Implementation Figure 4 -Latch Implementations 4

7 described earlier. The output of the multiplexer is connected to the input and renamed Q, the input is renamed (for enable), and the input is renamed. The results of the simulations are shown in Table 5. As with the multiplexers, Table 5 shows that a large number of faults are missed if no IQ test is done. The AOI implementation has the lowest percentage of faults that are detected only by IQ measurement. Impl. Table 4 Checking xperiment for -Latch Q Table 5 Number of Faults for -Latch Checking xperiment. Total Injected Boolean and IQ Boolean Alone IQ Alone Undetectable IQ not by Boolean a (28.4%) b (6.5%) c (9.1%) Conclusion imulation results presented in this technical note show that a large number of faults can be missed if no I ddq test is performed. ven though these faults may not affect the functionality of the circuit, they may have an impact on the timing. Acknowledgments The authors would like to thank Jonathan Chang and iyad Ma for their valuable comments. This work was supported in part by the Ballistic Missile efense Organization, Innovative cience and Technology (BMO/IT) irectorate and administered through the epartment of the Navy, Office of Naval Research under Grant No. N J-1782, in part by the Advanced Research Projects Agency under Contract No. ABT63-94-C-0045, and in part by the National cience Foundation under Grant No. MIP It was also funded in part by Cirrus Logic. References [Chandra 93] Chandra,., et. al., ÒCrossCheck: An Innovative Testability olution,ó I esign and Test of Computers, Vol. 10, No. 2, pp , June, [Hawkins 89] Hawkins, CF., ÒQuiescent Power upply Current Measurement for CMO IC efect etection,ó I Trans. on Industrial lectronics, pp , May,

8 [Hawkins 94] Hawkins, CF., et. al, Òefect Classes - An Overdue Paradigm for CMO IC Testing,Ó Proceeding ITC, pp , [Kielkowski 94] Kielkowski, R., Inside PIC Overcoming the Obstacles of Circuit imulation, McGraw Hill, UA, [Ma 95] Ma,., P. Franco and.j. McCluskey, ÒAn xperimental Chip to valuated Test Techniques, xperimental Results,Ó Proceedings ITC, pp , [Makar 95] Makar,.R. and.j. McCluskey, ÒFunctional Tests for can Chain Latches,Ó Proceedings ITC, pp , [Maxwell 92] Maxwell, P.C. and R.C. Aitken, V. Johansen and I. Chiang, ÒThe ffectiveness of IQ, Functional and can Tests: How Many Fault Coverages do We Need?,Ó Proceedings ITC, pp , [Perry 92] Perry, R., ÒIQ Testing in CMO igital AICs - Putting It All Together,Ó Proceedings ITC, pp , [awada 92] awada, K. and. Kayano ÒAn valuation of IQ Versus Conventional Testing for CMO ea-of-gates ICÕs,Ó Proceedings ITC, pp , [ucar 89] ucar, H., ÒHigh Performance Test Generation for Accurate efect Models in CMO Gate Array Technology,Ó ICCA, pp , [Wiscombe 93] Wiscombe, P.C., ÒA Comparison of tuck-at Fault Coverage and IQ Testing on efect Levels,Ó Proceedings ITC, pp ,