8-Ch/Dual 4-Ch High-Performance CMOS Analog Multiplexers

Transcription

1 8-Ch/ual 4-Ch High-Performance CMOS Analog Multiplexers Low On-Resistance r S(on) : Low Charge Injection Q: pc Fast Transition Time t TRANS : 6 ns Low Power I SUPPLY : A Single Supply Capability 44-V Supply Max Rating TTL Compatible Logic Reduced Switching Errors Reduced Glitching Improved ata Throughput Reduced Power Consumption Increased Ruggedness Wide Supply Ranges ( 5 V to V) ata Acquisition Systems Audio Signal Routing ATE Systems Battery Powered Systems High Rel Systems Single Supply Systems Medical Instrumentation The G48 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (,, ). The G49 is a dual 4-channel differential analog multiplexer designed to connect one of four differential inputs to a common dual output as determined by its 2-bit binary address (, ). Break-before-make switching action protects against momentary crosstalk between adjacent channels. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable () function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (A x ) and enable () are TTL compatible over the full specified operating temperature range. Applications for the G48/49 include high speed data acquisition, audio signal switching and routing, ATE systems, and avionics. High performance and low power dissipation make them ideal for battery operated and remote instrumentation applications. esigned in the 44-V silicon-gate CMOS process, the absolute maximum voltage rating is extended to 44 V. Additionally, single supply operation is also allowed. An epitaxial layer prevents latchup. For additional information please see Technical Article TA (FaxBack Number 76). G48 ual-in-line SOIC and TSSOP G49 ual-in-line SOIC and TSSOP ecoders/rivers 5 2 ecoders/rivers 5 GN V GN 3 4 V 3 4 S 4 3 S a 4 3 S b S 2 S S 2a 5 2 S 2b S 3 6 S 6 S 3a 6 S 3b S 4 7 S 7 S 4a 7 S 4b 8 9 S 8 a 8 9 b Top View Top View 5-

2 On Switch X X X None On Switch X X None Logic = V AL.8 V Logic = V AH 2.4 V X = on t Care Temp Range Package Part Number Temp Range Package Part Number 6-Pin Plastic IP G48J 6-Pin Plastic IP G49J 4 to 85 C 6-Pin SOIC G48Y 6-Pin TSSOP G48Q G48AK 4 to 85 C 6-Pin SOIC G49Y 6-Pin TSSOP G49Q G49AK 55 to 25 C 6-Pin CerIP G48AK/ MEA 55 to 25 C 6-Pin CerIP G49AK/ MEA LCC-* M2A LCC-* M2A *Block iagram and Pin Configuration not shown. Voltage Referenced to V V GN V igital Inputs a, V S, V (V ) 2 V to () +2 V or ma, whichever occurs first Current (Any Terminal) ma Peak Current, S or (Pulsed at ms, % uty Cycle Max) ma Storage Temperature (AK Suffix) to 5 C (J, Y Suffix) to 25 C Power issipation (Package) b 6-Pin Plastic IP c mw 6-Pin Narrow SOIC and TSSOP d mw 6-Pin CerIP e mw LCC- f mw Notes a. Signals on S X, X or IN X exceeding or V will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. erate 6 mw/ C above 75 C. d. erate 7.6 mw/ C above 75 C. e. erate 2 mw/ C above 75 C. f. erate mw/ C above 75 C. 5-2

3 SPECIFICATIONS a Parameter Analog Switch Symbol Test Conditions Unless Otherwise Specified A Suffix 55 to 25 C Suffix 4 to 85 C = 5 V, V = 5 V V AL =.8 V, V AH = 2.4 V f Temp b Typ c Min d Max d Min d Max d Unit Analog Signal Range e V ANALOG V rain-source On-Resistance r S(on) V = V, I S = ma 4 25 r S(on) Matching Between Channels g r S(on) V = V 5 5 % Source Off Leakage Current I S(off) V S = V, V = V V = V rain Off Leakage Current I (off) V S = V V = V V = V rain On Leakage Current I (on) Sequence Each V S = V = V Switch On igital Control Logic High Input Voltage V INH Logic Low Input Voltage V INL.8.8 V Logic High Input Current I AH V A = 2.4 V, 5 V Logic Low Input Current I AL V = V, 2.4 V, V A = V A Logic Input Capacitance C in f = MHz 8 pf ynamic Characteristics Transition Time t TRANS See Figure Break-Before-Make Interval t OP See Figure ns Enable Turn-On Time t ON() See Figure Enable Turn-Off Time t OFF() Charge Injection Q C L = nf, V S = V pc Off Isolation h V OIRR = V, R L = k 75 db f = khz G48 G49 G48 G49 Source Off Capacitance C S(off) V = V, V S = V, f = MHz 3 G48 26 rain Off Capacitance C (off) V = V, V = V G49 4 pf f = MHz G48 37 rain On Capacitance C (on) G49 25 Power Supplies na Positive Supply Current I+ Negative Supply Current I Positive Supply Current I+ Negative Supply Current I V = V A = V or 5 V V = 2.4 V, V A = V A ma 5 5 A 5-3

4 Test Conditions Unless Otherwise Specified A Suffix 55 to 25 C Suffix 4 to 85 C Parameter Analog Switch Symbol = 2 V, V = V V AL =.8 V, V AH = 2.4 V f Temp b Typ c Min d Max d Min d Max d Unit rain-source On-Resistance e, f r S(on) V = 3 V, V, I S = ma 9 ynamic Characteristics Switching Time of Multiplexer e t TRANS V S = 8 V, V S8 = V, V IN = 2.4 V 8 Enable Turn On Time e t ON() VINH = 2.4 V, V INL = V Enable Turn Off Time e t V S = 5 V OFF() 8 ns Charge Injection e Q C L = nf, V S = 6 V, R S = 5 pc Notes a. Refer to PROCESS OPTION FLOWCHART. b. = 25 C, = as determined by the operating temperature suffix. c. Typical values are for ESIGN AI ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function. g. r S(on) = r S(on) Max r S(on) Min. h. Worst case isolation occurs on Channel 4 do to proximity to the drain pin. 5-4

5 8 6 Source/rain Capacitance vs. Analog Voltage = 5 V V = 5 V C (on) 6 4 rain Leakage Current vs. Source/rain Voltage (Single 2-V Supply) V S = V for I (off) V S = V for I (on) G49 I (off) G48 I (off) CS, (pf) 4 C (off) (pa) I G49 I (on) C S(off) 4 G48 I (on) V ANALOG Analog Voltage (V) V rain Voltage (V) 2 rain Leakage Current vs. Source/rainVoltage = 5 V V = 5 V 6 V S = V for I (off) V = V S(open) for I (on) 5 Source Leakage Current vs. Source Voltage (pa) I G49 I (off) (na) I S(off) 5 = 5 V V = 5 V 6 G49 I (on) G48 I (on), I (off) 5 = 2 V V = V V or V S rain or Source Voltage (V) V S Source Voltage (V) V TH (V) Input Switching Threshold vs. Supply Voltage ÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉ ÉÉ ÉÉ É É I Negative Supply Current vs. Switching Frequency ma V SUPPLY = 5 V ma ma V = 2.4 V A A.5 A V = V or 5 V V SUPPLY (V). A k k k M M Switching Frequency (Hz) 5-5

6 Positive Supply Current vs. Switching Frequency ma V SUPPLY = 5 V ma ma I+ I SUPPLY vs. Temperature ma ma I+ ma V = 2.4 V I+, I na na A V = V or 5 V na pa (I ) V SUPPLY = 5 V V A = V V = V A k k k M M pa Switching Frequency (Hz) Temperature ( C) Positive Supply Current vs. Temperature (G48) Charge Injection vs. Analog Voltage C L =, pf V IN = 5 Vp-p I+ ( A) 5 5 = 5 V V = 5 V V IN = V V = V Q (pc) = 5 V V = 5 V = 2 V V = V Temperature ( C) V S Source Voltage (V) r S(on) vs. V and Supply 6 r S(on) vs. V and Supply (Single Supply) 5 V 4 = 7.5 V rs(on) ( ) V V 2 V rs(on) ( ) 8 6 V 2 V 5 V V V 5 V 4 V = V 22 V V rain Voltage (V) V rain Voltage (V) 5-6

7 rs(on) ( ) r S(on) vs. V S and Temperature C 4 C V S Source Voltage (V) = 5 V V = 5 V 25 C 85 C 25 C 55 C rs(on) ( ) r S(on) vs. V S and Temperature (Single Supply) C 25 C 85 C 25 C C 4 C V S Source Voltage (V) = 2 V V = V (db) Off Isolation and Crosstalk vs. Frequency Off-Isolation = 5 V V = 5 V R L = k LOSS (db) 2 3 Insertion Loss vs. Frequency = 5 V V = 5 V Ref. Vrms R L = k 7 5 Crosstalk 4 5 R L = 5 3 k k k M M f Frequency (Hz) M 6 k k k M M M f Frequency (Hz) Switching Time vs. Bipolar Supply 275 Switching Time vs. Single Supply 75 t TRANS t (ns) 5 t (ns) t TRANS t OFF() 5 t OFF() t ON() 25 t ON() V SUPPLY (V) V SUPPLY (V) 5-7

8 GN V REF A X Level Shift ecode/ rive V S S n V FIGURE. S V GN G48 S 2 S 7 V S 8 V V 35 pf Logic Input 3 V V 5% t r < ns t f < ns Switch Output V S 9% V S S a S 4a, a V V S8 t TRANS S ON 9% S 8 ON t TRANS G49 S 4b V b GN V V 35 pf FIGURE 2. Transition Time 5-8

9 S 5 V 5 S 2 S A 8 G48 GN V k 5 V 35 pf Logic Input 3 V V t ON() V 5% t r < ns t f < ns t OFF() % S b 5 V Switch Output 9% S a S 4a, a S 2b S 4b 5 G49 b GN V k 35 pf 5 V FIGURE 3. Enable Switching Time +2.4 V 5 G48 G49 All S and a GN V b, 5 V 3 +5 V 35 pf Logic Input Switch Output 3 V V V S V 5% 8% t OP t r < ns t f < ns FIGURE 4. Break-Before-Make Interval 5-9

10 R g S X Logic Input 3 V V OFF ON OFF Channel Select GN V 5 V C L nf Switch Output is the measured voltage due to charge transfer error Q, when the channel turns off. Q = C L x FIGURE 5. Charge Injection V S V IN S X V S V IN S S X R g = 5 S 8 R g = 5 S 8 GN V R L k GN V R L k 5 V 5 V Off Isolation = log UT V IN Crosstalk = log UT V IN FIGURE 6. Off Isolation FIGURE 7. Crosstalk V S S R g = 5 GN V R L k Channel Select A GN S S 8 V Meter HP492A Impedance Analyzer or Equivalent f = MHz 5 V Insertion Loss = log UT V IN 5 V FIGURE 8. Insertion Loss FIGURE 9. Source rain Capacitance 5-

11 Overvoltage Protection A very convenient form of overvoltage protection consists of adding two small signal diodes (N448, N94 type) in series with the supply pins (see Figure ). This arrangement effectively blocks the flow of reverse currents. It also floats the supply pin above or below the normal or V value. In this case the overvoltage signal actually becomes the power supply of the IC. From the point of view of the chip, nothing has changed, as long as the difference V S (V ) doesn t exceed +44 V. The addition of these diodes will reduce the analog signal range to V below and V above V, but it preserves the low channel resistance and low leakage characteristics. N448 V g S X G48 N448 V FIGURE.Overvoltage Protection Using Blocking iodes 8-Channel Sequential Multiplexer/emultiplexer 5 V ifferential 4-Channel Sequential Multiplexer/emultiplexer 5 V Analog Inputs (Outputs) GN V S S 2 S 3 S 4 G48 S 5 S 6 S 7 S 8 Analog Output (Input) ifferential Analog Inputs (Outputs) GN V S a S 2a S 3a a S 4a G49 S b S 2b b S 3b S 4b ifferential Analog Outputs (Inputs) Clock In NC Enable In M7493 B IN (MUX On-Off Control) Q B Q C Q J Q J Q A IN Q NC Clock /2 MM74C73 /2 MM74C73 A r r 2 GN In CLK CLK K Q NC K Q CLEAR GN CLEAR Reset Enable 6 NC FIGURE. 5-