IH5341, IH5352. Dual SPST, Quad SPST CMOS RF/Video Switches. Description. Features. Ordering Information. Applications. Pinouts.

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1 SEMICONDUCTOR IH, IH2 December Features Description Dual SPST, Quad SPST CMOS RF/Video Switches R DS(ON) < Ω Switch Attenuation Varies Less Than db From DC to 00MHz "OFF" Isolation > 0dB Typical at 0MHz Cross Coupling Isolation > 0dB at 0MHz Compatible With TTL, CMOS Logic Wide Operating Power Supply Range Power Supply Current < µa Break-Before-Make Switching Fast Switching (80ns/0ns Typ) Applications Video Switch Communications Equipment Disk Drives Instrumentation CATV The IH (IH2) is a dual (quad) SPST, CMOS monolithic switch which uses a Series/Shunt ( T switch) configuration to obtain high OFF isolation while maintaining good frequency response in the ON condition. Construction of remote and portable video equipment with extended battery life is facilitated by the extremely low current requirements. Switching speeds are typically t ON = 0ns and t OFF = 80ns. Break-Before-Make switching is guaranteed. Switch ON resistance is typically 0Ω - 0Ω with ±V power supplies, increasing to typically Ω for ±V supplies. Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE IHCPD 0 o C to +0 o C Lead Plastic DIP IHITW -2 o C to +8 o C 0 Pin TO-00 Can IHMTW - o C to +2 o C 0 Pin TO-00 Can IHMTW/88B - o C to +2 o C 0 Pin TO-00 Can IH2CPE 0 o C to +0 o C Lead Plastic DIP IH2IJE -2 o C to +8 o C Lead Ceramic DIP IH2MJE - o C to +2 o C Lead Ceramic DIP IH2MJE/88B - o C to +2 o C Lead Ceramic DIP IH2CBP 0 o C to +0 o C 20 Lead SOIC IH2IBP -2 o C to +8 o C 20 Lead SOIC Pinouts IH (PDIP) TOP VIEW IH (TO-00 CAN) TOP VIEW IH2 (CDIP, PDIP) TOP VIEW IH2 (SOIC) TOP VIEW V+ D S IN V L IN S 2 V+ D V L 0 8 I IN S I IN2 I IN S I IN S 2 8 D V+ 2 D 0 D V L I IN S I IN2 I IN S I IN D V+ 8 D 2 D S 0 V L CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright Harris Corporation - File Number

2 IH, IH2 Functional Block Diagrams IH2 S D IH I IN S D IN I IN2 S D I IN S D I IN Switches are open for a logic 0 control input, and closed for a logic control input. Schematic Diagram ( / 2 IH, / IH2) +V -V Q Q Q Q 20 Q 8 Q +V 0kΩ kω Q Q S TTL Q Q8 -V Q Q 22 -V Q Q 0 +V +V Q 2 +V kω kω Q 2 Q Q Q +V Q D -V Q Q -

3 Absolute Maximum Ratings V+ to Ground V to Ground V V L to Ground V+ to Logic Control Voltage V+ to Analog Input Voltage V+ to Current (Any Terminal) mA Storage Temperature o C to +0 o C Lead Temperature (Soldering, 0s) o C Specifications IH, IH2 Thermal Information Thermal Resistance θ JA θ JC Ceramic DIP Package o C/W o C/W TO-00 Can Package o C/W o C/W SOIC Package o C/W - Plastic DIP Package o C/W - Operating Temperature (M Version) o C to +2 o C (I Version) o C to +8 o C (C Version) o C to +0 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = +V, V L = +V, = -V, T A = +2 o C Unless Otherwise Specified. M GRADE DEVICE I/C GRADE DEVICE PARAMETER TEST CONDITIONS (NOTE ) TYP - o C +2 o C +2 o C -2 o C/ 0 o C +2 o C +8 o C/ +0 o C UNITS DC CHARACTERISTICS Supply Voltage Ranges (Note ) Positive Supply, V+ to V Logic Supply, V L to V Negative Supply, - to V Switch ON Resistance, R DS(ON) V D = ±V, I S = 0mA, 2.V (Note ) V D = ±, I S = 0mA, 2.V (Note ) Ω cd 0 0 Ω Switch ON Resistance, V+ = V L = +V, = V, R DS(ON) = -V,V D = ±V, I S = 0mA Ω On Resistance Match Between Channels, R D- S(ON) I S = 0mA, V D = ±V Ω Logic l Input Voltage, V IH > V Logic 0 Input Voltage, V IL < V Switch OFF Leakage, I D(OFF) or I S(OFF) V S/D = ±V or ±V, 0.8V (Notes 2 and ) IH - - ± ± 00 na IH2 - - ± 0 - ±2 00 na Switch ON Leakage, V S/D = ±V, 2.V IH - - ± 0 - ±2 00 na I D(ON) + I S(ON) V S/D = ±V, 2.V - - ± 00 - ±2 00 na V S/D = ±V or ±V, 0.8V IH2 - - ± 00 - ±2 00 na Input Logic Current, I IN > 2.V or < 0. ± ± 0 ± ± 0 ma Positive Supply Quiescent Current, I+ Negative Supply Quiescent Current, I- = or +V ma = or +V µa Logic Supply Quiescent = or +V µa Current, I L -

4 Specifications IH, IH2 Electrical Specifications V+ = +V, V L = +V, = -V, T A = +2 o C Unless Otherwise Specified. (Continued) M GRADE DEVICE I/C GRADE DEVICE PARAMETER TEST CONDITIONS (NOTE ) TYP - o C +2 o C +2 o C -2 o C/ 0 o C +2 o C +8 o C/ +0 o C UNITS AC CHARACTERISTICS Switch ON Time, t ON ns Switch OFF Time, t OFF ns OFF Isolation Rejection Ratio, OIRR Cross Coupling Rejection Ratio, CCRR db db Switch Attenuation db MHz Frequency, f db NOTES:. Typical values are not tested in production. They are given as a design aid only. 2. Positive and negative voltages applied to opposite sides of switch, in both directions successively.. These are the operating voltages at which the other parameters are tested, and are not directly tested.. The logic inputs are either greater than or equal to 2.V or less than or equal to 0.8V, as required, for this test. Typical Performance Curves 0 PIN = +V, PIN = -V PIN 0 = +V, T A = +2 o C 80 PIN = PIN0 = +V PIN = -V, T A = +2 o C 0 0 R DS(ON) (Ω) 0 R DS(ON) (Ω) ANALOG INPUT VOLTAGE LEVEL (V) FIGURE. R DS(ON) vs ANALOG INPUT VOLTAGE WITH ±V POWER SUPPLIES ANALOG INPUT VOLTAGE LEVEL (V) FIGURE 2. R DS(ON) vs ANALOG INPUT LEVEL WITH ±V POWER SUPPLIES 00 T A = +2 o C 00 T A = +2 o C OIRR (db) 0 0 CCRR (db) FREQUEY (MHz) FIGURE. OFF ISOLATION REJECTION vs FREQUEY (SEE FIGURE 8) FREQUEY (MHz) FIGURE. CROSS COUPLING REJECTION vs FREQUEY (SEE FIGURE ) -8

5 Typical Performance Curves (Continued) IH, IH2 SWITCH ATTENUATION (db) T A = +2 o C FREQUEY (MHz) 00 FIGURE. TYPICAL SWITCH ATTENUATION vs FREQUEY (R L = Ω, SEE FIGURE 0) Detailed Description Figure shows the internal circuit of one channel of the IH2. This is identical to the IH T-Switch configuration. Here, a shunt switch is closed, and the two series switches are open when the video switch channel is open or off. This provides much better isolation between the input and output terminals than a simple series switch does, especially at high frequencies. The result is excellent off-isolation in the Video and RF frequency ranges when compared to conventional analog switches. The control input level shifting circuitry is very similar to that of the IH0 series of Analog Switches, and gives very high speed, guaranteed Break-Before-Make action, low static power consumption and TTL compatibility. SWITCH SOURCE (VIDEO INPUT) LOGIC CONTROL INPUT DRIVER TRANSLATOR NOTE: channel of shown. SWITCH SOURCE (VIDEO OUTPUT) FIGURE. INTERNAL SWITCH CONFIGURATION Test Circuits +V V ANALOG TTL IN 00Ω R L = 2 S D IN +V -V +V 0 +V TTL INPUT +.V V ANALOG + V V ANALOG - V 0% -.V 0% ton 0% 0% t OFF 0% 0% 0% NOTE: Only one channel shown. Other acts identically. FIGURE A. SWITCHING TIME TEST CIRCUIT FIGURE. FIGURE B. SWITCHING TIME WAVEFORMS -

6 IH, IH2 Test Circuits (Continued) Ω +V +V +V +V RG- COAX 2 S D 0 IH Ω 2 S D 0 IH OPEN Ω Ω RG- COAX IN +V IN -V -V V = ± V ( )atf = 0MHz IN P P OIRR = 20log NOTE: Only one channel shown. Other acts identically. FIGURE 8. OFF ISOLATION TEST CIRCUIT V = 22m RMS at f = 0MHz CCRR = 20log FIGURE. OFF ISOLATION TEST CIRCUIT Ω +V +V 0 Ω RG- COAX RG- COAX +V 2 S D IN IH Ω -V ATTN: = 20log R L R + R DS ( ON) L Nominally, at DC, this ratio is equal to -db. When the attenuation reaches -db, the frequency at which this occurs is f db NOTE: Only one channel shown. Other acts identically. FIGURE 0. SWITCH ATTENUATION vs FREQUEY -0

7 IH, IH2 Typical Applications Charge Compensation Techniques Charge injection results from the signals out of the level translation circuit being coupled through the gate-channel and gate-source/ drain capacitances to the switch inputs and outputs. This feedthrough is particularly troublesome in Sample-and-Hold or Track-and-Hold applications, as it causes a Sample (Track) to Hold offset. The IH devices have a typical injected charge of 0pC- 0pC (corresponding to 0m0mV in a 000pF capacitor), at V S/D of about. This Sample (Track) to Hold offset can be compensated by bringing in a signal equal in magnitude but of the opposite polarity. The circuit of Figure accomplishes this charge injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a generator of a compensating signal. The kω potentiometer allows the user to adjust the net injected charge to exactly zero for any analog voltage in the -V to +V range. +V ANALOG INPUT Ω 2 S D IN +V 0 -V kω CERMET NOT WIRE WOUND* Since individual parts are very consistent in their charge injection, it is possible to replace the potentiometer with a pair of fixed resistors, and achieve less than mv error for all devices without adjustment. An alternative arrangement, using a standard TTL inverter to generate the required inversion, is shown in Figure 2. The capacitor needs to be increased, and becomes the only method of adjustment. A fixed value of 22pF is good for analog values referred to ground, while pf is optimum for AC coupled signals referred to -V as shown in the figure. The choice of -V is based on the virtual disappearance at this analog level of the transient component of switching charge injection. This combination will lead to a virtually glitch-free switch. Overvoltage Protection If sustained operation with no supplies but with analog signals applied is possible, it is recommended that diodes (such as N) be inserted in series with the supply lines to the IH. Such conditions can occur if these signals come from a separate power supply or another location, for example. The diodes will be reverse biased under this type of operation, preventing heavy currents from flowing from the analog source through the IH. The same method of protection will provide over 2V overvoltage protection on the analog inputs when the supplies are present. The schematic for this connection is shown in Figure. +V N µf 2 S +V 0 Ω D 0pF IN C HOLD 000pF +V TTL IN (STROBE) µf * Adjust pot for 0mV P-P steip at with no analog (AC) signal present. FIGURE. CHARGE INJECTION COMPENSATION N -V µf FIGURE. OVERVOLTAGE PROTECTION +V +V DC BIAS VOLTAGE = -V ANALOG INPUT Ω µf 2 S D IN 0 2 SN V 22pF-pF -V 8 C HOLD 000pF +V TTL CONTROL IN +V FIGURE 2. ALTERNATIVE COMPENSATION CIRCUIT -

8 IH Die Characteristics DIE DIMENSIONS: 288µm x 2µm METALLIZATION: Type: Al Thickness: 0kÅ ± kå GLASSIVATION: Type: PSG/Nitride PSG Thickness: kå ±.kå Nitride Thickness: 8kÅ ±.2kÅ WORST CASE CURRENT DENSITY:. x 0 A/cm 2 Metallization Mask Layout IH D V+ (SUBSTRATE) S IN V L -2

9 IH2 Die Characteristics DIE DIMENSIONS: 2µm x 2µm METALLIZATION: Type: Al Thickness: 0kÅ ± kå GLASSIVATION: Type: PSG/Nitride PSG Thickness: kå ±.kå Nitride Thickness: 8kÅ ±.2kÅ WORST CASE CURRENT DENSITY:. x 0 A/cm 2 Metallization Mask Layout IH2 S IN D V+ (SUBSTRATE) IN D S IN D S V L -

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118. Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,