NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset

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NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic

1 NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP type package. The flip flop changes state with the positive transition of Clock (1CP and 2CP). The flip flip is set and reset by active low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. Features: Asynchronous Set and Reset Schmitt Trigger Clock Inputs Typical Propagation Delay: 18ns (typ) Fanout (Over Temperature Range): Standard Outputs LS TTL Loads Bus Driver Outputs LS TTL Loads Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LS TTL Logic ICs Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, to +7.0V Clamp Diode Current, I IK, I OK... ±20mA DC Output Current (Per Pin), I OUT... ±25mA DC or GND Current (Per Pin), I CC... ±50mA Maximum Junction Temperature, T J C Storage Temperature Range, T stg C to +150 C Typical Thermal Resistance, Junction to Ambient (Note 3), R thja C/W Lead Temperature (During Soldering, 10sec), T L C Note 1. Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the Recommended Operating and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the Recommended Operating may effect device reliability. The Absolute Maximum Ratings are stress ratings only. Note 2. Unless otherwise specified, all voltages are referenced to GND. Note 3. R thja is measured with the component mounted on an evaluation PC board in free air.

2 Recommended Operating : Min Typ Max Supply Voltage V DC Input or Output Voltage V IN, V OUT 0 V Operating Temperature Range T A C C P Input Rise or Fall Times = 2.0V t r, t f 1.0 ms = 4.5V 1.0 ms = 6.0V 1.0 ms Input Rise or Fall Times (All Inputs Except C P ) = 2.0V t r, t f 1000 ns = 4.5V 500 ns = 6.0V 400 ns DC Electrical Characteristics: High Level Input Voltage V IH V V V Low Level Input Voltage V IH V High Level Output Voltage CMOS Loads TTL Loads Low Level Output Voltage CMOS Loads TTL Loads V OH V IN = V IH or V IL, I O = 0.02mA V V V V V V I = V IH I O = 4mA V or V IL I O = 5.2mA V V OL V IN = V IH or V IL, I O = 0.02mA V V V V IN = V IH I O = 4mA V or V IL I O = 5.2mA V Input Leakage Current I IN V IN = or GND 6.0 ±0.1 ±1.0 ±1.0 μa Quiescent Supply Current I CC V IN = or GND, I O = 0mA μa Prerequisite for Switching Characteristics: Setup Time J, K, to CP t SU ns

3 Prerequisite for Switching Characteristics (Cont d): Hold Time J, K, to CP t H ns ns ns Removal Time R, S, to CP t REM ns Pulse Width CP, R, S t W ns CP Frequency f MAX MHz MHz MHz Switching Characteristics: (t r = t f = 6ns) CP to Q, Q S to Q S to Q R to Q R to Q t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns C L = 50pF ns C L = 15pF ns C L = 50pF ns Transition Times t TLH, t THL C L = 50pF ns ns ns

4 Switching Characteristics (Cont d): (t r = t f = 6ns) Input Capacitance C IN pf CP Frequency f MAX C L = 15pF MHz Power Dissipation Capacitance C PD Note pf Note 4. C PD is used to determine the dynamic power consumption, per flip flop. P D = 2 f I + Σ + C L f O where f I = input frequency, f O = output frequency, C L = output load capacitance, = supply voltage. Truth Table: Inputs Output S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H (NOTE) H (NOTE) H H L L L H H H H L Toggle H H L H No Change H H H H H L H H L X X No Change H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Don t Care = Low to High Transition NOTE: Unpredictable and unstable condition if both S and R go high simultaneously. Pin Connection Diagram 1 R 1 J 1 K 1 CP 1 S R 14 2 J 13 2 K 12 2 CP 1 Q S 1 Q Q GND Q

5 (22.0) Max.260 (6.6) Max.200 (5.08) Max.100 (2.54).099 (2.5) Min.700 (17.78)

NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output

NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability