NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register

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Reynold Booth
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NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type

1 NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package that utilize advanced silicon gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits along with the ability to drive 10 LS TTL loads. This 8 bit serial shift register shifts data from Q A to Q H when clocked. Parallel inputs to each stage are enabled by a low level at the SHIFT/LOAD input. Also included is a gated CLOCK input and a complementary output from the eighth bit. Clocking is accomplished through a 2 input NOR gate permitting one input to be used as a CLOCK INHIBIT function. Holding either of th CLOCK inputs high inhibits clocking, and holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the SHIFT/LOAD input is HIGH. When taken LOW, data at the parallel inputs is loaded directly into the register independent of the state of the clock. The 74HC logic family is functionally as well as pin out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by diodes to V CC and GND. Features: Typical Propagation Delay: Clock to Q: 20ns Low Quiescent Current: 80 A (max) Low Input Current: 1 A (max) Wide Power Supply Range: 2V to 6V Fanout to 10 LS TTL Loads Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, V CC to +7.0V DC Input Voltage, V IN to V CC +1.5V DC Output Voltage, V OUT to V CC + 0.5V Clamp Diode Current, I IK, I OK... 20mA DC Output Current (Per Pin), I OUT... 25mA DC V CC or GND Current (Per Pin), I CC... 50mA Power Dissipation (Note 3), P D mW Storage Temperature Range, T stg C to +150 C Lead Temperature (During Soldering, 10sec), T L C Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2. Unless otherwise specified, all voltages are referenced to GND. Note 3. Power Dissipation temperature derating: 12mW/ C from +65 C to +85 C.

2 Recommended Operating Conditions: Parameter Symbol Min Typ Max Supply Voltage V CC V DC Input or Output Voltage V IN, V OUT 0 V CC V Operating Temperature Range T A C Input Rise or Fall Times V CC = 2.0V t r, t f 1000 ns V CC = 4.5V 500 ns V CC = 6.0V 400 ns DC Electrical Characteristics: (Note 4 unless otherwise specified) Minimum High Level Input Voltage V IH V V V Maximum Low Level Input Voltage V IL V V V Minimum High Level Output Voltage V OH V IN = V IH or V IL I OUT 20 A V CC V CC 0.1 V CC 0.1 V I OUT 4.0mA V I OUT 5.2mA V Minimum Low Level Output Voltage V OL V IN = V IH I OUT 20 A V I OUT 4.0mA V I OUT 5.2mA V Maximum Input Current I IN V IN = V CC or GND A Maximum Quiescent Supply Current I CC V IN = V CC or GND, I OUT = 0 A A Note 4. For a power supply of 5V 10% the worst case output voltages (V OH and V OL ) occur at 4.5V. Thus, the 4.5V values should be used when designing with this supply. Worst case V IH and V IL occur at V CC = 5.5V and 4.5V respectively (The V IH value at 5.5V is 3.85V). The worst case leakage current (I IN, I CC and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. AC Electrical Characteristics: (V CC = 5V, t r = t f = 6ns, C L = 15pF, unless otherwise specified) Typ Guaranteed Limits Maximum Operating Frequency f MAX ns (H to Q H or Q H ) t PHL, t PLH ns (Serial Shift/Parallel Load to Q H ) t PHL, t PLH ns (Clock to Output) t PHL, t PLH ns Minimum Set Up Time (Serial Input to Clock, Parallel or Data to Shift/Load) t S ns

3 AC Electrical Characteristics (Cont d): (V CC = 5V, t r = t f = 6ns, C L = 15pF, unless otherwise specified) Typ Guaranteed Limits Minimum Set Up Time (Shift/Load to Clock) t S ns Minimum Set Up Time (Clock Inhibit to Clock) t S ns Minimum Hold Time (Serial Input to Clock or Parallel Data to Shift/Load) t H 0 ns Minimum Pulse Width (Clock) t W 16 ns AC Electrical Characteristics: (t r = t f = 6ns, C L = 50pF unless otherwise specified) Maximum Operating Frequency f MAX MHz (Delay H to Q H or Q H ) (Delay Serial Shift/Parallel Load to Q H ) (Delay Clock to Output) (Serial Input to Clock, or Parallel Data to Shift/Load) (Shift/Load to Clock) (Clock Inhibit to Clock) Minimum Hold Time (Serial Input to Clock, or Parallel Data to Shift/Load) MHz MHz t PHL, t PLH ns ns ns t PHL, t PLH ns ns ns t PHL, t PLH ns ns ns t S ns ns t S ns ns t S ns ns t H ns ns ns Minimum Pulse Width, Clock t W ns ns ns Maximum Output Rise and Fall Time t THL, t TLH ns ns ns

4 AC Electrical Characteristics (Cont d): (t r = t f = 6ns, C L = 50pF unless otherwise specified) Maximum Input Rise and Fall Time t r, t f ns ns ns Power Dissipation Capacitance C PD Per Package, Note pf Maximum Input Capacitance C IN pf Note 5. C PD determines the no load dynamic power consumption, P D = C PD V CC 2 f + I CC V CC, and the no load dynamic current consumption, I S = C PD V CC f + I CC. Truth Table: Inputs Internal Shift/ Clock Parallel Outputs Output Load Inhibit Clock Serial A... H Q A Q A Q H L X X X a...h a b h H L L X X Q A0 Q B0 Q H0 H L H X H Q AN Q GN H L L X L Q AN Q GN H H X X X Q A0 Q B0 Q H0 H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Irrelevant (any input, including transitions) = Transition from LOW to HIGH level Q AO, Q BO, Q HO = the level of Q A, Q B, or Q H, respectively, before the indicated steady state input conditions were established. Q AN, Q GN = the level of Q A or Q G before the most recent transition of the clock; indicated a one bit shift. Pin Connection Diagram Shift/Load Clock Parallel Input E Parallel Input F Parallel Input G Parallel Input H Output Q H GND V CC Clock Inhibit 14 Parallel Input D 13 Parallel Input C 12 Parallel Input B 11 Parallel Input A 10 Serial Input 9 Output Q H

5 (22.0) Max.260 (6.6) Max.200 (5.08) Max.100 (2.54).099 (2.5) Min.700 (17.78)

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs

NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that